PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 1 OF 11

4 3 2 1

REVISIONS
REV ECO DESCRIPTION BY/DATE CHK/DATE
+13VDC EA . PROTOTYPE RELEASE TDW/01NOV99 .
9) Power & Watchdog
EB . USED MAIN 5 VOLTS FOR U62 PULLUPS TDW/08NOV99 .
AGND COIL GNDA TT-BACKUP
MAINDOOR DET A 5043 PRODUCTION RELEASE TDW/27DEC99 .
BILLVAL DET
DOORVAL OUT
+25VDC DROPDOOR DET
CARDCAGE DET
BGND COIL GNDB RESET MEZZ
4) QUARTs & I/O
+13VDC +13VDC PA RESET\
For Reference SPEAKER- PA RESET J4
D SPEAKERA+ CCAGE OPEN\ D
A1
CCAGE OPEN DDOOR OPEN\ CCAGE OPEN 1A
A2
JKPT RST DDOOR OPEN MDOOR OPEN\ DDOOR OPEN 1C
A3
MDOOR OPEN BVAL OPEN\ MDOOR OPEN 2A
A4
PROG TxDg BVAL OPEN BVAL OPEN 2C
J2 A5
+13VDC PROG RxDg TT-DET\ WCHDOG SEL 3A
A6
1A +13VDC TT-DET TT-DISABLE\ TT-DET 3C
A7
1B GNDA ( To NETPLEX Ground ) RxDf TT-DISABLE TT-CNTR1 TT-DISABLE 4A
A8
2A TxDf TT-CNTR1 TT-CNTR2 TT-CNTR1 4C
A9
2B SPEAKER- TT-CNTR2 TT-CNTR2 5A
A A10
3A TT-BACKUP
LPSW INTERROGATE 5C
A11
3B SPEAKERA+ INTERROGATE INTERROGATE 6A
A12
4A SPEAKERB+
NETPLEX TxD SRAM BAT LOW\ 6C
A13
4B MAINDOOR DET\ NETPLEX RxD SRAM BAT LOW TT BAT LOW\ SRAM BAT LOW 7A
A14
5A BILLVALDET\ TT BAT LOW RESET\ CPU/SEN/AUD TT BAT LOW 7C
A15
5B DOORVALOUT RESET CPU/SEN/AUD RESET\ I/O RESET CPU/SEN/AUD 8A
A16
6A DROPDOOR DET\ RESET I/O RESET I/O 8C
RESET CPLD/F/O A17
6B JKPT RST RESET QUART RESET CPLD/F/O 9A
CE\OUT A18
7A CARDCAGE DET\ I/O RESET RESET QUART RESET QUART CEOUT 9C
RESET\ SIMM A19
7B PROG TxDg TxDd RESET SIMM 10A
VOUT A20
8A PROG RxDg TxDd RxDd TxDd VOUT 10C
A21 J11
8B RxDf DCS TxDh RxDd RxDd 11A RESET\
A22
9A LPSW
DCS RxDh T T T T
11C INT1\ 1
ISP (OPTIONAL) A23
9B NETPLEXRxD M D D C +13VDC LOW 12A 2
VBATT A24 BOOTSEL\
10A TxDf S I O K J10 VBATT 12C 3
INT2 A25 GAMESEL\
10B I/O RESET\ INT2 13A 4
A26 VBIT SEL\
11A 13C 5

1
2
3
4
5
6
7
8
9
NETPLEXTxD PAGE 9 IO RD\ VOUT
11B DCS TxDh RESET VIDEO 14A 6
IO WR\ CE\OUT
12A DCS RxDh
14C 7
VCC SLVSEL\ PASEL\
12B 15A 8

ISP2

ISP1
ISP6

ISP3
SRESET\ D0 WR0\
13A SIN IN
SRESET 15C WR1\ 9
D1
13B SIN IN D2
16A 10
COMM TxDc
14A COMM TxDc 2) CPU 16C
COMM RxDc D3 10 PIN
14B COMM RxDc INT0\ 17A
COMM RTS D4
15A COMM CTS COMM RTS INT0 INT0 17C
D5
15B TxDb
COMM CTS VERTOUT INT1 MM CLK 18A
D6
16A RxDb VERTOUT INT3\ INT2 S ALE 18C
D7
16B TxDb INT3 A25\ INT3 SLV SEL 19A
D8
RxDb A25 A[1..31] A25 19C
32 PIN DIN D9
A[1..31] A[1..31] 20A
C D10 C
POWER SAVE 20C

(14.74560MHz)
ISP[1..6] D11
ISP[1..6] MEZRDY 21A
D12
RxDa D[0..15] MEZ1 SEL 21C
D13
DTR 22A
D14
TxDa IA[1..3] IA[1..3] 22C
D15
DIR 23A
PD0
R191 DCD PD[0..7] PD[0..7] 23C
FWR EN\ PD1
FWR EN 24A
1 2 PD2
RESET CPLD/F/O 24C
PD3 J5
0 OHM IO RD IO RD 25A
B A SCLK256 PD4
3 Amps SCLK256 IO WR IO WR 25C FWR0A\
QUART CLK PD5
QUART CLK QRT1 SEL\ QUART CLK 26A 1A
PD6 RESET MEZZ
QRT1 SEL QRT2 SEL\ WR1 26C 1C
PD7 INT1\
QRT2 SEL OUT SEL\ WR0 27A 2A
BBSTB IA1 MM CLK
OUT SEL SOUND SEL\ BBSTB 27C 2C
IA2 SALE
SOUND SEL BLTRDY 28A 3A

PD[0..7]
MM AUDIO1 IA3 MEZ2SEL\
MM AUDIO1 RESET CPU/SEN/AUD 28C 3C
GND MEZRDY\
IO2B2 FAILURE BITBLITZ SEL GND
29A 4A
MEZ1SEL\
+25VDC IO2B2 IO3B3 BLT CLK 29C +13VDC
4C
SYSCLK
IO3B2 OUT5 SENRDY SYS CLK 30A +13VDC
5A
RD\
OUT5 OUT6 30C +25VDC 5C
IOT SEL\ WR0\
VCC OUT6 IOT SEL 31A +25VDC 6A
PAGE 4 FLH SEL\ WR1\

OUT7

D[0..15]
OUT7 BITBLITZ CLK FLH SEL 31C 6C
VCC PX0
MM[1..5] RAM SEL 32A 7A

IA[1..3]
J1 +5VDC
PX1
RD 32C 7C

DWG NO:
(VCC GND PLANE) PX2
1A +5VDC 5) SENET PA SEL 8A
PAGE 2 PX3
1B EPR SEL 8C

PA SEL\
SCL PX4
2A SCL IO2B2 9A
SDA PX5
2B SDA IO3B2 9C
POWERSAVE PX6

757 039 11
3A SENSTB OUT5 10A
RxDa PX7
3B SENCLK OUT6 10C
DTR
4A SDATA TxA OUT7 11A
AUSTRALIAN TxDa
4B SDATA RxA FAILURE 11C
SLOT DIR
5A SDATA ADR FAILURE 12A
DCD

RESERVED FOR MULTIMEDIA

CONNECTION 5B SDATA TxB SYS CLK 12C
USART TXD
N/C-------------------- 6A SENRST 13A
LPSTB\ SENRDY\
MECH SW---------- 6B SENRDY 13C

EPR SEL\
N/C--------------------- USART RXD
7A +13VDC 3) Main Memory 14A
DET 1----------------- 7B RESET CPU/SEN/AUD 14C

20 PINS
USART CLK
B LPSTB\--------------- 8A A[1..31] 15A B
DET2------------------ 8B EPR SEL 15C
GNDA
GND------------------- 9A PAGE 5 PD[0..7] A[1..31] RAM SEL 16A
TO CARD CAGE SWITCH A
CARDCAGE DET 9B FLH SEL 16C
SENSTB\
SENSTB\------------ 10A IO RD D[0..15] IOT SEL 17A
SENCLK MEZ2 SEL\
SENCLK-------------- 10B IO WR VBATT MEZ2 SEL 17C
SDATATxA BOOTSEL\
SDATA TxA--------- 11A SCLK256 QRT1 SEL BOOT SEL 18A
SDATARxA SENET SEL\
SDATA RxA-------- 11B SENET SEL QRT2 SEL 18C
SDATA ADR-------- SDATA ADR GAMESEL\
12A OUT SEL GAME SEL 19A
SDATATxB VBIT SEL\
SDATA TxB--------- 12B CONNECTED TO U71 (5) SOUND SEL VBIT SEL 19C
SENGND VOUT
SENGND------------- 13A IO RD VOUT 20A
SENRST\ FWR0A\
SENRST\------------ 13B IO WR FWR0A 20C
GNDB FWR1A\
GNDB----------------- 14A FWR EN FWR1A 21A
GNDB RAM SEL\ MM AUDIO1
GNDB----------------- 14B E22 RD 21C
MM BLUE B
L6-4-------------------- 15A RESET SIMM 22A
MM RED
V REEL6------------ 15B SENET SEL FWR1A\ 22C
MM HORIZ AUDIO
L6-1------------------- 16A 7) Video BLOCK & VDAC FWR0B CEOUT 23A
MM GREEN SPEAKERB+
DET 6----------------- 16B FWR1B SCL 23C
L6-3------------------- V GND WCHDOGSEL\
17A A[1..31] WCHDOG SEL SDA 24A
MM VERT
L6-2------------------- 17B ISP[1..6] VBLK0 SEL 24C
+25VDC USART TXD
+25VDC------------- 18A IA[1..3] VBLK1 SEL WR0 NORMAL STRAPPING: 25A
USART RXD
+25VDC------------- 18B WR1 1-15,3-13, 4-12, 25C
COLORSEL\ USART CLK
DET 3----------------- 19A COLOR SEL COLOR SEL 5-6 & 7-8 26A
V REEL1------------ VCC RED V GND
19B RED IO RD PAGE 3 MULTI-MEDIA STRAPPING: 26C
BLUE RED
DET 5----------------- 20A RESERVED BLUE IO WR 15-16, 13-14, 11-12, 27A
GREEN GREEN
3

V REEL2------------ 20B FOR GREEN PD[0..7] 6-10 & 8-9 27C TO

PX[0..7] BLUE
L1-2-------------------- 21A SLOT CR9 CR10 CR8 PX[0..7] 28A MULTI-MEDIA
DOT CLK
V REEL3------------ 21B 28C
X1 BLANK2
1N914

1N914

1N914

DET 4----------------- 22A 29A

6) BitBlitz & VDRAM RED 1 16 MM RED MM RED
V REEL4------------ 22B 29C
L1-1------------------- 23A
V GND CA0 2 15 MN RED MM GREEN
30A
CA0 CA0 FROM
1

V REEL5------------ 23B
FWR0B\ +13VDCLOW\ GREEN 3 14 MM GREEN MM BLUE
FWR0B +13VDC LOW 30C MULTI-MEDIA
L1-3-------------------- 24A
MN BLUE
FWR1B
FWR1B\
A[1..31]
BLUE 4 13 MN GREEN MM VERT
31A
MN RED BLTCLK V SYNC 5 12 MN BLUE MM HORIZ
L1-4-------------------- 24B D[0..15] D[0..15] BLT CLK 31C
MN HSYNC BITBLITZ SEL\ MN VSYNC 6 11 MM BLUE V SYNC
L2-1-------------------- 25A RD RD BITBLITZ SEL 32A
L2-2-------------------- 25B
MN GREEN RESET\ VIDEO BLTRDY\ H SYNC 7 10 MM VERT H SYNC
32C
TO MULTI-MEDIA
RESET VIDEO RESET VIDEO BLTRDY
L2-3-------------------- 26A
DOT CLK2 MN HSYNC 8 9 MM HORIZ
MN VSYNC VERTOUT BBSTB REF X1
BLOCKRW\
L2-4-------------------- 26B BLOCKRW BLOCKRW
R187 75 FLATCH1 HEADER, VIDEO 1
3

L3-1-------------------- 27A FLATCH1 FLATCH1 WR0

L3-2-------------------- 27B 1 2 FLATCH2
FLATCH2
FLATCH2 WR1
A CR14 CR15 CR13 R189 75 BLANK1 16 pin DIP Socket A
L3-3-------------------- 28A BLANK1 BLANK1
1 2 BLANK2
1N914

1N914

1N914

L3-4-------------------- 28B BLANK2 BLANK2

DD[0..7]
L4-1-------------------- 29A R188 75 DD[0..7] FD[0..15] DD[0..7] ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO INTERNATIONAL GAME TECHNOLOGY
L4-2-------------------- 29B
RESERVED 1 2 FD[0..15] FD[0..15] THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
1

FOR BD[0..15]
L4-3-------------------- 30A SLOT BD[0..15] SC-1 BD[0..15] 9295 PROTOTYPE DRIVE RENO, NV 89511
L4-4-------------------- 30B SC-1 BA0 SC-1 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
NOTES: (UNLESS OTHERWISE INDICATED) V TITLE
L5-1-------------------- 31A BA0 BA0 INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
BA1
L5-2-------------------- 31B BA1 BA1
L5-3-------------------- 32A 28PINS
1. ALL RESISTORS EXPRESSEDINOHMS1/4W5% PAGE 7 DOT CLK
DOT CLK
DOT CLK BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED SCHEMATIC, GAME KING 2
ALL CAPACITORS EXPRESSED IN MICROFARADS 256COLOR\
L5-4-------------------- 32B 256COLOR 256COLOR BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
VBLK0 SEL\ BITBLITZ CLK
64 PIN DIN 2. ALL 14 PIN ICS, PIN 14 IS PWR, PIN 7 IS GND
VBLK0 SEL
VBLK1 SEL
VBLK1 SEL\ BITBLITZ CLK
LPSTB CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
ALL 16 PIN ICS, PIN 16 IS PWR, PIN 8 IS GND H SYNC
H SYNC COVENANTS IT WILL NOT BE USED IN ANY MANNER
ALL 20 PIN ICS, PIN 20 IS PWR, PIN 10 IS GND BLOCK DWG. SIZE DWG. NO. REV LTR
BLOCK BLOCK
FID1 FID2 FID3 V SYNC
V SYNC PAGE 6 DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
FOR PCB USEONLY
3. JUMPER OPTIONS SHOWN ONPAGE2
DOT CLK2 RETURNED ON DEMAND. C 757 039 11 A
FIDUCIAL DRAWN DATE CHECKED DATE APPROVED DATE SCALE
ISP[1..6]
TDW 01NOV99 NONE 1 OF 11
SHT __ __
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 19
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 2 OF 11

4 3 2 1
R71
1 2 VCC
10K
U26
VCC VCC A27 1 15 EPR SEL\ 0000 0000h EPR SEL\
A Y0 (1,3)
RP13 A28 2 14 FLH SEL\ 0800 0000h FLH SEL\
B Y1 (1,3)
1 A29 3 13 RAM SEL\ 1000 0000h RAM SEL\
C Y2 (1,3)
A24 2 12 BLT SEL\ 1800 0000h BITBLITZ SEL\
Y3 (1,6)
A25 3 11 SLV SEL\ 2000 0000h SLV SEL\

8
7
6
5
Y4 J4,15A (1)
A26 4 6 10 IO SEL\ 2800 0000h
RP6 G1 Y5 PA SEL\ 3000 0000h PA SEL\
A27 5 A30 4 G2A Y6 9 (1)
A28 6 A31 5 7 MEZZ1 SEL\ 3800 0000h MEZ1 SEL\
10K G2B Y7 J5,4C (1)
A30 7
A29 8 74HC138
R83 1K

1
2
3
4
A31 9 VCC 1 2
10 VCC
R85 1K
1 2
10K 1 2
R83, R85, R89, R101 and R66 R89 1K
D R96 1 2 D
INT0\ from QUART #2 ARE NOT USED AT THIS TIME R65 10K
(1,4) 1 2
R101 1K
U18A RP5 1 2 1 2
100 1
INT1\ from MULTIMEDIA VCC RP4 VCC R66 1K R99 10K
(1) 1 2 RP9 A9 2 1 2
1 1 A10 3 1 2
74HC14 A16 2 2 A1 A11 4
INT2 Low +13VDC U29 R94 10K
(1,9) A17 3 3 A2 A12 5 OPT 0 5
A18 4 VCC 4 A3 A13 6 39 1 2
CLK OPT 1
R72 A19 5 5 A4 A14 7 6 CLK OPT 2 40 R86 10K
INT3\ from QUART #1 1 2 A20 6 6 A5 A15 8 EPR SEL\ 2 43
(1,4) EPROMSEL RAMNW
A21 7 7 A6 9 RAM SEL\ 3 44 1 2
100 U3B
TP
MEZ1 SEL\ RAMSEL OPT 4
A22 8 8 A7 10 4 MEZ1SEL
WR R82 10K
A23 9 9 A8 7 24 SYS CLK (1,5)
A25\ 10K BITBLITZ SEL\ WR SYSCLK
(1,4) 4 3 A25 10 10 8 25 IOT SEL\ (1,3)
BITSEL IOTSEL

17
21
31
33
44
47
53
71
73

62
SLV SEL\ 9 26 BBSTB

6
1
SLVSEL BBSTB (1,6)
10K 10K IO SEL\ 11 27 WR0\
IOSEL WR0 (1,3,6,10)
74HC04 ALE 12 28 RESET CPLD/F/O

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
ALE RESET (1,9)
A16 16 41 D0 AS\ 13 29 RD\
A16 D0 AS RD (1,3,6,7,10)
A17 15 40 D1 BLAST\ 14 38 IO WR\
A17 AD1 BLAST IO_WR (1,3,4,5,7,11)
A18 14 39 D2 READY\ 22 33 IO RD\
A18 AD2 RDY IO_RD (1,3,4,5,7)
A19 13 38 D3 DEN\ 1 34 FAILURE
A19 AD3 DEN FAIL (1,5)
VCC A20 12 37 D4 BE0\ 37 35 S ALE (1)
A20 AD4 BE0 SALE J5,3A
A21 11 36 D5 BE1\ 18 36 WR1\ (1,3,6,10)
A21 AD5 FLH SEL\ BE1 WR1
A22 10 A22 AD6 35 D6 20 NC
A23 9 30 D7 15 ISP1
A23 AD7 TDI ISP2
A24 8 29 D8 16

2
A24 AD8 TMS ISP3
A25 5 A25 AD9 28 D9 19 IO_EN TCK 17
A26 4 27 D10 42 30 ISP4
R64 R59 A26 AD10 EXTRDY TDO
A27 3 A27 AD11 26 D11
10K 910 A28 83 25 D12 E17 XC9536, BUSS CONTROLLER
A28 AD12
A29 82 A29 AD13 24 D13 ISP[1..6]

1
A30 81 A30 AD14 20 D14 (1,6,7)
A31 80 A31 AD15 19 D15
BLTRDY\ (1,6)
57 INTO ALE 78
58 68 R88 10K
INT1 DT/R
59 INT2/INTR DEN 67 10 1 2
C
60 INT3/INTA A1 49 A1 2 8 74AC32 C
RESET\ CPU/SEN/AUD 46 A2 3 9 1 2
(1,4,5,9,11) A2 74AC32
70 45 A3 1 U42C
LOCK A3 U42A R93 10K
64 SENRDY\ (1,5)
HOLD
TP
61 HLDA AS 76
READY 79
MEZRDY\ J5,4A (1)
U3C 66 R80 10K
U3A W/R
R18 R2 5 1 2
BLT CLK 1 2 BLT CLK1 6 5 1 2 CPU CLK1 1 2 CPU CLK 55 69 6
(1,6) CLK2 BLAST/FAIL 74AC32
BE0 52 4 1 2
20 74HC04 20 U42B
56 RESET BE1 51 R51 10K
SIMMRDY\

2
74HC04 (10)
A[1..31]

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R58 (1,3,4,5,6,7,10)
1K
IA[1..3]
(1,4,7,11)
U16 80960SA U40

18
22
32
34
43
48
54
63
72
74
77
84
U3E D[0..15]

7
D7 2 D1 Q1 19 A7 (1,3,4,6,7,10)
R28 E12 D6 3 18 A6
D2 Q2

DWG NO:
MM CLK 1 2 MM CLK1 10 11 D5 4 17 A5 U52
(1) J5,2C D3 Q3
D4 5 D4 Q4 16 A4 D7 2 A1 B1 18 PD7
20 D3 6 15 IA3 D6 3 17 PD6
VCC D5 Q5 A2 B2
74HC04 D2 7 D6 Q6 14 IA2 D5 4 A3 B3 16 PD5
D1 8 13 IA1 D4 5 15 PD4

757 039 11
D7 Q7 A4 B4
D0 9 D8 Q8 12 TP
D3 6 A5 B5 14 PD3
REF U16 D2 7 13 PD2
A6 B6
11 D1 8 12 PD1

1
C A7 B7
1 2 1 D0 9 11 PD0

1
C7 + C5
OC A8 B8
84 pin PLCC Socket (Through Hole)
5
6
7
8

PD[0..7]
U4 10uF R79 1K 74AC573 19 (1,4,5,7,11)
RP1 0.1uF DT/R\ G
4 16 1 74AC245
VDD VDD DIR

2
20 19 VCC U32
10K 32XIN VBATT
TP
1 32XOUT 32K 2 TP
D15 2 D1 Q1 19 A15
Y2 D14 3 18 A14

1
D2 Q2
4
3
2
1

1 2 6 D13 4 17 A13 VCC

XTALIN D3 Q3
8 14.74560 MHz D12 5 16 A12 RP11
14.7456 MHz 7 XBUFF R92 D4 Q4
XTALOUT FLPCLK 13 TP
D11 6 D5 Q5 15 A11 1
14 10 24.0143 MHZ 10K D10 7 14 A10 PD7 2
S0 CPUCLK D6 Q6
B 15 S1 CLKA 12 TP
11.9996 MHZ D9 8 D7 Q7 13 A9 PD6 3 B

2
17 S2 CLKB 11 26.6722 MHZ D8 9 D8 Q8 12 A8 PD5 4
18 OE CLKC 3 3.6864 MHZ PD4 5
5 GND CLKD 9 TP
11 C
PD3 6
1 2 1 OC
PD2 7
CY2291 PD1 8
2

R70 1K 74AC573 PD0 9

STRAPPING OPTIONS 10
OPTIONAL FOR DIFFERENT R10 R9 R19 R20 E2
CPU SPEEDS 1K 1K 1K 1K CPU CLK 10K
R10 R9 R19 FREQUENCY
------------------------------------
1

0 1 0 32.0087 MHz
1 1 0 29.4912 MHZ
0 0 0 24.0143 MHz (DEFAULT)
VCC
0=OPEN , 1=INSTALLED
TESTING VCC VCC
PURPOSE RP8 RP7
R20 STRAPPED DISABLES THE PLL
ONLY 1 1
(TRI-STATES OUTOUTS)
D7 2 D15 2
D6 3 D14 3
R26 VCC D5 4 D13 4
QUART CLK 1 2 QUART CLK1 8 9 RP3 D4 5 D12 5
(1,4)
1 D3 6 D11 6
20 U3D 2 A1 D2 7 D10 7
3 A2 D1 8 D9 8
74HC04
4 A3 D0 9 D8 9
5 10 10
U3F
R3 10K 10K 10K
BITBLITZ CLK E4 1 2 BITBLITZ CLK1 12 13
(1,6)

ETCH 20
74HC04

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

VCC INTERNATIONAL GAME TECHNOLOGY
THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
U45 U40 U4 U19 U42 U46 U31 U32 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO TITLE
1

BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

SCHEMATIC, GAME KING 2
1

+ C20 C47 C41 C4 C19 C49 C63 C34 C8

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
2

COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. C 757 039 11 A
U19 DRAW N DATE CHECKED DATE APPROVED DATE SCALE
VSS
TDW 01NOV99 NONE 2 OF 11
SHT __ __
4 3 2 1

20 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) OCTOBER 15, 2001
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 3 OF 11

1 2 3 4

VBATT
(1,9)

CE\OUT
(1,9)

D[0..15] D[0..15]
(1,2,6,7,10)

VOUT
(1,9,10)

D D

STUFF FOR RTC 62423

A[1..31] (REMOVE FOR DALLAS RTC)
(1,2,4,5,6,7,10)

R61
1 2

0 OHM
EPSON RTC SEL\ VCC

CE\OUT
U39 SRAM CE\ SRAM CE\
(10)
U46

2
A1 21 19 D0 VCC
U41A A0 D0 R113 A1 U21 RTC DS1215S
A2 22 A1 D1 18 D1 5 A0 DO 19 D0 R62
BOOT SEL\ 0000 0000H 4 2 23 17 1K A2 7 16 15 VCCI 16 2 1
(1) A21 A3 D2 D1
0020 0000H Y0 A A2 D2 A3 A1 D1 VCCO
5 Y1 B 3 A22 A4 24 A3 D3 16 D3 9 A2 D2 15 D2 1K
6 A5 25 15 D4 A4 10 14 D3 14
Y2 A4 D4 A3 D3 BAT2

1
TP 7 Y3 G 1 A6 26 A5 D5 14 D5
A7 27 A6 D6 13 D6 4 ALE STD.P 1 TP
BAT1 4 VBATT
A8 28 A7 D7 12 D7 2 CS0 GND 3 R60
74HC139 A9 29 10 D8 WR0\ 13 6 9 1 2
EPR SEL\ A8 D8 WR GND ROM/RAM
(1,2) A10 31 A9 D9 9 D9 RD\ 11 RD GND 8 RST 13 1K
A11 32 A10 D10 8 D10 R104 1K GND 12 WE 3
A12 33 A11 D11 7 D11 1 2 20 CS1 GND 17 OE 12
A13 34 6 D12 VOUT 24 18 10 11
A12 D12 VDD GND CEO CEI
A14 35 5 D13 21 Y3
A13 D13 GND
A15 36 A14 D14 4 D14
(VDD) 23 TP
X2 2 1 2
A16 37 A15 D15 3 D15
(VDD) 22 TP
VCC A17 38 1 32.768 MHz
A16(2M) RTC 62423 X1
A18 39 VPP(A17)
7 Q D 6 D0
OPTIONAL REAL TIME CLOCK
40 VCC GND 30
1 VPP GND 11

2 REF U39
C CE _10) Memory Options C
20 OE
BASE A[1..31]
SRAM CE D[0..15]
256KX16 EPROM 40 pin DIP Socket VBIT SEL
(1,10)
GAME SEL\ 120nS
GAME SEL VOUT
U7
0800 0000H 15 1 A21
0820 0000H Y0 A A22
(1,10) VBIT SEL\ 14 2
0840 0000H Y1 B A23
XM1 SEL\ 13 Y2 C 3
XM2 SEL\ 0860 0000H 12 VCC
0880 0000H Y3 74HC138
XM3 SEL\ 11 Y4 R31
XM4 SEL\ 08A0 0000H 10 6 2 1
08C0 0000H Y5 G1 R30
(1,7) VBLK0 SEL\ 9 4 1K 1 2
08E0 0000H Y6 G2A
(1,7) VBLK1 SEL\ 7 5 1K
Y7 G2B

XMB SEL
XM1 SEL
XM2 SEL
XM3 SEL
FLH SEL\ XM4 SEL
(1,2)

DWG NO.
(9,10)
RESET\ SIMM
RESET SIMM

VCC
WR0

757 039 11
WR1
RP10
1

RD
1 8 1
2 7 3 FW R0A\
R81 74AC32 FWR0A
3 6 2
10K 4 5 U25A
2

10K
IO WR\ 4
(1,2,4,5,7,11)
6 FW R1A\
IO RD\ 74AC32 FWR1A
(1,2,4,5,7) 5
B U25B B
RD\
(1,2,6,7,10) 9
8 SRAM OE\
74AC32 SRAM OE
10
U25C
PAGE 10
RAM SEL\ 12
(1,2)
11 SRAM W E0\
WR0\ 74AC32 SRAM WE0
(1,2,6,10) 13
U25D

12
11 SRAM W E1\
WR1\ 74AC32 SRAM WE1
(1,2,6,10) 13
U19D FWR0B
FWR1B
12
11 FW R0B\ FW R0B\ (1,7,10)
FWR EN\ 74AC32 FW R1B\
(1,4) 13 (1,7,10)
U42D
FW R0A\ (1,10)
1 FW R1A\ (1,10)
3 FW R1B\
74AC32
2
U19A
U20
A16 1 15 MEZ2 SEL\ 28000000h MEZ2 SEL\
A Y0 J5,3C (1)
A17 2 14 QRT1 SEL\ 28010000h QRT1 SEL\
B Y1 (1,4)
A18 3 13 SENET SEL\ 28020000h SENET SEL\
C Y2 (1,5)
12 WCHDOG SEL\ 28030000h WCHDOG SEL\
Y3 (1,9)
VCC R57 1K 11 QRT2 SEL\ 28040000h QRT2 SEL\
Y4 (1,4)
1 2 6 10 SOUND SEL\ 28050000h SOUND SEL\
G1 Y5 (1,4,11)
A19 4 9 COLOR SEL\ 28060000h COLOR SEL\
G2A Y6 (1,7)
IOT SEL\ 5 7 OUT SEL\ 28070000h OUT SEL\
(1,2) G2B Y7 (1,4,11)

74HC138

VCC

A A
1

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

VCC INTERNATIONAL GAME TECHNOLOGY
R100 R97 R98 THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
10K 10K 10K U41B 9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
U47 U11 U22 U39 U26 U21 U41 INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO TITLE
2

14 A Y0 12 TP

13 11 BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

SCHEMATIC, GAME KING 2
1

C64 C48 C28 C54 C40 C31 C27 C46 B Y1 TP

10
+ 15
Y2
9
TP
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF G Y3 TP

CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
2

22uF
COVENANTS IT WILL NOT BE USED IN ANY MANNER
2

74HC139 DW G. SIZE DW G. NO. REV LTR

DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
VSS
TDW 01NOV99 NONE 3 OF 11
SHT __ __
1 2 3 4

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 21
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 4 OF 11
4 3 2 1

U2
PD4 4 2 E1
D1 Q1 TP PAD SPARE
Q1 3
PD5 5 D2 Q2 7 TP

6 OUT5 (1,5)
A25\ Q2
(1,2) 9 PD6 12 D3 Q3 10 TP
R56 8 11 OUT6 (1,5)
IA[1..3] 74AC32 PD7
Q3
(1,2,7,11) VCC 1 2 10 13 D4 Q4 15 TP
U19C 14 OUT7
A[1..31] Q4 (1,5)
10K

1
(1,2,3,5,6,7,10)
OPTIONAL OUT CLK 9 TO LEDs (DS5, DS6 & DS7)
PD[0..7] RESET\
CLK
1 74HC175

2
(1,2,5,7,11) CLR
D U45 R63 D
IO RD\ 1K FWR EN\

VCC
(1,2,3,5,7) (1,3)
PD0 18 D0 RXDA 19 RXDA2
IO WR\

2
(1,2,3,5,7,11) PD1 17 20 TXDA2
D1 TXDA
PD2 15 27 VERTOUT (1,6)
QRT1 SEL\ D2 IO0A
(1,3) PD3 13 26 INTERROGATE (1,8,9)
D3 IO1A SPARE I/O E13
PD4 12 D4 IO2A 25 PAD
QRT2 SEL\ PD5 11 24
(1,3) D5 IO3A
PD6 10 IO2B2 (1,5)
D6
PD7 9 8 IO3B2 (1,5)
VCC D7 RXDB
TXDB 7
IA1 51 23 TO LEDs (DS2 & DS3)
A0 IO0B
IA2 50 A1 IO1B 22
IA3 49 21 MDOOR OPEN\

2
A2 IO2B (1,8,9)
A4 48 16 DDOOR OPEN\ (1,8,9)
R87 A3 IO3B BVAL OPEN\
A5 47 (1,8,9)
A6 46
A4 #2 36 CCAGE OPEN\ (1,8,9)
10K A5 RXDC SRAM BAT LOW\
TXDC 37 (1,9)
4 29 TT BAT LOW\ (1,9)
RDN IO0C

1
52 30 VCC

8
7
6
5
WRN IO1C R11 10K
3 CEN IO2C 31
INT0\ 45 32 1 2 RP15 LPSW
(1,2) IQRN IO3C J2,9B (1)
6 IACKN 10K LIGHT PEN
TP 5 DACKN RXDD 44
RESET QUART S1 SWITCH DETECT
(1,9) 38 RESET TXDD 43

1
2
3
4
IO0D 33 1 2
(1,2)
QUART CLK 42 34
X1/CLK IO1D TEST SWITCH SRESET\
IO2D 35 J2,13A (1)
E15 41 39 U77
TP
X2 IO3D +13VDC RESET\
3 AI AO 2 TP
INT3\ 1 28 5 BI 4
(1,2) VSS VSS BO TP

14 VSS VSS 40 7 CI CO 6
TXDB2 9 DI 10 TxDf J2,10B (1)
DO RxDf
TXDC2 11 EI EO 12 J2,9A (1)
SC26C94 TXDD2 14 FI 15
RESET\ I/O VCC FO SPARE F/O Max. rate = 19.2kb/s
(1,9)
13 +13VDC
_11) Audio MODE PROG TxDg
1 VC J2,8A (1)
16 PROG RxDg J2,8B (1)
C PD[0..7] J9 VOUT C
8

1
OUT SEL\ VSS PROGRESSIVE
IA1

1
2
3
4
4
3
(1,3,11) OUT SEL IA1

1
2
VCC OPTION 4504 COMMUNICATIONS Max. rate = 4800b/s
SOUND SEL\ R168 R170 C126 RP22
(1,3,11) SOUND SEL IO WR R84
2 1 1K 1K 0.1uF RP23

2
10K DCS TxDh J2,12A (1)

2
10K 10K DCS RxDh J2,12B (1)
SPEAKERA+

8
7
6
5
1
2
(1,11) J2,4A
VCC
SPEAKERA+ U81 RP25 100K DATA COLLECTION
OUT CLK IO0B2 2 3 8 1 SYSTEM (IGT) Max. rate = 38.4kb/s
OUT CLK AO AI
RXDB2 4 5 7 2

2
SPEAKER- U31 BO BI JKPT RST
(1,11) J2,3A RXDC2 6 CO CI 7 6 3 J2,7A (1)
SPEAKER- RXDD2 10 9 5 4

VCC
MM AUDIO1 DO DI JACKPOT RESET DETECT
(1,11) J5,21C PD0 18 D0 RXDA 19 IO2C2 12 EO EI 11 1 4
MM AUDIO1
PD1 17 D1 TXDA 20 IO0B1 15 FO FI 14 2 3
PD2 15 27 SIN IN J2,13B (1)
RESET\ CPU/SEN/AUD D2 IO0A VCC RP24 100K +13VDC
(1,2,5,9,11) PD3 13 D3 IO1A 26 MODE 13
RESET CPU/SEN/AUD CHOPPED AC IN
PD4 12 D4 IO2A 25 VC 1
(LOW VOLTAGE)
+25VDC PD5 11 D5 IO3A 24 16 VOUT
PD6 10 8

DWG NO.
J1,18A,18B
+25VDC VCC D6 VSS SCLK256
PD7 9 D7 RXDB 8 (1,5)
7 4504
+13VDC TXDB SENET CYCLE DONE
J2,1A,1B IA1 51 A0 IO0B 23
+13VDC PAGE 11 VCC IA2 50 22

1
A1 IO1B
IA3 49 21 TT-CNTR1 (1,8.9)
A2 IO2B

757 039 11
A4 48 16 TT-CNTR2
1

2
A3 IO3B (1,8.9)
R226 R225 A5 47 TT-DISABLE\
220 10K R69 A6 46
A4 #1 36 TT-DET\
(1,8,9)
A5 RXDC (1,8.9)
R196 U62A 37
TXDC TELL TALE
2

2
2.2K U87A 74HC125 10K 4 29
RDN IO0C
7 2 52 WRN IO1C 30
2

1
8 1 3 2 IO2A1 3 31
I/O RESET\ CEN IO2C E14
(1) J2,11A 45 IQRN IO3C 32 PAD
ILD2 6
3

2N3904 IACKN RxDd

5 44
1

TP
DACKN RXDD (1,9)
CR17 1 1 RESET QUART 38 43 TxDd
RESET TXDD (1,9)
IO0D 33
1N914 Q7 R197 ON BOARD F/O
42 X1/CLK IO1D 34
COMMUNICATIONS
2

B 220 35 Max. rate = 115.2kb/s B

IO2D
1

R212 U61 41 39
TP
X2 IO3D
2

1 2
DATA 1 1 VSS VSS 28
A 220 3 E11 14 40 U76
N/C TP
VSS VSS TxDa
GND 2 TXDA1 3 AI AO 2 J1,4B (1)
+13VDC 4 IO2A1 5 4 RxDa J1,3B (1)
GND SC26C94 BI BO
R198 IO3A1 7 CI CO 6
1 2 DS2401Z TXDB1 9 10 DTR J1,4A (1)
U62C DI DO
SILICON TXDC1 11 EI EO 12
2.2K U87B R185 SERIAL SNIN 14 15 DCD J1,5B (1)
TxDe NUMBER VCC FI FO DIR
R199 6 3 1 2 8 9 J1,5A (1)
2 1 5 4 13 +13VDC
NETPLEX TxD 750 74HC125 MODE RS485 Max. rate = 19.2kb/s
(1) J2,11B 1 VC
2N3904 220 ILD2 U62B
16
10

R117
3

VOUT
1 2 6 5 SNOUT
VSS 8
NETPLEX RxD CR18 1 VCC

1
(1) J2,10A
4.7K 74HC125 4504 C103 TxDb

1
2
3
4
3
4
J2,16A (1)
1N914 Q8 U62D RxDb J2,16B (1)
2

4
R200 VCC 0.1uF RP19 RP20
1
1

2
1 2 12 11 MICROTOUCH / SPARE Max. rate = 9.6kb/s
VCC 10K 10K
A 220 R118 74HC125

8
7
6
5
2
1
1K U80 RP21 100K
13

RP12 RXDA1 2 3 8 1
AO AI
2

10 1 IO0A1 4 5 7 2 COMM TxDc J2,14A (1)

VCC R78 BO BI
5 2 RXDB1 6 CO CI 7 6 3
R217 U86A 10K 3 IO2C1 RXDC1 10 9 5 4 COMM RxDc
3

DO DI J2,14B (1)
1 2 2 7 R211 4 IO0C1 12 11 2 3 COMM CTS J2,15B (1)
EO EI
2

1 8 1 2 1 Q4 6 15 14 1 4 COMM RTS J2,15A (1)

2.4K
TP
FO FI
7
1

ILD2 150 2N3904 VCC RP18 100K +13VDC RS232 DATA

8 MODE 13 COLLECTION Max. rate = 19.2kb/s
2

+13VDC 9 1
R208 VC 4504 INPUT OUTPUT
16 VOUT
220 8 MODE LEVEL LEVEL
VCC VDD 10K VSS
1 (VCC) TTL CMOS
2

4504
U44 U77 U2 U76 U78 U62 U78 U60 U20 U79 U30 0 (VSS) CMOS CMOS
A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

POWER SAVE INTERNATIONAL GAME TECHNOLOGY
1

1
C70 C53 C101 C6 C105 C112 C76 C61 C24 C26 C113 C124 THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
(1) J1,3A
VCC U18C + 9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
U86B R175 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF TITLE
3

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO

2

2
2N3904 6 3 1 2 6 5 22uF
2

CR12 1 5 4 BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

470
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
1N914 Q5 ILD2 74HC14
PROTECT GAME KING CTR/TT
2

CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT

1

R181 VSS
1 2 R55 10K U18D COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
1 2 9 8 TP DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
A 1K
74HC14 RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE 4 OF 11
SHT __ __
4 3 2 1

22 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) OCTOBER 15, 2001
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 5 OF 11
4 3 2 1

VCC

R17 1K R24 10K

1 2 1 2

R7 1K R8 10K
1 2 1 2
D D

R6 1K R5 10K
1 2 1 2
DON'T
STUFF
R16 1K R23 10K
1 2 1 2

+13VDC

RESET\ CPU/SEN/AUD R25 10K

(1,2,4,9,11)

10
1 2

5
RP16
SYS CLK
(1,2)
4.7K

TP

TP

TP
68
67
66
65
64
63
62
61
SCLK256

9
8
7
6
5
4
3
2
1
(1,4)

1
2
3
4
6
7
8
9
U10

SEL3
SEL2
SEL1
SEL0
GND
GND

VCC

SCLK17

VCC

CABSTBIN

CABSDI
RESET

CABSTBOUT
GND (wrtramhi)
GND (selramhi)

SCLK256 (rd7)

SYSCLK
A[1..31]
(1,2,3,4,6,7,10)
R169 20
1 2 SDATA TxA J1,11A (1)
A1 10 60 U78 U74 R192 20
A1 CH1SDO CH1SDO SDATA TxB
A2 11 A2 CH1SDI 59 3 AI AO 2 2 1A1 1Y1 18 1 2 J1,12B (1)
A3 12 58 CH2SDO 5 4 4 16
A3 CH2SDO MASDO BI BO 1A2 1Y2 SDATA ADR
A4 13 A4 (ntr) MASDO 57 7 CI CO 6 6 1A3 1Y3 14 1 8 J1,12A (1)
A5 14 56 SCLK 9 10 8 12 2 7 SENCLK
A5 (rd6) SCLKO DI DO 1A4 1Y4 J1,10B (1)
A6 15 55 STB 11 12 11 9 3 6 SENSTB\
A6 (rd4) STB EI EO 2A1 2Y1 J1,10A (1)
IO_EN

VCC
A7
A8
16
17
A7
A8
SENETEEG (rd5) IO_EN
SDA
54
53 VCC
14 FI FO 15 13
15
2A2
2A3
2Y2
2Y3
7
5 TP
4

RP17 22
5 SENRST\ J1,13B (1)

A9 18 52 13 17 3
A10 19
20
A9
A10
68PLCC SCL
GND 51
50
1
MODE
VC
16 1
2A4 2Y4
20
TP

VCC
VCC GND VOUT 1G VDD
21 VCC (rd3) NC 49 TP
VSS 8 19 2G VSS 10
1 22 48

1
GND (scanen) (rd2) NC TP

(oenramhi) GND
23 47 4504 74C240
1

C
C12 + C25
GND (scantn) VCC C
24 46

3
TP
NC (scanout) VCC R174 R150 R160 R149
25 45

1
.01uF 22uF GND (rd1) NC TP
10K 10K 10K 10K CR16
26 44

SENRDY
GND (rd0) NC TP

SENSEL
2

1N914

IO-WR
R193

2
IO-RD
150

GND
GND

VCC
VCC
U18F

D0
D1
D2
D3
D4
D5
D6
D7

1
R178

2
12 13 1 2 SDATA RxA J1,11B (1)
E9 SENET II

27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

3
10K
74HC14 CR11
VCC 1N914

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

1
SENGRD - (J1-13A)

RP9 U68
PD[0..7] +13VDC
(1,2,4,7,11) J2,1A/1B (1)

1
(1,2)
SENRDY\ C109 C104

DWG NO.
SENET SEL\ 0.1uF 0.1uF
(1,3)

2
IO WR\
(1,2,3,4,7,11)
IO RD\

757 039 11
(1,2,3,4,7)

R206
1 2 SDA J1,2B (1)
100
I^2C
R205
1 2 SCL
J1,2A (1)
100

VCC
B B

U5A DS6
FAILURE (FAILURE DETECTED) 1 2 1 2 CPU FALURE
(1,2,5)

1
Red
74HC14
R194
R177 R179
U5D DS4 10K 10K 10K
OUT7 (FIRMWARE DEFINEABLE) 9 8 1 2 OUT7
(1,4)

2
Yellow U85
74HC14
6 SCL VCC 8
5 SDA NC 1
U5B DS1 7 2
IO2B2 MODE/WC NC
(1,4) (FIRMWARE DEFINEABLE by QUART) 3 4 1 2 3 WCR
OPTIONAL
VCC 4
Yellow RP2 VSS
74HC14
1 10 M34R32
2 5
U5C DS2 3
(1,4)
IO3B2 (FIRMWARE DEFINEABLE by QUART) 5 6 1 2 4
6
Yellow 7
74HC14
8
9
U5F DS3
OUT5 (FIRMWARE DEFINEABLE) 13 12 1 2 OUT5 1K
(1,4)
Yellow
74HC14
+13VDC VCC

U5E DS5
OUT6 (FIRMWARE DEFINEABLE) OUT6 U83 U6 U3
(1,4) 11 10 1 2

Yellow
1

1
74HC14
C58 C21 C125 C9 C117
A A
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO
IO2B2

INTERNATIONAL GAME TECHNOLOGY

OUT7

OUT6

OUT5

IO3B2

2
THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
FAIL

9295 PROTOTYPE DRIVE RENO, NV 89511

1

INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO TITLE
R54
DSx DSx DSx DSx DSx DSx 10K U18E BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
2

LED configiration (FRONT PANEL VIEW) 11 10 TP

CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
74HC14
COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
PCB side RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE 5 OF 11
SHT __ __
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 23
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-02 REV A PAGE 6 OF 11
4 3 2 1
U18B
R218
DOT CLK2 4 3 1 2
(1)
R221
1 2 0 OHM
74HC14
BITBLITZ CLK 10K
(1,2)
R4
VCC 1 2
10K
R15

1
OPTIONAL C3 14 8 1 2

2
VCC OUT
R48 0.1uF Y1 0 OHM

2
7 GND EN 1
10K
U17 26.667MHz STUFF IF PLL NOT USED

1
VCC 7 VPP DATA 1 DIN
TP 6 CEO CLK 2 CCLK
D D
4 DONE DOT CLK
CE (1,7)
XC1765D 3 SC-1
RESET/OE (1,7)
SC-2
E8
D[0..15]
(1,2,3,7,10) DD[0..7]

2
(1,7)
VCC
R219
A[1..31] 20 VCC VCC
(1,2,3,4,5,7,10) R49
1 2

1
REF U9
10K U8

18
32
47
57

18
32
47
57
5 18 DD0

1
8

1
8
DCLK DD0

BB DOT CLK
84 pin PLCC Socket (SMT) U11 U1 VS0 6 19 DD1
VS0 DD1

22
64
VS1 7 20 DD2

VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
U9 XC3142, BitBlitz VS1 DD2
VS2 8 VS2 DD3 22 DD3
VS3 9 24 DD4

VCC
VCC
SC-1 SC-3 VS3 DD4
D0 44 D0 SC-1 8 64 SC I/O 00 5 D0 64 SC I/O 00 5 D0 VS4 11 VS4 DD5 25 DD5
D1 46 7 SC-2 7 D1 7 D1 VS5 12 26 DD6
D1 SC-2 I/O 01 I/O 01 VS5 DD6
D2 41 D2 SC-3 6 SC-3
I/O 02 10 D2
I/O 02 10 D2 VS6 13 VS6 DD7 27 DD7
D3 45 D3 OE-1 82 2 DT/OE I/O 03 12 D3 2 DT/OE I/O 03 12 D3 VS7 14 VS7
D4 40 81 15 D4 15 D4 VS8 40 28 BLOCK (1,7)
D4 OE-2 I/O 04 I/O 04 VS8 BLOCK
FID4 FID5 D5 42 3 24 17 D5 24 17 D5 VS9 42 39 CA0 (1,7)
D5 WE-1 WBL/WEL I/O 05 WBL/WEL I/O 05 VS9 CA0
D6 48 D6 WE-2 2 25 WBU/WEU I/O 06 20 D6 25 WBU/WEU I/O 06 20 D6 VS10 43 VS10
FOR PCB USE ONLY D7 49 84 22 D7 22 D7 VS11 44 35

VS[0..15]
D7 WE-3 I/O 07 I/O 07 VS11 NC
FIDUCIAL D8 50 D8 DSF-1 80 I/O 08 43 D8
I/O 08 43 D8 VS12 1 VS12 NC 29
D9 51 D9 CAS-1 78 39 CAS I/O 09 45 D9 39 CAS I/O 09 45 D9 VS13 2 VS13 NC 33
D10 52 D10 CAS-2 76 I/O 10 48 D10
I/O 10 48 D10 VS14 3 VS14 NC 36
D11 53 D11 RAS 77 26 RAS I/O 11 50 D11 26 RAS I/O 11 50 D11 VS15 4 VS15 NC 37
53 D12 53 D12

1
I/O 12 I/O 12 SC-1 34 ISP4
A1 24 A1 VA0 62 VA0 VA0 37 A0 I/O 13 55 D13 VA0 37 A0 I/O 13 55 D13
SC1 TDI 15
A2 21 63 VA1 VA1 36 58 D14 VA1 36 58 D14 16 ISP2
A2 VA1 A1 I/O 14 A1 I/O 14 TMS ISP3 R32 R33 R37 R41
A3 27 A3 VA2 59 VA2 VA2 35 A2 I/O 15 60 D15 VA2 35 A2 I/O 15 60 D15 38 C256 TCK 17
A4 61 60 VA3 VA3 34 VA3 34 30 ISP5 10K 10K 10K 10K

1
A4 VA3 A3 A3 TDO
A5 66 A5 VA4 65 VA4 VA4 31 A4 SI/O 00 4 VS0 VA4 31 A4 SI/O 00 4 FD0

2
A6 16 67 VA5 VA5 30 6 VS1 VA5 30 6 FD1 XC9536, DD CONTROLLER
C A6 VA5 A5 SI/O 01 A5 SI/O 01 R27 C
A7 71 A7 VA6 68 VA6 VA6 29 A6 SI/O 02 9 VS2 VA6 29 A6 SI/O 02 9 FD2
A8 14 69 VA7 VA7 28 11 VS3 VA7 28 11 FD3 10K
A8 VA7 A7 SI/O 03 A7 SI/O 03
A9 73 A9 VA8 70 VA8 VA8 27 A8 SI/O 04 14 VS4 VA8 27 A8 SI/O 04 14 FD4

2
A10 25 A10 BLANK 33 SI/O 05 16 VS5
SI/O 05 16 FD5
A11 23 A11 SI/O 06 19 VS6
SI/O 06 19 FD6
A12 28 A12 PWRDN 12 SI/O 07 21 VS7
SI/O 07 21 FD7
A13 26 A13 M0 31 63 SE SI/O 08 44 VS8 63 SE SI/O 08 44 FD8
A14 20 A14 M1 32 SI/O 09 46 VS9
SI/O 09 46 FD9 ISP[1..6]

DWG NO.
A15 19 A15 SI/O 10 49 VS10
SI/O 10 49 FD10 (1,2,7)
A16 18 A16 BLTRDY 9 SI/O 11 51 VS11
SI/O 11 51 FD11
A17 17 A17 FLATCH1 30 40 NC SI/O 12 54 VS12 40 NC SI/O 12 54 FD12
A18 15 A18 FLATCH2 29 SI/O 13 56 VS13
SI/O 13 56 FD13
+13VDC LOW\ R47

757 039 11
(1,8,9) 1 2 39 BLANK2 BA0 47 SI/O 14 59 VS14
SI/O 14 59 FD14
0 OHM A20 34 A20 BA1 58 41 DSF SI/O 15 61 VS15 41 DSF SI/O 15 61 FD15
A21 35 A21 BLOCKRW 56
BBSTB 36 38 256X16 VDRAM 38
(1,2) DOTCLK TP
QSF TP
QSF FD[0..15]
54 38 60nS 256X16 VDRAM (1,7)
BLT CLK RESET HORZ 60nS
10 57

2
(1,2) ADRSTB VERT

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
13 BITCLK
BITBLITZ SEL\ 11 37 R29 R1
(1,2) BLTSEL OSC

VA[0..8]
75 LPSTB
LPSTB\ 79 10K E6 10K E5

13
23
33
42
52
62

13
23
33
42
52
62
(1) DSF-2

3
5 72 U48
WR0\ WR0 DIN/256COLOR

1
(1,2,3,10) 4 WR1 CCLK 74 FD0 2 D1 Q1 19 BD0
GND
GND

83 RD DONE 55 FD1 3 D2 Q2 18 BD1

WR1\ FD2 4 17 BD2
(1,2,3,10) D3 Q3
FD3 5 D4 Q4 16 BD3
RD\ FD4 6 15 BD4
43

(1,2,3,7,10) E3 D5 Q5
1

R14 FD5 7 D6 Q6 14 BD5

RESET\ VIDEO 1 2 FD6 8 13 BD6
(1,7,9) D7 Q7
0 OHM FD7 9 D8 Q8 12 BD7
R42
NORMALLY NOT STUFFED 1 2 11 CLK
1 2 1

2
220 OC BD[0..15]
(1,7)
VCC R102 10K 74HC574
R53
E7 4.7K
B JUMPER U27 B

1
FD8 2 D1 Q1 19 BD8
FOR ENGINEERING TESTING FD9 3 18 BD9
D2 Q2
FD10 4 D3 Q3 17 BD10
FD11 5 D4 Q4 16 BD11
BLTRDY\ FD12 6 15 BD12
(1,2) D5 Q5
FD13 7 D6 Q6 14 BD13
FD14 8 D7 Q7 13 BD14
FD15 9 D8 Q8 12 BD15
9
H SYNC 8 11
(1) CLK
74HC32 10 1 2 1 note:
U59C OC BD12, BD13, BD14 and BD15
3

R67 10K 74HC574 are NOT USED or connected

CR7 CR5 VCC BD12 TP
R127 BD13
1N914 1N914 TP
1K BD14 TP

BD15 TP
1

1 BLANK1
(1,7)
V SYNC 3
(1) FLATCH1
74HC32 2
3

(1,7)
U59A
1

CR4 CR6 FLATCH2

(1,7)
1N914 1N914 R108 BA0
1K (1,7)
BA1
1

(1,7)
2

VERTOUT BLOCKRW\
(1,4) (1,7)

BLANK2
(1,7)
V

A A
VCC
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO
INTERNATIONAL GAME TECHNOLOGY
U13 U55 U12 U7 U14 U28 U50 THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
1

TITLE
1

C23 C74 C14 C1 C13 C35 C56 C36 + C2 INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
2

CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
VSS
RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE 6 OF 11
SHT __ __
4 3 2 1

24 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) OCTOBER 15, 2001
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 7 OF 11
4 3 2 1

(1,2,3,4,5,11)
IO WR\
(1,2,3,4,5)
IO RD\

PD[0..7]
(1,2,4,5,11)

(1,3)
COLOR SEL\

(1,6)
FLATCH1
(1,6)
SC-1
(1,6)
BLANK1
(1,3,10)
FW R0B\
IA[1..3]
(1,2,4,11)

(1,3)
VBLK1 SEL\ 13
11

1
(1,6)
BLOCKRW\ 12 74HC32 C119
D U59D D
DD[0..7] 0.1uF
(1,6)

20
21
22

2
4
(1,2,3,6,10) D[0..15] U82
V

VCC
VCC
VCC
VCC
U22 PX0 32 1
PX1 P0 N/C
1 DIR 33 P1
19 PX2 34 25 RED J1,24B
G PX3 P2 RED
U33 35 26 GREEN J1,25B
PX4 P3 GREEN
D0 9 11 BK0 BK0 2 19 BL0 U34 36 27 BLUE J1,24A
A8 B8 D1 Q1 PX5 P4 BLUE
D1 8 A7 B7 12 BK1 BK1 3 D2 Q2 18 BL1 BL0 2 1A 1Y 4 PX0 37 P5
D2 7 13 BK2 BK2 4 17 BL2 BL1 5 PX6 38 28
A6 B6 D3 Q3 2A PX7 P6 IREF
1 D3 6 A5 B5 14 BK3 BK3 5 D4 Q4 16 BL3 BL2 11 3A 2Y 7 PX1 39 P7 COMP 29
5 3 D4 5 15 BK4 BK4 6 15 BL4 BL3 14 C120
74HC08 A4 B4 D5 Q5 4A PD0
6 2 D5 4 A3 B3 16 BK5 BK5 7 D6 Q6 14 BL5 BL4 3 1B 3Y 9 PX2 8 D0 VREF 31 1 2
4 74HC32 U44A D6 3 17 BK6 BK6 8 13 BL6 BL5 6 PD1 9
U59B A2 B2 D7 Q7 2B PD2 D1 0.1uF
D7 2 A1 B1 18 BK7 BK7 9 D8 Q8 12 BL7 BL6 10 3B 4Y 12 PX3 10 D2
BL7 13 PD3 11 30
74HC245 FLATCH2 4B PD4 D3 OPA TP

11 CLK 12 D4
U23 74HC574 ENBLK1 15 PD5

BL[0..15]
1 74HC257 13
OC G D5
(1,2,3,6,10)
RD\ 1 SC0 1 PD6 14
DIR A/B PD7 D6
19 G R74 15 D7

VBLK0 SEL\
2 1
D8 9 11 BK8 IA1 17 7
A8 B8 10K RS0 BLANK
D9 8 12 BK9 IA2 18
A7 B7 BK[0..15] RS1
D10 7 A6 B6 13 BK10 16 WR
D11 6 14 BK11 U49 6 40
A5 B5 PX4
RD PCLK
D12 5 A4 B4 15 BK12 BL4 2 1A 1Y 4

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D13 4 A3 B3 16 BK13 BL5 5 2A
D14 3 17 BK14 BL6 11 7 PX5 VDAC (PLCC)
A2 B2 3A 2Y
D15 2 A1 B1 18 BK15 BL7 14 4A
BL12 3 9 PX6

19
23
24
41
42
43
44
1B 3Y

2
3
5
74HC245 BL13 6
A[1..31] 2B
(1,2,3,4,5,6,10) BL14 10 3B 4Y 12 PX7
BL15 13 4B
256 EN\ 15 74HC257 V
G
SC1

VBLK1 SEL\
1

BLKRW\+VBLK1
A/B
C C
VCC
BA[2..24] OPTIONAL
U30 IF PLCC PART NOT AVAILABLE

(1,6)
BA0 12 13 BK0 J3 VIDEO VCC
BA1 A0 D0 VCC
(1,6) 11 A1 D1 14 BK1 1 2
BA2 10 15 BK2 3 4 A1 U24

1
BD[0..15] A2 D2 L1
BA3 9 17 BK3 5 6 A2

1
(1,6) A3 D3
U47 BA4 8 18 BK4 FWR0B\ 7 8 A3 ENBLK1 5 24 COLOR SEL\ C82 + C81 1 2
A4 D4 ENBLK1 COLORSEL
BD0 2 19 BA2 BA5 7 19 BK5 BL0 9 10 BL4 256 EN\ 40 25 IO RD\ 10uF
D1 Q1 A5 D5 B256 IO_RD
BD1 3 18 BA3 BA6 6 20 BK6 BL1 11 12 BL5 DD0 2 26 VDAC W\ 0.1uF FERRITE BEAD
D2 Q2 A6 D6 DD0 VDAC_WR

28
IO WR\

2
BD2 4 D3 Q3 17 BA4 BA7 5 A7 D7 21 BK7 BL2 13 14 BL6 DD1 42
DD1 IO_WR 27
BD3 5 16 BA5 BA8 27 BL3 15 16 BL7 DD2 4 11 256COLOR\ U73
D4 Q4 A8 DD2 C256
BD4 6 15 BA6 BA9 26 REF U30 BA20 17 18 BL8 DD3 7 39 PX0 V V

VCC
D5 Q5 A9 DD3 PX0
BD5 7 D6 Q6 14 BA7 BA10 23 A10
BA19 19 20 BK7 DD4 18
DD4 PX1 33 PX1 PX0 5 P0 RED 1
BD6 8 D7 Q7 13 BA8 BA11 25 A11
BA18 21 22 BK6 DD5 19
DD5 PX2 34 PX2 PX1 6 P1 GREEN 2
BD7 9 D8 Q8 12 BA9 BA12 4 A12
BA17 23 24 BK5 DD6 20
DD6 PX3 35 PX3 PX2 7 P2 BLUE 3
BA13 28 32 pin DIP Socket BA16 25 26 BK4 DD7 28 36 PX4 PX3 8
A13 DD7 PX4 P3

DWG NO.
FLATCH2 11 BA14 29 BA15 27 28 BK3 FLATCH1 13 37 PX5 PX4 9
CLK A14 F1 PX5 P4
1 2 1 BA15 3 BA14 29 30 BK2 BLANK1 43 38 PX6 PX5 10
OC A15 BLANK1 PX6 P5
BA16 2 BA13 31 32 BK1 BLOCK 3 29 PX7 PX6 11
R105 10K A16(1M) BLOCK PX7 P6
74HC574 BA17 30 BA12 33 34 BK0 CA1 8 PX7 12

1
A17(2M) CA1 P7
RD\

757 039 11
BA18 31 PRG(A18)
BA11 35 36 CA2 9
CA2
U43 BA10 37 38 BL9 CA3 14 44 SC-1 PD0 17 R173
CA3 SC1 DQ0
BD8 2 D1 Q1 19 BA10 BA19 1 VPP(A19)
BA9 39 40 BK15 CA4 1
CA4
PD1 18 DQ1
BD9 3 18 BA11 BA8 41 42 BK14 ENBLK2 12 15 ISP5 PD2 19 10K
D2 Q2 ENBLK2 TDI DQ2
BD10 4 17 BA12 BA7 43 44 BK13 VDAC R\ 22 16 ISP2 PD3 20

1
D3 Q3 VDAC_RD TMS DQ3

2
BD11 5 16 BA13 22 BA6 45 46 BK12 17 ISP3 PD4 21 C127
D4 Q4 CE SC0 TCK ISP6 DQ4
FD0 6 D5 Q5 15 BA14 24 OE
BA5 47 48 BK11 6 SCO TDO 30 PD5 22 DQ5 IREF 4
FD1 7 14 BA15 BA4 49 50 BK10 PD6 23 10pF
1

D6 Q6 DQ6

2
FD2 8 13 BA16 BA3 51 52 BK9 E10 XC9536, PIXEL CONTROLLER PD7 24 50V
D7 Q7 DQ7
FD3 9 12 BA17 512KX8 EPROM BA2 53 54 BK8
D8 Q8 R77 R73 100nS BA1 DOT CLK
55 56 BL10 IA1 26 RS0 PCLK 13 (1,6)
FLATCH2 11 10K 10K BA0 57 58 BL11 IA2 27 R176
CLK BLOCK LOOKUP GND GND RS1
1 2 1 OC 59 60 25 W BLANK 16 1 2 BLANK2 (1,6)
VBLK0 SEL\
2

VSS
61 62 BL12 15 R
R90 10K 74HC574 U53 BL13 63 64 BL14 0 OHM
FWR1B\ 65 66 BL15 R46
B U28 12 13 BK8 256C GND 67 68 FLATCH2 1 2 ISP3 REF U73 VDAC (DIP) B

14
A0 D0 FLATCH1 FLATCH1
FD4 2 D1 Q1 19 BA18 11 A1 D1 14 BK9 69 70
FD5 3 18 BA19 BA2 10 15 BK10 RESET\ 71 72 BLOCKRW\ 10K E20
D2 Q2 A2 D2 28 pin DIP Socket
FD6 4 D3 Q3 17 BA20 BA3 9 A3 D3 17 BK11
FD7 5 16 BA21 BA4 8 18 BK12 72 Pin SIMM VCC

1
D4 Q4 A4 D4 C114 C108
FD8 6 D5 Q5 15 BA22 BA5 7 A5 D5 19 BK13
FD9 7 14 BA23 BA6 6 20 BK14

1
D6 Q6 A6 D6 1.0uF 0.1uF
FD10 8 D7 Q7 13 BA24 BA7 5 A7 D7 21 BK15 V

2
FD11 9 D8 Q8 12 BA25 BA8 27 A8
BA9 26 REF U53 R95
FLATCH2 A9 10K
11 BA10 23

3
CLK A10
1 2 1 OC
BA11 25 A11
FD[0..15]

2
BA12 4 + Q3
R68 10K A12 32 pin DIP Socket
74HC574 BA13 28 2
A13 LM334
PL CA4 BA14 29 A14
PL CA3 BA15 3 A15
-
PL CA2 BA16 2 U57 U58 R148
A16(1M)

1
(1,6) PL CA1 BA17 30 A17(2M)
BK8 2 D1 Q1 19 BL8 BL8 2 1A 1Y 4 PX0 1 2
PL CA0 BA18 31 PRG(A18)
BK9 3 D2 Q2 18 BL9 BL9 5 2A
BK10 4 17 BL10 BL10 11 7 PX1 15

1
D3 Q3 3A 2Y 1%
U35 BA19 1 BK11 5 16 BL11 BL11 14

1
VPP(A19) D4 Q4 4A CR3
3 D1 Q1 2 CA0 BK12 6 D5 Q5 15 BL12 BL12 3 1B 3Y 9 PX2
4 D2 Q2 5 CA1 BK13 7 D6 Q6 14 BL13 BL13 6 2B 1N914
6 7 CA2 22 BK14 8 13 BL14 BL14 10 12 PX3 R147
D3 Q3 CE D7 Q7 3B 4Y 150
11 10 CA3 24 BK15 9 12 BL15 BL15 13
1

D4 Q4 OE D8 Q8 4B

3
13 D5 Q5 12 CA4
FLATCH2 11 ENBLK2

2
VCC 1 2 14 15 15 74HC257
D6 Q6 TP
R115 R114 512KX8 EPROM CLK 74HC574 SCO G
1 1

1
R76 10K FLATCH2 10K 10K 100nS OC A/B
R75 9 CLK
1 2 1 R123 R186 R190
CLR
2

1K 2 1
74AC174 0 OHM 0 OHM
CA[0..4] 10K 3 Amps 3 Amps
CA0
(1,6)

2
(1,6)
FLATCH2 V A B

(1,6,9)
RESET\ VIDEO PX[0..7] (1)
ISP[1..6]
A (1,2,6) A
(1,3)
VBLK0 SEL\
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO
(1,3,10)
FW R1B\ INTERNATIONAL GAME TECHNOLOGY
BLOCK THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
(1,6) 9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
VCC TITLE
5 10 INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
6 8 BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
4 74HC08
TP

9 74HC08
TP

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS

SCHEMATIC, GAME KING 2
U44B U44C
PROTECT GAME KING CTR/TT
1

CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT

1

1
+ C51 C32 C50 C42 C29 C30 C55 C43 C57 C123 C52 C45 C33 C44 C73 C71 C72
13 22uF COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
R103 R91 11 TP
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
C 757 039 11 A
2

2
10K 10K 12 74HC08
U44D RETURNED ON DEMAND.
2

DRAW N DATE CHECKED DATE APPROVED DATE SCALE

VSS
TDW 01NOV99 NONE 7 OF 11
SHT __ __
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 25
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 8 OF 11
4 3 2 1

VDD

D D

1
R203 R210 R213 R204
470K 470K 470K 470K

2
R209 U66A
CARDCAGE DET\ 1 2 1
(1,9)
3
100K 4071 CCAGE OPEN\
2 (1,4,9)
1 CC-OPEN
3 4081
2 DDOOR OPEN\
(1,4,9)
U75A MD-OPEN

MDOOR OPEN\ (1,4,9)

5
4 4081
6 BVAL OPEN\
(1,4,9)
U66B U75B
5 VDD
R202 4071 4
DROPDOOR DET\ 1 2 6 U71 U65 U70
(1,9)
4 D0 Q0 2 2 I1 O1 3 14 D0 Q0 3
100K 3 4 5 13 4
Q0 I2 O2 D1 Q1
5 D1 Q1 7 6 I3 O3 7 12 D2 Q2 5
Q1 6 10 I4 O4 9 11 D3 Q3 6
12 D2 Q2 10 12 I5 O5 11
Q2 11 14 I6 O6 13 9 DDA
13 D3 Q3 15 10 DDB
Q3 14 1 DA 7 CLK
9 CLK 1 2 15 DB 1 ODA
U66C 1 2 1 2
CLR R125 1K ODB 4076
8 4503 15 RST
R201 10 R152 1K 40175
MAINDOOR DET\ 4071
(1,9) 1 2 9
C C
100K 8
R214 10
BILLVAL DET\ 4081
(1,9) 1 2 9
U75C R154
100K U67A CC-OPEN 1 2 STUFF R154 FOR CARD CAGE ALARM (DEFAULT)
2 A Q0 4
0 OHM
3 B Q1 5
VDD 6
Q2
12 1 E Q3 7 TP R153
11 MD-OPEN 1 2 STUFF R153 FOR MAIN DOOR ALARM
4081
13 4556
8
7
6
5

U66D U75D 0 OHM

RP14 12
R107 11 U67B
470K 470K 4071
13 14 A Q0 12

DWG NO.
13 B Q1 11 TP
1
2
3
4

Q2 10 TP

1 2 15 E Q3 9 TP
TT-CNTR1
(1,4,9)

757 039 11
R133 1K 4556
TT-CNTR2
(1,4,9)
VDD
TT-DISABLE\
(1,4,9)
INTERROGATE

1
(1,4,9)

R183
U83A 10K
+13VDC LOW\ 1
(1,6,9)

2
4001 3
2 R184
1 2 TT-DET\ (1,4,9)
100K

U83B DOORVAL OUT (1,9)

VDD 5
B 4 B
4001
6

3
U83C
TT-BACKUP U36 U41 U92 U60 U25 U61 U50 U35 Q6
(9) R137 8 R182
1 2 10 1 2 1 MOSFET N
1

4001
9
1

2
C86 C87 + C62 C91 C78 C116 C98 C99 C100 390K 100

1
10uF R157 R158 C102 R155
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
200K
2

10K 10K 1000pF

2
1
1

2
9 4

S
U37 A O1
10
1

B
11 C O2 5
VSS 12 U83D
R142 D
DO 13 12
47K 6 R171 11
8_BY 4001
7 CINH 2 1 13
2

1K
15 MONO
14 U68
1

C92 OINH
3

R
IN1
1000pF 4536
2

2
2

R161 R159 R136 R156 R145

1K 1K 1K 1K 1K
1

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

INTERNATIONAL GAME TECHNOLOGY
THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO TITLE

BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE 8 OF 11
SHT __ __
4 3 2 1

26 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) OCTOBER 15, 2001
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 9 OF 11

4 3 2 1

REF U84B1
HEAT SINK
VDD VCC
E21
1 FOR EXTERNAL
REF U84B3 HEATSINK COUMPOUND POWER SUPPLY VCC
2
REF U84A R12
1 2

1
REMOVE E27 WHEN USING AN U64A U64B 3.3K FO1
REF U84B2 CLIP EXTERNAL POWER SUPPLY R172
HEAT SINK 0 OHM 2 1 4 3 1
3 Amps

2
U84 40106 40106 2
+13VDC 1 4 VCC OUT2
(1) J2,1A/1B +VIN FDB
3 +

GND

OFF
D L2 D

1
2 VCC OUT1 2 1 C11 4

1
OUT TP

1
+ C93 C118 LM2576T-5.0 100uH .01uF

1
3

2
+ C107 C122 D3 R21 51 HFBR-2522
100uF .01uF D4
1N6373

2
25V 1000uF .01uF 1N6373
.25W FO2

2
1N5823 25V

2
1

2
R215

1
2 1 C10 2

A 0 OHM 1000pF

2
3 Amps
U6
(1,4)
RxDd 3
(1,4)
TxDd 1
2 HFBR-1522
+13VDC U72 4
OPTIONAL 1 8 CR2 6 OPTIONAL
VIN NC TP R143
2 VOUT VOUT 7 1 2 1 3 7
3 6 VCC 5
VOUT VOUT 39
TP

4 5 1N914

2
ADJ NC TP
75453
LM317 R112 VCC TT BAT LOW\

1
(1,4)
39 D1
R122

2
1 2 VCC

1
Schottky

1
R110
VCC 510 SRAM BAT LOW\
3

1
(1,4)

3
R120 680K D2 R35 VCC

3
1 21 Q1 R126 10K U12

1
2N3904 1 2 1 Q2 1 3 R40

2
10K 2N3904 1 8 10K OPTIONAL COMPONENTS TO BE USED ONLY
OUT1 V+ WHEN BT1 IS NOT INSTALLED.
2

430 R121 R52 R44

2
Schottky 1 2 1 2 1 2 2 7 CR1 VCC
HYS1 OUT2
R39 R36 R34 R22
1M 100K 22M 3 6 1 2 1 2 1 2 1 2 1 2
VCC 1% 1% SET1 SET2
R45

1
C C
U69 OPTIONAL 4 5 1 2 1M 100K 1K 100 1N5818
GND HYS2 1% 1% BT1
1 16

1
CHG VDD R43 22M C18 R13
2 15

1
DCHG N/C TP
1M 3.0V 10K
3 14 R146 ICL7665
TP
PFN VIN Lithium

2
4 13 2 1 BT2 1% R38 0.1uF
TP
MMN OPRF

2
5 12 51K VCC 1M
TP
CMN AUX1 TP
3.6V 1%
6 11 R163

2
TP
SEL0 AUX0 TP
NiCad

2
TP
8 SEL1 RC 10 2 1
7 9 R111

1
VSS MRN TP
C106 15K
ICS1722N 330K
2 100pF

1
VBATT
(1,3)
U64C

DWG NO.
VCC
5 6 RESET QUART
(1,4)

1
R141 U56A 40106

757 039 11
1 2
R138 1 2 RESET MEZZ
(1)
+13VDC 330K 10K
40106

2
VCC U63
RESET CPLD/F/O
(1,2)
3 5

1
VCC BATT/N TP

TT-BACKUP 1 2 VOUT
(1,8) VBATT VOUT (1,3,10)
R140
47K 12 CE\OUT
CE OUT (1,3)
13 CE IN

2
6 U64D U64E
LOW LN
9 PFI
15 9 8 11 10 RESET\ CPU/SEN/AUD
R119 RESET (1,2,4,5,11)
WCHDOG SEL\ 1 2 11
(1,3) WDI
16 40106 40106
0 OHM RESET

1
7 14 U56F
OSC IN WDO TP
B B

GND
R139 C88 8 10 13 12 INT2
OSC SL PFO (1,2)
6.04K

1
1% 47pF 40106

2
Supervisory (691) U56B

4
R109 R134
1K 1K 3 4 RESET\ SIMM
(3,10)

2
40106 U56C
8) TellTale 5 6 RESET\ I/O
(1,4)
TT-DISABLE\
(1,4,8) TT-DISABLE
U56D 40106
TT-BACKUP
9 8 RESET\ VIDEO
INTERROGATE (1,6,7)
(1,4,8) INTERROGATE TT-DET 40106
TT-CNTR1
DROPDOOR DET\ PA RESET\
(1,8) DROPDOOR DET TT-CNTR2 (1)

+13VDC LOW\
+13VDC LOW (1,6,8)
MAINDOOR DET\
(1,8) MAINDOOR DET BVAL OPEN\
BVAL OPEN (1,4,8)
MDOOR OPEN\
MDOOR OPEN (1,4,8)
BILLVAL DET\
(1,8) BILLVAL DET DDOOR OPEN\
DDOOR OPEN (1,4,8)
CCAGE OPEN\
DOORVAL OUT CCAGE OPEN (1,4,8)
(1,8) DOORVAL OUT TT-DET\
(1,4,8)
CARDCAGE DET\ TT-CNTR1
(1,8) CARDCAGE DET (1,4,8)

PAGE 8 TT-CNTR2 (1,4,8)

A A
VCC
U22 U69 ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO
INTERNATIONAL GAME TECHNOLOGY
U56E THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
1

C68 C77 C22 C80 C79 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
11 10 TITLE
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
TP TP
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
1
2

40106 BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
R116
10K CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
VSS
COVENANTS IT WILL NOT BE USED IN ANY MANNER
2

DW G. SIZE DW G. NO. REV LTR

DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE 9 OF 11
SHT __ __
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 27
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 10 OF 11

4 3 2 1

(1,2,3,6,7)
D[0..15]
A[1..31]
(1,2,3,4,5,6,7)

(3)
SRAM WE0\
(3)
SRAM WE1\
(1,3,9) VOUT
(3)
SRAM CE\
(3)
SRAM OE\ A18

BIT
(1,2,3,6,7)
RD\

GAME
U13
SRAM
U15 U14

A1 12 A0 D0 13 D0 A1 12 A0 D0 13 D0 A1 12 A0 D0 13 D0
A2 11 A1 D1 14 D1 A2 11 A1 D1 14 D1 A2 11 A1 D1 14 D1
A3 10 A2 D2 15 D2 A3 10 A2 D2 15 D2 A3 10 A2 D2 15 D2
A4 9 A3 D3 17 D3 A4 9 A3 D3 17 D3 A4 9 A3 D3 17 D3
D A5 8 A4 D4 18 D4 A5 8 A4 D4 18 D4 A5 8 A4 D4 18 D4 D
A6 7 19 D5 REF U13 A6 7 19 D5 REF U15 A6 7 19 D5 REF U14
A5 D5 A5 D5 A5 D5
A7 6 A6 D6 20 D6 32 pin DIP Socket A7 6 A6 D6 20 D6 32 pin DIP Socket A7 6 A6 D6 20 D6 32 pin DIP Socket
A8 5 A7 D7 21 D7 A8 5 A7 D7 21 D7 A8 5 A7 D7 21 D7
A9 27 A8
A9 27 A8
A9 27 A8
A10 26 A9
A10 26 A9
A10 26 A9
A11 23 A10
A11 23 A10
A11 23 A10
A12 25 A11
A12 25 A11
A12 25 A11
A13 4 A13 4 32 VOUT A13 4
A12 A12 VCC A12
A14 28 A14 28 A14 28

1
A13 A13 A18 C16 A13
A15 29 A14
A15 3 A14 CE2/A17 30 A15 29 A14
A16 3 A15
A16 31 A15
A16 3 A15
A17 2 A17 2 0.1uF A17 2
A16(1M) A16 A16(1M)

2
A18 30 A17(2M)
A19 1 NC/A18
A18 30 A17(2M)
A19 31 A19 31
PRG(A18) PRG(A18)
A20 1 A20 1
VPP(A19) VPP(A19)
29 WE
22 CE 22 CE1/CS 22 CE
24 OE 24 OE 24 OE

1MX8 EPROM 512KX8 SRAM 1MX8 EPROM

(1,3)
GAME SEL\ U36 U38 U37

A1 12 A0 D0 13 D8 A1 12 A0 D0 13 D8 A1 12 A0 D0 13 D8
A2 11 A1 D1 14 D9 A2 11 A1 D1 14 D9 A2 11 A1 D1 14 D9
A3 10 A2 D2 15 D10 A3 10 A2 D2 15 D10 A3 10 A2 D2 15 D10
A4 9 A3 D3 17 D11 A4 9 A3 D3 17 D11 A4 9 A3 D3 17 D11
A5 8 A4 D4 18 D12 A5 8 A4 D4 18 D12 A5 8 A4 D4 18 D12
A6 7 19 D13 REF U36 A6 7 19 D13 REF U38 A6 7 19 D13 REF U37
A5 D5 A5 D5 A5 D5
A7 6 A6 D6 20 D14 32 pin DIP Socket A7 6 A6 D6 20 D14 32 pin DIP Socket A7 6 A6 D6 20 D14 32 pin DIP Socket
A8 5 A7 D7 21 D15 A8 5 A7 D7 21 D15 A8 5 A7 D7 21 D15
A9 27 A8
A9 27 A8
A9 27 A8
A10 26 A9
A10 26 A9
A10 26 A9
A11 23 A10
A11 23 A10
A11 23 A10
A12 25 A11
A12 25 A11
A12 25 A11
A13 4 A13 4 32 VOUT A13 4
C A12 A12 VCC A12 C
A14 28 A14 28 A14 28

1
A13 A13 A18 C39 A13
A15 29 A14
A15 3 A14 CE2/A17 30 A15 29 A14
A16 3 A15
A16 31 A15
A16 3 A15
A17 2 A17 2 0.1uF A17 2
A16(1M) A16 A16(1M)

2
A18 30 A17(2M)
A19 1 NC/A18
A18 30 A17(2M)
A19 31 A19 31
PRG(A18) PRG(A18)
A20 1 A20 1
VPP(A19) VPP(A19)
29 WE
22 CE 22 CE1/CS 22 CE
24 OE 24 OE 24 OE

1MX8 EPROM 512KX8 SRAM 1MX8 EPROM

(1,3)
VBIT SEL\

DWG NO.
(3)
XM1 SEL\
(3)
XM2 SEL\
(3)
XM3 SEL\

757 039 11
VCC VCC VCC
J6 J7 J8
1 2 1 2 1 2
FW R0A\ FWR0A\ 3 4 XM1 SEL\ FWR0A\ 3 4 XM1 SEL\ FWR0A\ 3 4 XM1 SEL\
(1,3)
SRAM WE0\ 5 6 XM2 SEL\ SRAM WE0\ 5 6 XM2 SEL\ SRAM WE0\ 5 6 XM2 SEL\
FWR0B\ 7 8 GAME SEL\ FWR0B\ 7 8 GAME SEL\ FWR0B\ 7 8 GAME SEL\
A25 9 10 SRAM CE\ A25 9 10 SRAM CE\ A25 9 10 SRAM CE\
A24 11 12 VBIT SEL\ A24 11 12 VBIT SEL\ A24 11 12 VBIT SEL\
A23 13 14 WR0\ A23 13 14 WR0\ A23 13 14 WR0\
A22 15 16 WR1\ A22 15 16 WR1\ A22 15 16 WR1\
A21 17 18 XM3 SEL\ A21 17 18 XM3 SEL\ A21 17 18 XM3 SEL\
A20 19 20 D7 A20 19 20 D7 A20 19 20 D7
A19 21 22 D6 A19 21 22 D6 A19 21 22 D6
B A18 23 24 D5 A18 23 24 D5 A18 23 24 D5 B
A17 25 26 D4 A17 25 26 D4 A17 25 26 D4
A16 27 28 D3 A16 27 28 D3 A16 27 28 D3
A15 29 30 D2 A15 29 30 D2 A15 29 30 D2
A14 31 32 D1 A14 31 32 D1 A14 31 32 D1
A13 33 34 D0 A13 33 34 D0 A13 33 34 D0
A12 35 36 RD\ A12 35 36 RD\ A12 35 36 RD\
A11 37 38 SRAM OE\ A11 37 38 SRAM OE\ A11 37 38 SRAM OE\
A10 39 40 D15 A10 39 40 D15 A10 39 40 D15
A9 41 42 D14 A9 41 42 D14 A9 41 42 D14
A8 43 44 D13 A8 43 44 D13 A8 43 44 D13
A7 45 46 D12 A7 45 46 D12 A7 45 46 D12
A6 47 48 D11 A6 47 48 D11 A6 47 48 D11
A5 49 50 D10 A5 49 50 D10 A5 49 50 D10
A4 51 52 D9 A4 51 52 D9 A4 51 52 D9
A3 53 54 D8 A3 53 54 D8 A3 53 54 D8
A2 55 56 XM4 SEL\ A2 55 56 XM4 SEL\ A2 55 56 XM4 SEL\
A1 57 58 SIMMRDY\ A1 57 58 SIMMRDY\ A1 57 58 SIMMRDY\
GND 59 60 GND GND 59 60 GND GND 59 60 GND
FW R1A\ FWR1A\ 61 62 A31 FWR1A\ 61 62 A31 FWR1A\ 61 62 A31
(1,3)
SRAM WE1\ 63 64 VOUT 63 64 VOUT SRAM WE1\ 63 64 VOUT
FWR1B\ 65 66 A30 FWR1B\ 65 66 A30 FWR1B\ 65 66 A30
A26 67 68 A29 A26 67 68 A29 A26 67 68 A29
SRAM WE1\

A27 69 70 A28 A27 69 70 A28 A27 69 70 A28

RESET\ SIMM 71 72 XMB SEL\ RESET\ 71 72 XMB SEL\ RESET\ 71 72 XMB SEL\
(3,9)
72 Pin SIMM 72 Pin SIMM 72 Pin SIMM

(1,3,7)
FW R0B\
(1,3,7)
FW R1B\

(3)
XMB SEL\
(1,2,3,6)
WR0\
(1,2,3,6)
WR1\
(2)
SIMMRDY\
(3)
XM4 SEL\
A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

INTERNATIONAL GAME TECHNOLOGY
VCC THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO TITLE

BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
PROTECT GAME KING CTR/TT
1

C37 C17 C38 C15 CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT
0.1uF 0.1uF 0.1uF 0.1uF COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
2

DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE

RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE SHT10
__ OF 11
__
4 3 2 1

28 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) OCTOBER 15, 2001
PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC 757-039-11 REV A PAGE 11 OF 11

4 3 2 1

OUT CLK U51

(4) PD0 4 2
D1 Q1 TP
E23
Q1 3 PAD
PD1 5 D2 Q2 7 TP
OUT SEL\ 28070000h 4 6 E24
(1,3,4) Q2 PAD
6 PD2 12 D3 Q3 10 TP

5 74AC32 11 E25
U19B Q3 PAD
PD3 13 D4 Q4 15 TP

14 E16
Q4 PAD
9

1
RESET\
CLK
1 CLR 74HC175
R106 R222 R223 R224
D 10K 10K 10K 10K D

2
IA1
(1,2,4,7) J4,27C

PD[0..7]
(1,2,4,5,7)

IO WR\
(1,2,3,4,5,7)

RESET\ CPU/SEN/AUD
(1,2,4,5,9)

(1,3,4)
SOUND SEL\

Audio Pre-Amp Power

U50 C65

1
+13VDC 3 1 1 2 C85
(1) J2,1A\1B VI VO

GND
1 0.1uF 0.1uF

2
AUDIO
+ C59 LM340LAZ-5.0 + C69

2
4.7uF 4.7uF U55
R130 C84 1 16
GND VCC
2

2
2 12 1 15 RO D0 17 PD0

+
C
14 MO D1 18 PD1
C
2.2K 2.2uF 13 2 PD2
10V IC D2
12 3 PD3

1
CS D3
11 4 PD4
1

WE D4
D5 5 PD5
AUDIO R132 YM2413 XIN 8 6 PD6
R216 R207 2.2K XIN D6
D7 7 PD7
0 OHM 0 OHM 9 10 IA1
XOUT A0

2
3 Amps 3 Amps
2

AUDIO YM2413
A B E18
R129 C83 YM2413 XOUT
2 12 1 Y4

+
1 2

1
C94 R144 2.2K 2.2uF
MM AUDIO1
(1,4) J5,21C 2 1 2 1 10V 3.579 MHz AUDIO
R131
+

1
2.2uF 10K 2.2K C67 C66

DWG NO.
10V

2
15pF 15pF

757 039 11
R151 R166
+25VDC 1 2 1 2 AUDIO
(1) J1,18A/18B

22K 22K
1
1

C115 + C97
1

C96
0.1uF 100uF

+
1 2
2

25V R167
22K 10uF
35V
2

C89 .001uF
2 1
AUDIO

B 2 1 B
5

U79
C121 LM1875 1 R135 10K
SPEAKERA+ +
(1,4) J2,4A 2 1 4
+

- 2 AUDIO
1000uF

1
25V
U54B
3

E19

8
C95 U54A R124

8
6 10K
-
AUDIO 1 2 7 - 2
LM358

2
AUDIO + 5 1 LM358
1.0uF 3
+
R164

1
4
1 2
REF U79A3

4
REF U79A1 REF U79A2 + C90
150K R128
AUDIO 2.2uF 10K
1

2
10V

2
HEATSINK COUMPOUND CLIP
R162 R165
HEAT SINK 1 OHM 10K
AUDIO
2

2
1
1

C110 + C111
10uF
0.22uF
2

R180
SPEAKER- 1 2
(1,4) J2,3A

0 OHM
AUDIO
VCC

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

1

C75 INTERNATIONAL GAME TECHNOLOGY

1

C60 THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF

0.1uF 9295 PROTOTYPE DRIVE RENO, NV 89511
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
2

0.1uF TITLE
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
2

BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED

BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
SCHEMATIC, GAME KING 2
CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT PROTECT GAME KING CTR/TT
COVENANTS IT WILL NOT BE USED IN ANY MANNER DW G. SIZE DW G. NO. REV LTR
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND. C 757 039 11 A
DRAW N DATE CHECKED DATE APPROVED DATE SCALE
TDW 01NOV99 NONE SHT11
__ OF 11
__
4 3 2 1

OCTOBER 15, 2001 ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01) 29