11.

CIRCUIT DIAGRAM
11.1. Circuit Diagram of RF Band-1

modify0512
E3B
E3D
B1100
CPL + VBAT
BEAD
C1102 C1156 C1101
C1161 E3D C1103 33p 12p - 220uF
10n R1103
C1155
AN1161 L1101 1 2

2
DCSTX [8]
JP J1161

9
8
7
6
5
JP U1101
GND 6

OUT
L1162 L1161 GND 5 33p NM

4
3

VCC

GND
GND
15nH 15nH GND 4 C1106 C1105 C1115

IN
GND 3 U1131 NM NM

GSM OUT
MM8430-2600 4

1
10 GND BS BS [8]

DCS/PCS IN
modify0512 1 7 C1116
G/O G/I
2 G G 6 11 VCC Vcmos 3
3 5 33p

ISO CPL
C1185 E3D D/O D/I
12 GND VAPC 2 VAPC
NM C1154 LDC15D19 C1108 C1107 220

8
10n 100p R1101
C1143 22p C1114

DCS/PCS OUT
GND
GND
VCC
GSM IN
modify0512 C1131 C1111 JP
[8] GSMRX
C1141 NM R1131 CX77314 R1142

13
14
15
16
33p 39p 51 1k
C1157 L1102 6.8p 3
4

L1141 NM 4.7nH E3D E3D

2
13
7
NM U1141 C1110
NM C1112 C1113
10n 33p 2 1

ANT
GSMTX [8]

G_TX
modify0529 U1171 R1102

D/P_TX
16 G_RX VC1 11 6 2 TRSW_GT [1]
C1144
4.7K
[8] DCSRX 10 D_RX VC2 14
C1171 1 5 TRSW_DT [1]
3n9 L1142 9 4 33p 4.7K
U1172
0.5p P_RX VC3
6 2 TRSW_PR [1]
3 4 4.7K
C1173

GND
GND
GND
GND
GND
GND
GND
PEMB3 1 5
10p C1172

1
3
5
6
8
4.7K

12
15
C1145 10p Mode Vc1 Vc2 Vc3
SHS-L090TL 3 4 G_TX 1 0 0
[8] PCSRX
D/P_TX 0 1 0
12p PEMB3 G/D_RX 0 0 0
L1152 P_RX 0 0 1
NM
U1173

[8] VRF 1 OUTA OUTB 8

VTX[ 8]
2 7 C1176
[8] VSYN OUTC VCC 1u/0603
VTCXO 3 ENBC GND 6

4 ENA VREF 5
C1175
C1174 C1178
C1184 MAS9122 C1177
33p 1u/0603 10u/0805
R1190 R1192 1u/0603 10n/X7R
51.1 R1191 51.1
CPL 1 RFIN VCC 8
910 R1196 R1197 R1199
[1] RF_TXEN 2 ENBL VAPC 7 PA_EN [1]
R1193
JP JP 1k2
[2] RAMP 3 VSET NC 6
R1198
51k
4 5 1k
FLTR G
C1180 C1181 U1103 AD8315
15P 68p C1182
150p
R1195 VAPC
JP

111
11.2. Circuit Diagram of RF Band-2

TP1 TP2 TP3 TP4

1
1
1
1
VRF RXIP
RXIN
VTX L1241 C1246 C1245 RXQP
27n 100n 22p RXQN
C1249 C1248 C1247
VRF
33n 33p 10p C1244
100n
GSMTX
C1253
VSYN
33p C1250 B1241
2p7 BEAD
C1242 C1243
DCSTX C1241 10u 22p
C1254 0.1u B1222
C1252 18p R1202 BEAD
180R C1203 510/1% C1229 R1225 R1226
TP9 TP10 2.2n/X7R 220p 5k6 2k

56
55
54
53
52
51
50
49
48
47
46
45
44

1
1
L1201 C1228 TP5 TP6 TP7
1
1
1

R1203 180n/0603 C1204 C1227 8n2/PC

C1202 220/1% 39p/NPO U1201 680p

RXIP
RXIN

VCC4
VCC3
39p/NPO

RXQP
RXQN

TX900
1 43

UHFBYP

VCCUHF
RXEN1 RXENA VDDBB

UHFTUNE
E3B 2 42
RF_TXEN LE

VCCTXVCO
modify0522 TXENA LE

TXVCOTUNE
BS R1231 3 PCO CLK 41 CLK

TX1800/TX1900
VTCXO R1295 4 VCXO_EN DATA 40 R1296 DATA R1232
NM 5 PDETVCC XTALTUNE 39 AFC
R1204 JP 6 VCC1 SXENA 38 NM SXEN 10k
7 TXCPO VCCFN_CP 37
E3D TP8 C1230
1

390 8 TXINP UHFCPO 36

9 35 C1226 R1224 modify0522 100n
R1205 LNA900IN GNDFN 10p 10 E3B R1294
10 GNDLNA900 XTAL 34
R1206 11 33 JP
510 51 LNA1800IN VCCF
12 PDET VCCD 32
13 LNA1900IN GNDD 31 C1291
14 30 R4 U1291
R1207 NC XTALBUF NM
VRF 15 NC LPFADJ 29 2 GND Vc 1
100n 3 4
10 C1262 R1221 o/p Vcc

PAVAPC
BBVAPC
TXIP
TXIN
TXQP
TXQN
TXIFP
TXIFN
VCC2
CAPIP
CAPIN
CAPQP
CAPQN
C1205 39k/1% VTCXO R1293
100p 15p R1292

16
17
18
19
20
21
22
23
24
25
26
27
28
U1261 CX74063 R1291 100nF BEAD
C1265
GSMRX 1 IN G 4 NM
2 G OUT 3
C1225
SAFSE942 L1261 C1221 C1223 C1224 1n 13MHz_BB
15p 8n2 22p 22p 100n R1297 JP
U1271 del C1222 R1223
C1266 E3B
1 4 C1214 C1215 10 B1221
3
2
1

DCSRX IN G L1211 VTX

2 3 82n 470p 470p R1222 BEAD
G OUT L1271 C1216 10
B7744 JPE3C 3n9 100n
modify 0529 VRF
C1271 E3C
U1272 0p5 modify 0529
C1267 TXQN
PCSRX 1 IN G 4 TXQP
2 3 C1211
G OUT TXIN
L1272 22p
TXIP
B7740 C1272 3n9
12p 0p5

C1212 C1213
NM NM

112
11.3. Circuit Diagram of GSM Processor

VCO RE VMEM

VCO RE SIMVCC VMEM VMEM VRTC

C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
R101
0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C

0R/0402R + BAT101
C112 SEIKO XH414H
0.1U /0402C
D[0..15]
D[0..15]

H1
P7
K14
C8
L9
L2
N5
N9
N13
B14
B10
C6
D5
E3
A2
LCD_CTL U101
ADD[1..22] H4 N6 D0
ADD[1..22] ADD0 DATA0
ADD1 J3 P6 D1
ADD1 DATA1

VSIM

VCC1
VCC2
VCC3
VCC4
ADD2 J2 M6 D2

VEXT1
VEXT2
VEXT3
VEXT4
VPEG1
ADD2 DATA2

VMEM1
VMEM2
VMEM3
VMEM4
ADD3 J4 N7 D3

VDDRTC
ADD4 ADD3 DATA3 D4
K3 ADD4 DATA4 M7
ADD5 K2 L7 D5
ADD6 ADD5 DATA5 D6
K4 ADD6 DATA6 P8
ADD7 L4 N8 D7
ADD8 ADD7 DATA7 D8
L1 ADD8 DATA8 M8
ADD9 L3 P9 D9
AD D10 ADD9 DATA9 D10
L5 ADD10 DATA10 M9
AD D11 M1 P10 D11
AD D12 ADD11 DATA11 D12
M2 ADD12 DATA12 N10
AD D13 N1 M10 D13
AD D14 ADD13 DATA13 D14
P1 ADD14 DATA14 P11
AD D15 N2 N11 D15
AD D16 ADD15 DATA15
P2 ADD16
AD D17 N3
AD D18 ADD17
M3 ADD18 RD M11 RD
AD D19 P4 N12
AD D20 ADD19 HWR HWR
N4 ADD20 LWR P13 LW R
AD D21 M4 P14
AD D22 ADD21 WE WE
P5 ADD22(nDISPLAYCS) ROMCS M13 ROMCS
RAMCS M14 RAMCS
KEYR OW_0 A6 KEYPADROW0
KEYR OW_1 F4 KEYPADROW1
KEYR OW_2 D4 KEYPADROW2 TXPA (GPO_2) G13 TRSW_GT
KEYR OW_3 B5 KEYPADROW3 PA_NEGBIAS (GPO_4) H12 RXEN1
KEYR OW_4 A5 KEYPADROW4 TXPHASE (GPO_7) F14
KEYC OL_0 C4 KEYPADCOL0 DCS_SW_SYNC (GPO_8) F13 TRSW_DT
KEYC OL_1 E4 KEYPADCOL1 DCS_SW_DRV (GPO_9) H11 TRSW_PR
KEYC OL_2 B4 KEYPADCOL2
KEYC OL_3 A4 KEYPADCOL3
KEYC OL_4 C3 KEYPADCOL4 TX_GSM (GPO_16) E13
ADD23(TX_DCS)GPO_17 G11 RF_TXEN
E12 TP124
(OTH_EN)GPO_18 SXEN
BBCLK L12 CLKIN (OTH_VLO_EN)GPO_19 D14 LE
G14 D13 RXEN
1

CLKON CLKON (OTH_DATA)GPO_20 DATA

B3 OSCOUT (OTH_CLK)GPO_21 F11 CLK
X101 R102 A3 B1
MC-146 10M/0603R OSCIN (RXON)GPO_0 RXEN
POW ER_ON B2 PWRON (TXON)GPO_1 C2 TXEN
SYS_ PWR_ON E14 GSM_SW_DRV (GPO_11) GPO_3 G12 PA_EN TP101

NRESET N14 RESET 1

C113 C114 D1
CLKOUT CLK_OUT TP_CLKOUT
EOC D11 GPIO_0 CLKOUT_GATE D2 CLKOUT_GATE
TBD TBD D10 E1
CHG_GAT E_IN GPIO_1 (VBCRESET)GPO_24 VBC_RESET
LC D_ID B12 GPIO_2 (ARSM)GPO_5 A1 ARSM
CH G_EN C11 GPIO_3 (ATSM)GPO_6 C1 ATSM
D9 E2 VMEM 1 TP129
TP126 CHG_DET GPIO_4 ASDI AS DI RX
1 B11 GPIO_5 ASDO F1 ASDO
TP_GPIO5 A11 F2
PJ_ACC_ IN GPIO_6 ASFS ASFS
C10 1 TP130
MIC_ON GPIO_7
D8 TX
YMU_IRQ GPIO_8
TP104 1 A10 F3
2
4

TP_GPIO9 GPIO_9 BSDO BSDO R103 VMEM TP106

GPIO10 C9 GPIO_10 BSOFS G4 BSOFS 1
TP125 1 C7 G2 TP_USC0
TP_GPIO11 GPIO_11 BSDI BS DI
VIB_ON B9 GPIO_12 BSIFS G1 BSIFS
A9 G3 1 TP113
PJ_FUNC_ SEL GPIO_13 VSDI VS DI
B8 H3 TBD TP_USC1
1
3

TP102 GPIO_14 VSDO VSDO R105

1 YMU_AVCC _ON A8 GPIO_15 VSFS H2 VSFS
TP_GPIO14 D6 100K/0402R 1 TP115
TP105 GPIO_16 TP_USC2
1 B7 GPIO_17
TP_GPIO16 H14 C14 US C0
TP107 GPIO_18 USC0 US C1
1 H13 GPIO_19 USC1 D12 US C1
TP_GPIO17 J12 A14 US C2
TP108 TCK GPIO_20 USC2 US C3 US C2
1 J11 GPIO_21 USC3 A13
TCK E11 US C4
TP109 TMS USC4 US C5 TP112
1 USC5 C12 1
TMS C5 B13 US C6 TP_USC3
BL_KEY BACKLIGHT1 (GPO_23) USC6
TP110 1 TDI A7
BL_LC D BACKLIGHT0 (GPO_22)
TDI 1 TP114
TP111 1 TDO J13 TP_USC4
2
4

SIMDATAOP SIM_IO
TDO M5 K12 R107 R106
LCD_ CS nDISPLAYCS(LCDCTL) SIMCLK SIM_CLK 100K/0402R
L10 1 TP116
SIMRESET (GPIO_23) SIM_RESET TP_USC5
LCD_NRST F12 SM_SW_SYNC (GPO_10) SIMSUPPLY (GPIO_24) K13 SIM_ON
TP128 1 L13 J14
GPCS1 GPCS1 SIMVPROG (GPIO_22) SIM_PROG TBD TP118
M12 1
1
3

YMU_CS GPCS0 TP_USC6

TP123 1 L14 K11
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
VSSRTC

TP_GPIO32 GPIO_32(WAIT) JTAGEN

AD6525 1 TP122
J1
L6
L8

K1
P3
B6
D7
D3

TP_JTAGEN
L11
P12
A12
C13

113
11.4. Circuit Diagram of Voiceband, Baseband and Codec

VMEM VANA VCO RE VMEM VANA VCO RE

R213

C201 C202 C203 C204 C205 C206 C207

100K/0402R
2.2U /0603C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C 0.1U /0402C

2
4
R201
100K/4P2R

1
3
F10
A9
J8
A1
G1
K5
U201

ASDO H1 ASDI ITXP F9 TXIP

H2 E9

AVDD1
AVDD2
AVDD3
ASFS ASFS ITXN TXIN

DVDD1
DVDD2
DVDD3
AS DI J1 ASDO QTXN C9 TXQN
QTXP D9 TXQP

VSFS D2 VSFS IRXP E10 RXIP

VS DI D1 VSDO IRXN D10 RXIN
VSDO E1 VSDI QRXP C10 RXQP
TP207 1 B10
BSIFS QRXN RXQN
TP205 1 E2 A10
BSIFS BSOFS AFCDAC AFC
BS DI F1 H9
BS DI BSDO RAMPDAC RAMP
BSOFS F2 BSIFS
G2 R206
BSDO BSDI 100K/0402R
TP208 1
BSOFS
1 ATSM K3 ATSM
TP206 J3
BSDO ARSM ARSM
REFOUT A7
REFCAP A8
CLKOUT_GATE K2 MCLKEN
J2 C213 C212 C218
CLK_OUT MCLK
0.1U /0402C 0.1U /0402C 2.2U /0603C
TXEN K4 TXON
RXEN J4 RXON

VINNORP J10 VINNORP

VBC_RESET K1 RESET VINNORN K10 VINNORN
TP201 H10
VINAUXP VINAUXP
1 B2 TDI VINAUXN G10 VINAUX N
B1 TP202
TP_VBCRST TDO
C2 TMS VOUTNORP K8 VOUTNORP
C1 K7 TP_BUZZER
TCK VOUTNORN VOUTNORN
1

VOUTAUXP K9 VOUTAUXP
B4 K6

2
4
IDACOUT VOUTAUXN VOUTAUXN
A3 IDACREF
R207 J6
100K/4P2R BUZZER BUZZ ER

1
3
BAT_VOLTAGE
C214
A6 10nF/ 0402C VANA
AUXADC1
A5 Charging T emp
AUXADC2
B5 R208
AUXADC3 200K/0402R /1%
AUXADC4 A4
VANA
AUXADC5 B6

B7 C215 R209
AUXADC6 R210
NTC

NC(MICCAP)
NC(REFCAP2)
AGND4
AGND3
AGND2
AGND1
DGND1
DGND3
100K/0402R /1% 0.1U /0402C 100K/N TC/0402R
AD6521

J9
J7
J5

B9
B3
B8
A2

G9
BATTEMP
C216 VANA

0.1U /0402C

R211
200K/0402R /1%

PCB_Temp

C217 R212
100K/N TC/0402R
NTC

0.1U /0402C

ADC5 1 TP203
ADC5

ADC6 1 TP204
ADC6

114
11.5. Circuit Diagram of Power Management System

VBAT

VBAT
C301 C302
4.7U /0805C 0.1U /0402C VRTC VANA VCO RE
CON3 01
TP301
1 1 VBAT
TP_VBAT VBAT
2 TP303 C303 C304 C305

24
32
17
BATTEMP BAT_TEMP POW ERON_ KEY U301 0.1U /0402C 4.7U /0805C 4.7U /0805C
TP302 22 5

1
VBAT MVBAT BAT_VOLTAGE

NC
NC
NC
1 3 GND R301 19
TP_GND C325 100K/0402R VBAT2
39pF BAT_CON R302 4
100K/0402R BATSNS
U302 DAN2 22 2 VRTCIN VRTC 3 VRTC
VMEM SIMVCC VTCXO
POW ER_ON 2 POWERON_ IN 29 23
3 PWRONIN VAN VANA
SYS_ PWR_ON 1 TP304
POWER_KEY 30 PWRONKEY VCORE 21 VCO RE EOC
KEYR OW_4 31 ROWX VMEM 20 VMEM
C306 C307 C308

1
1 18 4.7U /0805C 2.2U/0805 1U/0603C
SIM_ON SIMEN VSIM SIMVCC

CLKON 28 TCXOEN VTCXO 25 VTCXO

TP306 1
CH G_EN 14
CH G_EN CHGEN

SIM_PROG 8 SIMVSEL EOC 13 EOC

TP305 1
CHG_GAT E_IN 10 6 TP307
CHG_GAT E_IN GATEIN CHRDET CHG_ DET
R313 1
7 CHRIN RESET 16 NRESET CHR_ DET
12 15 0R
ISENSE RESCAP
9 GATEDR REFOUT 26
CON3 02 U307 C311
U312

AGND
DGND
F302 FDC640P 0.1U /0402C
1 1 2 4 1 ADP3522XCP-3.0
1

27
11
2
FULSE/0603 C319 5 C309

2
2
C310 CRS03 0.01U /040 2C R303
6
U306 U308 10N/0402 0.3/0805R

T301
2 2
2.2U /25V/0805C BLM55C9V1 1 6

1
3

22 K
R311

1
P_JACK 2 5 TBD
U309
U311
C322 SI3443DV
R310 4 3 0.1U 4 1 1 2 VBAT

22 K
10K 2
EMD2 5 CRS03
6
R309
10K

3
C312 C323
C321 10N/040 2C 0.1U
0.1U

VTCXO

R314 C317 R3
10N/040 2C TBD
CLKON
TBD
1 D VCC 5

13MHz_BB 2 A L301 C324

3 GND Y 4 BBCLK
U305 NC7SZU04P5X 2.2uH /060 3R
18pF
C318
68pF
R307

1M/0402R

115
11.6. Circuit Diagram of Memory & SIM

VMEM

D[0..15]
D[0..15]
C401

0.1U /0402C

ADD[1..22]
ADD[1..22]

J5
J6
U401
VMEM D0 J3 G2 ADD1
D1 DQ0 A0 ADD2
G4 DQ1 A1 F2

VCCf
VCCs
D2 K4 E2 ADD3
D3 DQ2 A2 ADD4
H5 DQ3 A3 D2
D4 H6 F3 ADD5
D5 DQ4 A4 ADD6
K7 DQ5 A5 E3
D6 G7 D3 ADD7
D7 DQ6 A6 ADD8
J8 DQ7 A7 C3
D8 K3 C7 ADD9
D9 DQ8 A8 AD D10
H4 DQ9 A9 E7
D10 J4 F7 AD D11

8
7
6
5
D11 DQ10 A10 AD D12
K5 DQ11 A11 C8
R401 D12 J7 D8 AD D13
D13 DQ12 A12 AD D14 SIMVCC
H7 DQ13 A13 E8
0R/8P4R D14 K8 F8 AD D15
D15 DQ14 A14 AD D16 TP401
H8 D9

1
2
3
4
DQ15/A-1 A15 AD D17
A16 G9 1
F4 AD D18
A17 AD D19 TP_SIMVCC
A18 E4
WP -ACC C5 D7 AD D20
CI Os WP/ACC A19 AD D21
K6 CIOs A20 E6
CI Of H9 E9 AD D22 R405 R403
CE2 s CIOf A21 100K/0402 10K/0402
D6 CE2s

TP403 TP402

H3 F9 TP_SIMCLK TP_SIMRST
RD OE NC0
HWR D4 UB
C4

1
LW R LB
C6 J401

1
WE WE
ROMCS H2 CEf
J2 5 6 1 TP405
RAMCS CE1s R404 VCC GND GND
SIM_RESET 3 RST VPP 4
NRESET D5 RESET 150R/1%/0402 1 2
R406 SIM_CLK CLK I/O SIM_IO

GPIO10 E5 RY/BY
TBD C405 C402 SIM SOCKET C404
R407 22pF TBD C403 33pF
1

G8 0.1U /0402C
VMEM SA
0R/0402R
TP404

VSS
VSS
AMD (64+16PS)

J9
G3
TP_SIMIO

116
11.7. Circuit Diagram of Audio 1

TP502 TP501
1 I/O 1 I/O 6 6
SPK1 SPK2 TP_SPK-N TP_SPK-P
2 GND1 GND2 5

1
1
VBAT 3 4
R521 I/O 3 I/O 4
U507 ESDA
R503
100K
R522 U505 YMU_AVCC VOUTNORP

YMU_AVCC _ON 1 5 0R/0402R LS502

N O
2 I
0R/0402 3 4 C522
C G
SC1563ISK-3.0 R504 TBD/0402C RECEIVE R - B
C527 C525 C526
TBD/0402 2.2U/0603 4.7U/0805 VOUTNORN
0R/0402R
C524 C531 C523 C532

2
2
33P/0402C 33P/0402C 33P/0402C 33P/0402C

1
1

T503 - B (TBD)
T504 - B (TBD)

VOUTAUXN

C520
TBD/0402

R510
TBD
YMU_AVCC

C517 R508 R514 C521

VR EF
BUZZ ER
C512 C519 C529
0.1U 0.1U TBD 10N/040 2C 20K/0402R 10K/0402R 0.1U /0402C
VMEM

9
15
12
U506

32 SPK1

EQ1
SDOUT(IOVDD)

VREF
7 VDD EQ2 13

SPVDD
5 R509 C518 SPK2
IFSEL(NC)
6 PLLC 47K/0402R 200P/0402C
C530 C513 C528 14
0.1U /0402C 0.1U /0402C 0.01U EQ3
LS501
8 YMU762(MA3L2) 17
VSS SPOUT1 C511
16 SPVSS
18 TBD/0402C
SPOUT2 SPEAKER
YMU_IRQ 3 /IRQ
NRESET 4 /RST
1 10 HPOUT C515
2
2

CLK_OUT CLKI HPOUT-L/MONO

11 C516
HPOUT-R 33P/0402C 33P/0402C
2 EXT1 1
19 TP503
1
1

YMU_VIB

SDIN(/CS)
SCLK(/RD)
/WR
SYNC(A0)
D0
D1
D2
D3
D4
D5
D6
D7
EXT2 HPOUT_R
T501(TBD)
T502(TBD)

29
31
28
30
27
26
25
24
23
22
21
20

D0
D1
D2
D3
D4
D5
D6
D7

YMU_CS
RD
WE D[0..15]
ADD2
ADD[1..22] D[0..15]
ADD[1 ..2 2]

117
11.8. Circuit Diagram of Audio 2

VBAT MIC_PWR MIC_PWR

U601 R626
TP601
1 5 MIC_PWR
N O
2 I 1
3 4 2.4K/0402R
MIC_ON C G R624 R602 C603
LP2985AIMX5-2.5 C601 4.7K/0402R 0.1U /0402C TP_MIC
0R
C629 C602 C626 C627
2.2U /0603C 10N/040 2C 10U/0805C 10U/080 5C 0.1U /0402C
R621
VINNORP MIC601
0R 1
C623 C605 2
100P/0402 C621 C606 TBD/0402C
VINNORN MICROPH ONE - B
TBD/0402C

2
2
C607 0.1U
33P/0402C C608 R628 R603 1 6
33P/0402C TBD/0402R 0/0402R I/O 1 I/O 6

1
1
2 5

T602(TBD)
T603(TBD)
GND1 GND2
3 I/O 3 I/O 4 4
U605 ESDA

YMU_AVCC

C631
R609
1M

0.1U
R641
US C2
R615 R610 8.2K
47K 1M C630 US C6
2.2uF/0603 PJ_ACC_ IN VMEM

C614 R611 C616 VMEM

HPOUT
0.1uF 0R 10uF/0805
PJ_FUNC_ SEL
C628
VOUTAUXP R633 R637
10uF/0805 R625 100K/0402R 100K/0402R
0R U603 R640
US C1 1 B1 S 6
1 J601
100K TX 1
2 5 SPK 4
MIC_PWR GND VCC ACC_ IN 6
0 5
3 4 MIC/RX 3
B0 A GND 2
R630 NC7SB3157 R632
0R TBD 1 6
2
2
2
2
2

C615 R639 I/O 1 I/O 6

33P/0402C 1MR 2 5 PHONEJ ACK-B
GND1 GND2
1
1
1
1
1

3 4
T606 - B

R643 I/O 3 I/O 4

C622 0R U604 - B ESDA
T607 - B (TBD)
T604 - B (TBD)
T605 - B (TBD)
T601 - B (TBD)

R623 R606 0.1U /0402C

0R 1.2K /1%

R620
EXT_MIC
VINAUXP
0R R642
C624 TBd
C620
100P/0402
VINAUXN

0.1U
C610 C611 R629 C612
TBD/0402R
33P/0402C 33P/0402C TBD/0402C
MIC/ RX SPK TX GND

118
11.9. Circuit Diagram of User Interface

TP21 1
D8
TP20 1
D9
VMEM VBAT TP19 1 LCD_PWR
LCD_PWR D10
TP18 1
U703 D11
1 5 1 TP28
N O LCD_ PWR TP17
2 I 1
3 4 D12
C G TP16 C701
1
LP2985AIMX5-3.0 C735 C737 D13 C733 C7
C736 10U/0805C TP15 1 2.2U /060 3 -B 0.1U /040 2 -B 33P/0402C
2.2U /0603C 10N/040 2C D14
TP14 1
D15

TP13 1
LCD_CTL U701
TP22 1
LCD_ CS 1
TP23 VEE
1 2 VEE
ADD2 3
U706 VDD
4 VDD
12 N/C 5 SEL68
KEYR OW_3 1 KEYROW_3 6 VSS
2 D[0..15] 7
KEYC OL_4 KEYCOL_4 D[0..15] LCD_CTL RD(E)
3 D15 8
KEYR OW_0 KEYROW_0 ADD[1..22] D7
4 D14 9
KEYC OL_3 KEYCOL_3 ADD[1 ..2 2] D6
5 D13 10
KEYR OW_1 KEYROW_1 D5
6 D12 11
KEYC OL_2 KEYCOL_2 LCD_PWR D11 D4
KEYR OW_2 7 KEYROW_2 12 D3
8 D10 13
KEYC OL_1 KEYCOL_1 D9 D2
KEYC OL_0 9 KEYCOL_0 14 D1
10 D8 15
POWER_KEY POWER_KEY D0
11 R708 16
GND LCD_ CS CS
13 R707 TBD - B ADD2 17
N/C RS
LCD_NRST 18 RESB
KEYPAD_HOT BAR - B 19
WE WR
10K - B 20
TP24 VSS
1 21 VSS
LCD_NRST 22
TP25 C741 C742 C743 C744 C745 C746 C747 C748 C749 C750 C751 C752 C753 CA_LED
1 23 CA_LED
WE 24
TBD - B 0.1uF - B TBD - B TBD - B TBD - B 18pF 18pF 18pF 18pF 33pF 33pF 33pF 18pF AN_LED
25 AN_LED
26 N/C(VOUT)

VBAT TP27 1 Wintek DX1209K-6C LWa - B

V_LED GND
1 TP30
U704 V_LED
R709 100K 3 1
C754 VIN VOUT TP701
4 CD4
10U/080 5C 2 C738 1 LCD_ ID
CF1+ 1U/0603C
5 CX8 CF1- 9
CF2+ 10
R710 6 7 C739 C740
BL_LC D
GND

100K EN CF2- 1U/0603C 1U/0603C

SC600BIMLTR, 5V_ 60M A
8

R711 R712
TBD TBD

VBAT
JP702 R715
0R

1
2
3

1
2
3
V_LED VBAT
LC D_ID
1 TP29
VIB_PW R R716
C755 TBD

2
M701 TBD
+
LG COIN M OTOR
D713
A
D701 D702 D703 D704 D705 D706 D707 D708 D709 D710 1SS355
-
LE D - B LE D - B LE D - B LE D - B LE D - B LE D - B LE D - B LE D - B LE D - B LE D - B

1
1 TP12
Vibrator SIG

8
7
6
5
R701 R713

8
7
6
5
R714 100R /1%/0402 R - B 100R /1%/0402R - B
200R /8P4R - B R702 R704
TBD - B 8.2R/0805R - B

1
2
3
4
U702

1
2
3
4
U705
6 C1 C2 3
R706
2 VIB_ON
BL_KEY 2 B1 B2 5 3
1 YMU_VIB
R705 1 4 100R /0402R - B
1K/0402R - B E1 E2 DAN222 - B

FFB2222A - B

119
11.10. Circuit Diagram of Keypad

KEYCOL_0
KEYCOL_1
KEYCOL_2
KEYCOL_3
KEYCOL_4

SW701 SW702 SW703 SW704 SW705

1 2 1 2 1 2 1 2 1 2

KEY [*] KEY [7] KEY [4] KEY [1] KEY_[UP] KEYROW_0

SW706 SW707 SW708 SW709 SW710

1 2 1 2 1 2 1 2 1 2

KEY [0] KEY [8] KEY [5] KEY [2] KEY_[DOWN] KEYROW_1

SW711 SW712 SW713 SW714 SW715

1 2 1 2 1 2 1 2 1 2

KEY [#] KEY [9] KEY [6] KEY [3] SOFTKEY_LEFT KEYROW_2

SW716 SW717
1 2 1 2

SOFTKEY_RIGHT KEY [SEND] KEYROW_3

SW718
1 2

POWERKEY & END POWER_KEY

1110
12. LAYOUT DIAGRAMS
12.1. Main PCB

Z1

26

800Z

0
9122

Y762C
Z1

84VD23381FJ-80
Z3 Z3

AD6525ACA
H

S3KV
Z1

LUNA 600B

D2

640
R300 227
ADP3522 L00A

43

S3KV
6330

121