WEEK 2-2013

Directives, Assembler
Rules/Data Processing

ELEC2142: Embedded Systems Design

 Assembly Structure
Directives instructions to the assembler to create ,
for example, memory area for code (AREA), to
align data (ALIGN), mark the end of code (END)
etc

Directives do not turn into actual machine code

unlike instructions

The general form of source lines in your assembly

{label} {instruction| directive|pseudo-instruction} {,comment}

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 Assembly Structure
Directives instructions to the assembler to create ,
for example, memory area for code (AREA), to
align data (ALIGN), mark the end of code (END)
etc

Directives do not turn into actual machine code

unlike instructions

The general form of source lines in your assembly

{label} {instruction| directive|pseudo-instruction} {,comment}

where each field in braces is optional

3
 Assembly Structure
Labels are names that you choose to represent an
address somewhere in memory
do eventually translated into a numerical value
defined only once in your code
start at beginning of the line
The instructions, directives, and pseudo-instructions
must be preceded by a white space.
Blank lines are allowed and improve readability.
Beginning of a comment is indicated by the first
semicolon and the end of a comment is defined by
the end of the line
Constants are declared in various formats:

4
 Assembly Structure
Constants are declared in various formats:
Decimal, for example, 123
Hexadecimal, for example, 0x3F
n_xxx where:
n is a base between 2 and 9
xxx is a number in that base

Character constants consist of opening and closing

single quotes, enclosing a single character or an
escaped character.
String constants are contained within double quotes.
str1 SETS Hello world!\n
MOV r3, #A
5
 Assembly Structure
Directives, mnemonics, symbolic register names can
be written in either uppercase or lower case, but we
can not mix them
ADD or add are acceptable, but not Add.

A single line may be split up into several lines by

placing a backslash character (\) at the end of a line.

ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_stack_Size + \

FIQ_Stack_Size + IRQ_Stack_Size)

6
 Frequently used directives
AREA defines a block of data or code
Instructs the assembler to begin a new code or data section
Syntax
AREA sectionname {, attr}{,attr}.
Where
Section name is the name that the section is to be given.
enclose in bars names starting with a digit e.g |1_DataArea|
conventional names e.g |.text|
Valid attributes include
ALIGN = expr : align section to a 2expr byte boundary
CODE : section for machine instructions, READONLY
DATA: section for data, not instructions, READWRITE
READONLY: section not to be written to
READWRITE: section can be read from and written to

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 Frequently used directives
RN Register Name Definition
Defines a register name for a specified register
Syntax
name RN expr
Where
name is the name to be assigned to the register.
the parameter expr evaluates to a number between 0 and
15
coeff1 RN 8;
EQU EQUATE A SYMBOL TO A NUMERIC CONSTANT
gives a symbolic name to a numeric constant, a register
relative value, or a program relative value
similar to #define in C

8
 Frequently used directives
Syntax
name EQU expr {, type}
Where
name: the symbolic name assign to the value
expr: a register-relative address, a program-
relative address, an absolute address, or
a 32-bit integer constant
type: optional and can be CODE16, CODE32,
DATA
SRAM_BASE EQU 0x04000000
fiq EQU 0x1C, CODE 32; assign
;0x1C to the symbol fiq and
;marks it as code
xyz EQU label + 8
9
 Frequently used directives
ENTRY DECLARE AN ENTRY POINT
declares an entry point to a program
Syntax
ENTRY
example :
AREA ARMex, CODE, READONLY
ENTRY
DCB, DCW, and DCD ALLOCATE MEMORY AND
SPECIFY CONTENTS
DCB - allocates one or more bytes of memory, and defines the initial
runtime contents of the memory
Syntax
{label} DCB expr{, expr}.
where expr is either a numeric expression that evaluates to an integer
in a range -128 to 255 or a quoted string
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 Frequently used directives
Example:
C_string DCB C_string, 0; construct null-terminated
C_string 42 C ; assembly string
5F _
73 s
74 t
72 r
69 i
6E n
67 g
00 NULL

DCW allocates one or more halfwords of memory, aligned on two-byte

boundaries and defines the initial runtime contents of the memory
- Syntax
{label} DCW{U} expr{,expr} .
where expr is a numeric expression that evaluates to an
integer in the range of -32768 to 65635

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 Frequently used directives
DCD allocates one or more words of memory, aligned on 4-byte
boundaries and defines the initial runtime contents of the memory
- Syntax
{label} DCD {U} expr{,expr} .
where expr is a numeric expression or a program-relative expression.
{U} when alignment is not required

coeff DCW 0xFE37, 0x 8ECC ; defines 2 half words

data1 DCD 1,5,20 ; defines three words
;containing decimal 1,5,20
data2 DCD mem06 + 4 ; defines 1 word containing 4
;+ the address of the label mem06
AREA Mydata, DATA, READWRITE
DCB 255 ; Now misaligned
data3 DCDU 1,5,20 ; Not word aligned

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 Frequently used directives
ALIGN Align Data or Code to appropriate boundaries
aligns the current location to a specified boundary by
padding with zeros
Syntax
ALIGN {expr{, offset}}
where expr is a numeric expression evaluating to any power
of two from 2o to 231 , and offset is any numeric expression
The current location is aligned to the next lowest address of
the form
offset + n*expr

ALIGN 4 can be used before a label, which is defined on a

line by itself, to align it to the ARM code.

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 Frequently used directives
AREA OffsetExample, CODE
DCB 1 ; placing two bytes
ALIGN 4, 3 ; in the first and fourth
DCB 1 ; bytes of the same word

AREA Example, CODE, READONLY

start ADR r6, label1
MOV pc, lr
label1 DCB 1 ; pc now misaligned
ALIGN ;ensures that
;subroutine1 addresses
;the following instruction
subroutine1
MOV r5, #0x5
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 Frequently used directives
SPACE Reserve a Block of memory
The SPACE directive reserves a zeroed block of memory.
Syntax
{label} SPACE expr
where expr evaluates to the number of zeroes bytes to
reserve.
ALIGN directive should be used to align any code following
a SPACE directive
AREA MyData, DATA, READWRITE
data1 SPACE 255 ; Defines 255 bytes of zeroed storage

END END OF A SOURCE FILE

the end of the source file has been reached.
Syntax is
END
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 Data Processing Instructions
Largest category of ARM instructions, all sharing the same
instruction format.
Contains:
Arithmetic operations: add, sub, rsb, mul
Comparisons (no results saved - just set condition code
flags NZCV): cmp,cmn, tst, teq
Logical operations: and, orr, bic, eor
Data movement between registers: mov,mvn

They each perform a specific operation on operands.

4 field Format: 1 2, 3, 4 where:
1) operation by name
2) operand getting result (destination)
3) 1st operand for operation (source1)
4) second operand: register or shifted register or
immediate (numerical constant)

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 Data Processing Instructions
Operand 1 Operand 2 Register, optionally with shift operation
applied.
Shift value can be either be:
5 bit unsigned integer
add a1, v1, v3, lsl #8 ;a1 v1 +(v3
Barrel << 8 bits)
Shifter Specified in bottom byte of another
register.
add a1, v1, v3, lsl v4 ;a1 v1 +(v3
<< v4 bits)
ALU Immediate value.
8 bit number
Can be rotated right through an even
number of positions.
Result Assembler will calculate rotate for you
from a constant.
add a1, v1, #10 ;a1 v1 + 10
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 Addition/Subtraction
Addition in Assembly
Example: add v1,v2,v3 (in ARM)
Equivalent to: a = b + c (in C)
where registers v1,v2,v3 are associated with variables a, b, c
Example: add v1,v2,v3, lsl #1 (in ARM)
Equivalent to: a = b + 2 * c (in C)
where registers v1,v2,v3 are associated with variables a, b, c

Subtraction in Assembly
Example: sub v4,v5,v6 (in ARM)
Equivalent to: d = e - f (in C)
where registers v4,v5,v6 are associated with variables d, e, f

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 Addition/Subtraction
How do we do this?
f = (g + h) - (i + j);
Use intermediate register
add v1,v2,v3 ;f=g+h
add a1,v4,v5 ; a1 = i + j
; need to save i+j, but cant use f, so use a1
sub v1,v1,a1 ; f=(g+h)-(i+j)
How do the following C statement?
a = b + c + d - e;
Break into multiple instructions
add v1, v2, v3 ; a = b + c
add v1, v1, v4 ; a = a + d
sub v1, v1, v5 ; a = a - e
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 Addition/Subtraction with immediates
Immediates are numerical constants. They appear often
in code, so there are special instructions for them.
Add Immediate:
add v1,v2,#10 (in ARM)
f = g + 10 (in C)
where registers v1,v2 are associated with variables f, g
Immediates should be preceded by (#) symbol
Similarly,
add v1,v2,#-10 OR sub v1, v2, #10
f = g - 10 (in C)
where registers v1,v2 are associated with variables f, g

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 Addition/Subtraction with immediates
Immediates are numerical constants. They appear often
in code, so there are special instructions for them.
Add Immediate:
add v1,v2,#10 (in ARM)
f = g + 10 (in C)
where registers v1,v2 are associated with variables f, g
Immediates should be preceded by (#) symbol
Similarly,
add v1,v2,#-10 OR sub v1, v2, #10
f = g - 10 (in C)
where registers v1,v2 are associated with variables f, g

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 Addition/Subtraction with carry
ARM instruction set also include operations that
perform addition and subtraction with carry

Carry flag is used to indicate if an operation produced a

carry but in most significant bit of the result

adc, subc, and rsc make use of this flag by adding the
carry into the operation

adc v1,v2, v3; v1 = v2 + v3 + C

subc v1,v2,v3; v1 = v2 v3 + C - 1
rsc v1, v2, v3 ; v1 = v3 v2 + C - 1

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 Addition/Subtraction with carry
Useful for 64-bit arithmetic operations
Suppose we have a 64-bit integer contained in r2 and r3
and another 64-bit integer contained in r0 and r1. The two
integers can be added with the result being placed in r4
and r5 as follows
adds r4, r0, r2; adding least significant words
adc r5, r1, r3; adding most significant words with carry

Note: the use of suffix s for updating the flag bits in CPSR
r1 r0 Addend1
r3 r2 Addend2
+
r5 r4 Sum

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 Addition/Subtraction with carry
Similarly, 64-bit integer subtraction operation can be
built
subs r4, r0, r2; subtract lower halves, set Carry flag
sbc r5, r1, r3; subtract upper halves and Carry

Note: the use of suffix s for updating the flag bits in CPSR

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 Data movement instructions
Addition with zero is conveniently used to move content of one
register to another register, so:
add v1,v2,#0 (in ARM)
f = g (in C)
where registers v1,v2 are associated with variables f, g
This is so often used in code that ARM has an specific
instruction for it:
mov v1, v2
Another useful instruction often used to provide delay in a
loop is
mov a1, a1 ;this also called nop (No Operation)
This does nothing useful

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 Reverse subtraction
Normal Subtraction:
Example: sub v4,v5,v6 (in ARM); v4 v5 v6
Equivalent to: d = e - f (in C)
where registers v4,v5,v6 are associated with variables d, e, f

Reverse Subtraction:
Example: rsb v4,v5,v6 (in ARM) ; v4 v6 v5
Equivalent to: d = - (e) + f (in C)
where registers v4,v5,v6 are associated with variables d, e, f

rsb is useful in many situations

Example: d = 4e f (in C)
rsb v4,v6,v5, lsl #2 (in ARM)
where registers v4,v5,v6 are associated with variables d,e,f

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 Logic instructions
Operator Names:
and, bic, orr, eor,mvn:
Operands:
Destination : Register
Operand #1: Register
Operand #2: Register, or Shifted registers, or an
immediate
Example: and a1, v1, v2
and a1, v1, v2, lsl #5
and a1, v1, v2, lsl v3
and a1, v1, #0x40
ARM Logical Operators are all bitwise, meaning that
bit 0 of the output is produced by the respective bit 0s
of the inputs, bit 1 by the bit 1s, etc.

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 Logic instruction: AND
AND: anding a bit with 0 produces a 0 at the output while
anding a bit with 1 produces the original bit.
This can be used to create a mask.
Example:
1011 0110 1010 0100 0011 1101 1001 1010
Mask: 0000 0000 0000 0000 0000 0000 1111 1111
The result of anding these two is:
0000 0000 0000 0000 0000 0000 1001 1010
Thus, the and operator can be used to set certain portions
of a bitstring to 0s, while leaving the rest alone.
In particular, if the first bitstring in the above example
were in a1, then the following instruction would mask
the rightmost 8 bits and clears leftmost 24 bits :
and a1,a1,#0xFF
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 Logic instruction: AND
AND: bit-by-bit operation leaves a 1 in the result only if both
bits of the operands are 1. For example, if registers v1 and v2 are
0000 0000 0000 0000 0000 1101 0000 0000two
0000 0000 0000 0000 0011 1100 0000 0000two
After executing ARM instruction
and a1,v1, v2 ; a1 v1 & v2
Value of register a1
0000 0000 0000 0000 0000 1100 0000 0000two

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 Logic instruction: BIC (AND NOT)
BIC (AND NOT):Note that bicing a bit with 1 produces a
0 at the output while bicing a bit with 0 produces the
original bit.
This can be used to create a mask.
Example:
1011 0110 1010 0100 0011 1101 1001 1010
Mask: 0000 0000 0000 0000 0000 0000 1111 1111
The result of bicing these two is:
1011 0110 1010 0100 0011 1101 0000 0000
The second bitstring in the example is called a mask. It is used
to isolate the leftmost 24 bits of the first bitstring by masking
out the rest of the string (e.g. setting it to all 0s).

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 Logic instruction: BIC (AND NOT)
Thus, the bic operator can be used to set certain portions of
a bitstring to 0s, while leaving the rest alone.

In particular, if the first bitstring in the above example

were in a1, then the following instruction would mask the
leftmost 24 bits and clears rightmost 8 bits:
bic a1,a1,#0xFF

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 Logic instruction: BIC (AND NOT)
BIC: bit-by-bit operation leaves a 1 in the result only if bit of
the first operand is 1 and the second operands 0. For example
if register v1 and v2 are
0000 0000 0010 1100 0000 1101 0000 0000two -- v1
0000 0000 0000 1000 0011 1100 0000 0000two --- V2
After executing ARM instruction
bic a1,v1, v2 ; a1 v1 & (not v2)
Value of register a1
0000 0000 0010 0100 0000 0001 0000 0000two

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 Logic instruction: OR
OR: oring a bit with 1 produces a 1 at the output while
oring a bit with 0 produces the original bit.
This can be used to force certain bits of a string to 1s.
For example, if a1 contains 0x12345678, then after
this instruction:
orr a1, a1, #0xFF
a1 contains 0x123456FF (e.g. the high-order 24
bits are untouched, while the low-order 8 bits are
forced to 1s).

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 Logic instruction: OR
OR: bit-by-bit operation leaves a 1 in the result if either
bit of the operands is 1. For example, if registers v1 and
v2
0000 0000 0000 0000 0000 1101 0000 0000two
0000 0000 0000 0000 0011 1100 0000 0000two
After executing ARM instruction
ORR a1,v1,v2 ; a1 v1 | v2
Value of register a1
0000 0000 0000 0000 0011 1101 0000 0000two

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 Logic instruction: XOR
EOR: Eoring a bit with 1 produces its complement at
the output while Eoring a bit with 0 produces the
original bit.

This can be used to force certain bits of a string to

invert.
For example, if a1 contains 0x12345678, then after
this instruction:
eor a1, a1, #0xFF
a1 contains 0x12345687 (e.g. the high-order 24
bits are untouched, while the low-order 8 bits are
forced to invert).

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 Logic instruction: XOR
EOR: bit-by-bit operation leaves a 1 in the result if if bits of the
operands are different. For example, if registers v1 and v2

0000 0000 0000 0000 0000 1101 0000 0000two

0000 0000 0000 0000 0011 1100 0000 0000two
After executing ARM instruction
eor a1,v1,v2 ; a1 v1 ^ v2
Value of register a1
0000 0000 0000 0000 0011 0001 0000 0000two

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 Logic instruction: MVN
MVN (Move Negative): produces the complement of an
operand at the output. It takes a destination register
and an operand, which can be a register, an immediate,
shifted or rotated register.

For example, if a1 contains 0x12345678, then after

this instruction:
mvn a2, a1
a2 contains 0xEDCBA978

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 Shift Operations
Move (shift) all the bits in a word to the left or right by a
number of bits, filling the emptied bits with 0s.
Example: shift right by 8 bits
1001 0010 0011 0100 0101 0110 0111 1000

0000 0000 1001 0010 0011 0100 0101 0110

Example: shift left by 8 bits
1001 0010 0011 0100 0101 0110 0111 1000

0011 0100 0101 0110 0111 1000 0000 0000

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 Shift Operations
Move (shift) all the bits in a word to the right by
a number of bits, filling the emptied bits with the
sign bits.
Example: Arithmetic shift right by 8 bits
1001 0010 0011 0100 0101 0110 0111 1000

1111 1111 1001 0010 0011 0100 0101 0110

0001 0010 0011 0100 0101 0110 0111 1000

0000 0000 0001 0010 0011 0100 0101 0110

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 Rotate Operations
Move (shift) all the bits in a word to the right by a
number of bits, filling the emptied bits with the
bits falling of the right.

Example: rotate right by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

0111 1000 1001 0010 0011 0100 0101 0110

40
 ARM Shift Instructions
ARM does not have separate shift instruction.
Shifting operations is embedded in almost all other data
processing instructions.
Pure Shift operation can be obtained via the shifted version of
mov Instruction.
Data Processing Instruction with Shift Feature Syntax:
1 2,3,4,5 6 Example:
Where
add a1, v1,v3, lsl #8
1) operation ;a1 v1 +(v3 << 8 bits)
2) register that will receive value
3) first operand (register) add a1, v1,v3, lsl v4
4) second operand (register) ;a1 v1 +(v3 << v4 bits)
5) shift operation on the second operand
6) shift value (immediate/register)

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 ARM Shift Instructions
1. lsl (logical shift left): shifts left and fills emptied bits with 0s
N Z C V

Destination 0

mov a1, v1, lsl #8 ;a1 v1 << 8 bits

mov a1, v1, lsl v2 ;a1 v1 << v2 bits
shift amount between 0 to 31
2. lsr (logical shift right): shifts right and fills emptied bits with
0s
N Z C V

0 Destination
mov a1, v1, lsr #8 ;a1 v1 >> 8 bits
mov a1, v1, lsr v2 ;a1 v1 >> v2 bits
shift amount between 0 to 31
42
 ARM Shift Instructions
3. asr (arithmetic shift right): shifts right and fills emptied bits
by sign extending
N Z C V

Destination
Sign bit shifted in

mov a1, v1, asr #8 ;a1 v1 >> 8 bits ;a1[31:24]=v1[31]

mov a1, v1, asr v2 ;a1 v1 >> v2 bits ;a1[31:24]=v1[31]

shift amount between 0 to 31

43
 ARM Shift Instructions
4. ror (rotate right): shifts right and fills emptied bits by bits
falling of the right. (bits wrap around)
N Z C V

Destination

mov a1, v1, ror #8 ;a1 v1 >> 8 bits

;a1[31:24] v1[7:0]
mov a1, v1, ror v2 ;a1 v1 >> v2 bits
;a1[31:(31-v2)] v1[v2:0]
Rotate amount between 1 to 31

44
 ARM Shift Instructions
4. rrx (rotate right through carry): This operation uses the
CPSR C flag as a 33rd bit for rotation. (wrap around
through carry)
Rotate Right through Carry

Destination
N Z C V

mov a1, v1, rrx ;a1 v1 >> 1 bit

;a1[31] CF
;CF v[0]
Only Rotation by one bit is allowed
Encoded as ror #0.

45
 Isolation with shift
Suppose we want to isolate byte 0 (rightmost 8
bits) of a word in a0. Simply use:
and a0,a0,#0xFF
Suppose we want to isolate byte 1 (bit 15 to bit 8)
of a word in a0. We can use:
and a0,a0,#0xFF00
but then we still need to shift to the right by 8
bits...
mov a0,a0,lsr #8

46
 Isolation with shift
Instead, we can also use:
mov a0,a0,lsl #16
mov a0,a0,lsr #24

0001 0010 0011 0100 0101 0110 0111 1000

0101 0110 0111 1000 0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0101 0110

47
 Extracting a field of bits
Extract bit field from bit 9 (left bit no.) to bit 2 (size=8
bits) of register v1, place in rightmost part of register a1

31 9876543210
v1

000000000000000000000000 a1

Shift field as far left as possible (9 31) and then as far

right as possible (317)

v1

0000000000000000000000 a1

000000000000000000000000 a1

48
 Extracting a field of bits
mov a1, v1, lsl #22 ;8 bits to left end (31-9)
v1

0000000000000000000000 a1

mov a1, a1, lsr #24 ;8 bits to right end(7-0)

0000000000000000000000 a1

000000000000000000000000 a1

49
 Inserting a field of bits
Insert bit field into bit 9 (left bit no.) to bit 2 (size=8 bits) of
register a1 from rightmost part of register v1 (rest is 0)
31 9876543210
000000000000000000000000 v1

a1

Shift left field 2 bits, Mask out field, OR in field

0000000000000000000000 00 a2=v1<<2

00000000 a1 masked
a1 ored a2
mov a2, v1, lsl #2 ; field left 2
bic a1, a1, #0x3FC ; mask out 9-2
; 0x03FC = 0011 1111 1100
orr a1, a1, a2 ; OR in field
; bic stands for bit clear, where 1 in the second operand clears
; the corresponding bit in the first
50
 Multiplication Instruction
The Basic ARM provides two multiplication instructions.
Multiply
mul Rd, Rm, Rs ; Rd = Rm * Rs
Multiply Accumulate - does addition for free
mla Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn

(Lower precision multiply instructions simply throws top

32bits away)

Restrictions on use:
Rd and Rm cannot be the same register
Can be avoided by swapping Rm and Rs around. This
works because multiplication is commutative.
Cannot use PC.
These will be picked up by the assembler if overlooked.

Operands can be considered signed or unsigned

Up to user to interpret correctly.
51
 Multiplication Instruction
Example:
in C: a = b * c;
in ARM:
let b be v1; let c be v2; and let a be v3 (It may be
up to 64 bits)
mul v3, v2, v1 ;a = b*c; lower half of product into
; v3 Upper half is thrown away
Note: Often, we only care about the lower half of
the product.

52
 Multiplication Instruction
One example of use of mla is for string to number
conversion: eg
Convert string=123 to value=123
value = 0
loop = 0
len = length of string
Rd = value
while loop <> len
c = extract(string, len - loop,1)
Rm = 10 ^ loop
Rs = ASC(c) - ASC (0)
mla Rd, Rm, Rs, Rd
loop = loop + 1
53 endwhile
 Multiplication Instruction
Instructions are

MULL which gives RdHi,RdLo:=Rm*Rs

MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo

However the full 64 bit of the result now matter (lower precision multiply
instructions simply throws top 32 bits away)

Need to specify whether operands are signed or unsigned

Therefore syntax of new instructions are:

umull RdLo,RdHi,Rm,Rs ;RdHi,RdLo:=Rm*Rs

umlal RdLo,RdHi,Rm,Rs ;RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
smull RdLo, RdHi, Rm, Rs ;RdHi,RdLo:=Rm*Rs (Signed)
smlal RdLo, RdHi, Rm, Rs ;RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
(Signed)
N

a i bi
i0
54
 Multiplication by a constant
Since shifting is so much faster Operand 1 Operand 2
than multiplication (you can
imagine how complicated
multiplication is), a good Barrel
compiler usually notices when Shifter
C code multiplies by a power of
2 and compiles it to a shift
instruction: ALU
a *= 8; (in C)
would compile to:
mov a0,a0,lsl #3 (in ARM) Result

55
 Multiplication Instruction
Add and Subtract Examples:
f = 5*g /* f = (4+1) x g */ (in C)
add v1,v2,v2 lsl #2 ; v1 = v2 + v2 *4 (in ARM)

f = 105*g /* f = (15 x 7) x g */ (in C)

/* f = (16 1 ) x (8 1) x g */
rsb v1,v2,v2 lsl #4 ; v1 = -v2 + v2 *16 (in ARM)
; f = (16-1)* g
rsb v1,v1,v1 lsl #3 ; v1 = -v1 + v1 *8 (in ARM)
; f = (8-1)* f

56
 Division
ARM does not have division.
Division is done using software routine.
A divider circuit takes up too much area and
power
In C , the compiler will take care if the division
algorithm for you

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