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INTRODUCTION:
In this lab exercise, we will design a simple two-stage CMOS opamp and a wide-range current-mirror OTA.
We have known how to use Design Architect and AccuSimII to design and verify the transistor level circuits. In this lab, we will go further to do layout design for the
wide-range OTA using full-custom procedure in IC station. You may refer to the on-line IC Station User's Manual for more details about IC layout design. This lab
will cover:
2. In DA, create schematic sheets for a simple two-stage opamp and a wide-swing current-mirror opamp.
a. Set the working directory to your $CLASS/parts.
b. Open new sheets $CLASS/parts/ts_opamp and $CLASS/parts/wr_opamp which correspond to the two-stage opamp and the wide-range opamp,
respectively. Use the techniques in Lab 1 to create these two opamps shown in Figure 1 and Figure 2.
c. In Figure 1, transistors Q1 ~ Q5 construct a differential pair as the input stage, while Q6 and Q7 construct a common-source amplifier as the output stage.
Frequency compensation of the opamp is accomplished by means of the capacitor shown in Figure 1. In a real design, a "nulling" resistor, which is usually
created by a transistor, in series with the capacitor has to be added to make the opamp more stable in a feed-back configuration.
d. In Figure 2, three current mirrors are constructed by Q3 and Q5 (1:2), Q4 and Q6 (1:1), and Q7 and Q8 (1:2), respectively. This kind of current-mirror
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opamp has higher unity-gain frequency and wider output voltage range than a simple two-stage opamp.
c. From the above figures, we see that ts_opamp has unity-gain frequency bandwidth 23.3M Hz while wr_opamp has nearly 800M Hz. The latter has -3dB
frequency of 27M Hz. The former has more than 60dB gain in 22.6K Hz bandwidth.
d. Remember to save the setup data for later use.
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d. Once the empty cell has been opened, you should go to the Easy Edit menu on the palette menu. You may open a schematic window by selecting the
pull-down menu File>Logic>Open to specify the logic source. Use the navigator to select the $CLASS/parts/wr_opamp/sdl viewpoint. Your schematic
should appear in a window. You may rearrange the two windows so that they don't overlap.
e. The first thing you should probably do is to add the mos transistors. Because we are using very large transistors, we need to fold the large transistor into
small ones. You may notice that the width of the transistors in Figure 2 is multiple of 10 micron, for instance, Qb's width is 30 times of 10 micron. Let us
first use a device generator to generate a folded Qb. Select the pop-up menu Add>Device: and specify the device name as mos. In the dialog box, define
width as 25 lambda (10 micron) and length with 4 lambda, select nmos4 as the transistor type and both for Source/Drain Contacts, and give 30 1's in
the blank boxes after the Gate Combinations item. Then you will see a long row of transistors in the cell window as shown at the bottom-right corner in
Figure 5.
f. You may copy Qb for Q1 and Q2 due to the same size. In Figure 5, the Q1 and Q2 overlap each other at the edge and are placed in the middle of the figure.
You may conbine Q7 and Q8 into one device which has 18 gates. In Figure 5, this device is overlapped by Qb at the edge (the bottom row of transistors).
Then generate Q3 and Q5, Q4 and Q6 using pmos4 type (the top row shown in Figure 5). The total number of pmos transistors is 30.
g. After the placement is finished, we only need to wire up the devices using poly, metal1, metal2, via and contact_to_poly. You may use the [Add] Path
item on the palette. For example, we are going to wire up the VB signal by adding paths to connect all of the 30 gates of Qb. Select the poly layer and click
[Add] Path item. On the prompt bar, click on the Option button to change the path width to 4L. Then, add wires to connect the gates. You will see the path
centered with a line. Note poly spacing = 3L in this 0.8 micron process. For Qb, the sources of gates are wired up together while the drains are wired up
together. You may use the same pattern for wiring up transistors Q3 ~ Q8 (in Figure 5, can you tell which are Q3, Q5, and Q7?). The differential pair Q1
and Q2 are wired up in different way. In Figure 5, can you tell the drain and the source of Q1 and Q2?
h. Once you finished to wire up the gates, you need to place some tub-ties or sub-ties using the previousely generated nwell_contact and pwell_contact. Use
the techniques you knew to add ports for the input and output signals and power rails.
i. Now it is time to see if your circuit passes the DRC. Go back to the Session palette and then select ICrules. Do a check of your circuit and then use the
scanning menu items to locate the errors, if any. You should fix all DRC errors before moving on to the next section.
j. Once all DRC errors are fixed, save your cell.
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