Efficient Identification of

Multi-Cycle False Path

Kai Yang, Kwang-Ting Cheng

Department of Electrical and Computer Engineering

University of California, Santa Barbara
 Abstract
o Address the timing analysis problem by considering both
single-cycle and multi-cycle operations

o Provide the precise definition of multi-cycle false paths

and the necessary conditions for multi-cycle sensitizable
paths

o Propose a segment-based algorithm to identify multi-cycle

false paths

o Propose an iterative method to compute valid clock period

o Demonstrate the improvement in clock frequency by

taking multi-cycle false paths into account
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Motivation
o Clock period is determined by the delay of the longest
path in the circuit

o Utilizing only topological delay to determine the clock

period could be too conservative
False path
Multi-cycle path

o A multiple-cycle path in a sequential circuit is a

combinational path which does not have to complete the
propagation of the signals along the path within one clock
cycle
 Motivation (cont.)
o 3-cycle multi-cycle operation

MUX-2
MUX-1
FF1
FF0 0
0 Combinational DFF
DFF 1
IN 1 Circuit

launch FF2 FF3 FF4 FF5

DFF DFF DFF DFF

I nitial State 1 0 0 0
0 1 0 0 capture
0 0 1 0
0 0 0 1
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Previous Work
o Define: multi-cycle flip-flop pair

FFi (t ) FFi (t 1) FF j (t 1) FF j (t 2)
o All paths between multi-cycle flip-flop pairs are
then declared as multi-cycle paths

DFF DFF
o Stable state checking
BDD [K. Nakamura, ICCAD-1997]
SAT [K. Nakamura, IEICE-2000]
ATPG [H. Higuchi, DAC-2002]
Multi-Cycle Flip-Flop Pair Example

M ulti-Cycle Flip-Flop P air

MUX-2
MUX-1
FF1
FF0 0
0 Combinational DFF
DFF 1
IN 1 Circuit

FF2 FF3 FF4 FF5

DFF DFF DFF DFF

I nitial State 1 0 0 0
 Invalid Clock Calculation
o Stable state checking might not result in correct classification of multi-
cycle flip-flop pairs due the presence of static-hazard [H. Higuchi 2002]

FF1
FF0 0
0 Combinational DFF
DFF Circuit 1
IN 1

DFF DFF DFF DFF

I nitial State FF21 0 0 0

FF3
DFF DFF
State { 0,0} { 0,1}
{ 1,1} { 1,0}
I nitial State 0 0
 Static-Hazards Problem

FF1

DFF
Combinational
Circuit

FF3

DFF
0 0
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Multi-Cycle Path
o Definition: A k-cycle path Px could complete the
propagation of the signal transition from the source to the
destination in k cycles
o Clock period could be shorter than the delay of Px

Target Circuit

Px

clk
Model for Illustration and Analysis

Target Circuit Tim efram e Ex panded M odel

TF-1 TF-2
Px
seg-1
seg-2
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Necessary Conditions for Single-Cycle
Sensitizable Path
o Functional sensitization criterion [Cheng]
A path is sensitizable if there exists an input vector
such that all the side-inputs along the path are non-
controlling values when the corresponding on-input
propagates a non-controlling value

1 (ncv) on-input
1 (ncv)

Path
1 (ncv) side-input
Necessary Conditions for Multi-Cycle
Sensitizable Path
o Each segment of a multi-cycle sensitizable path must
satisfy the functional sensitization criterion in its
corresponding timeframe. Otherwise, it is false.

Timeframe Expanded Model

TF-1 TF-2
seg-2
seg-1
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
Identification of Multi-Cycle False Paths

o Segment-based checking algorithm to identify multi-cycle

false paths
o Check the necessary condition under the timeframe
expanded model

o Input
A path Px
The multiplicity k
The clock period clk
o Output
The sensitizability of path Px
Segment-Based Checking Algorithm
o Check the sensitizability of each segment of the multi-
cycle path at each timeframe

Target Circuit

Px a=1 d=1

b=1 c=1
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Valid Clock Period
o Traditionally, the valid clock period is determined by
the delay of the longest single-cycle sensitizable path

o With multi-cycle operation, the clock period is

determined by the delay of the longest k-cycle
sensitizable path divided by k

clk (max(d ( P )) / m, P m cycle true path,1 m k

 Calculating a Valid Clock Period
0
0 DFF
DFF 1
1

0 0
DFF DFF
1 1

ISCAS85 Circuit

FF0 FF1 FF2

DFF DFF DFF
I nitial State 1 0 0
 Iterative Method for Calculating Valid
Clock Period
MAX = 0
k=1

Identify the longest k-cycle sensitizable path Px

Delay of Px = d(Px)
(Based on BFS + Segment-based Checking)

Update MAX delay Done

k=k+1 Clock = MAX
If MAX < d(Px)/k, then MAX = d(Px)/k

Yes No
Exists path P, which d(P)/k+1 > MAX ?
 Outline
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Experimental Result
Reported Clock Period for exemplar circuit
 Outline
o Abstract
o Motivation
o Previous Work
o Multi-Cycle Path
o Necessary Conditions for Path Sensitization
o Identification of Multi-Cycle False Paths
o Valid Clock Period
o Experimental Result
o Conclusion
 Conclusion
o Define the multi-cycle false path and the multi-
cycle sensitizable path

o Provide necessary conditions for multi-cycle

sensitizable paths

o Algorithm to compute the valid clock period

o Demonstrate the improvement the clock

frequency by considering multi-cycle false paths