Demonstration of A Modern Physical Design Flow Using the

Silicon Virtual Prototyping Back-End Tools of Cadence

Anuj Kumar, Azadeh Davoodi, University of Wisconsin - Madison

Flat Physical Flow Silicon Virtual Prototype Hierarchical Physical Flow

Data Provides quick feedback on performance, area Divide and Conquer Approach to
Preparation Power Routing View and power early in design cycle. manage Complexity. Partitioned View
Floorplanning SVP Components Steps
Fast floorplan mode for placement Partition and Floorplan
Power Routing buffer
insertion, Define logical partitions, fix their
gate Accurate pre-routing timing analysis locations, shape and size.
Placement & sizing,
pin swap
Interconnect consideration via incorporation Initial place/route
Scan Chain Reorder
of a fast router. Guides the pin assignment for the
TrialRoute: Used for quick evaluation of partitions.
Pre-CTS Timing Analysis routability, congestion, timing analysis and
& Optimizations
Assign partition pins
optimizations. Actual pin assignment on the Logical Partitions (translated into Hard Blocks)

Native extraction partition boundaries used to guide

Hard
N
Power Stripes the routing inside the partitions.
Met
Timing ?
IP Block Layer M6 Core Ring Can make use of scale factors to improve
Derive timing budgets
Assembled View
the RC estimation for the routes generated
using Ostrich (SPEF Comparator). Generate local timing constraints
Y Scan Chain View for the paths that cross the partition
Clock Tree fix DRV, Timing optimizations boundaries.
Synthesis setup/hold
violation, At Pre- and Post- routing stages. Commit partition, top-level
correct Effective incremental mode. place/route
timing with
Post-CTS Low effort mode to meet timing constraint, Treat partition as hard IP block.
propagated
Timing Analysis clock, achieves within 10% of the target timing. Implement each partition
& Optimizations reduce area

Assemble Design
N Met
Engineering Change Order Merge together the individual blocks Signal Routes Merged with Top after
Timing ? and top. Assemble Design
Old Design
(in Memory) Local changes to
Y repair timing current logical netlist Educational Goals
Routing with no new to make functional
problem Placed Instances Scan Chain After
Identify Local modifications or Provide the students big picture on the sequence of and interaction
(Standard Cell) Reordering
introduction,
fix signal
Modifications meeting design among different stages of a modern physical design flow, which they learn
constraints
Post Route integrity only as disjoint steps in the class.
Optimizations issues Congestion View Make Logical May be manual Enhance the students understanding of challenges to achieve design
Analyze Design Changes (to Netlist) through loading an
ECO file.
closure and inevitability of backtracking within the design flow.
(Timing, DRV,
Power, Area)
May be done by tool
commands
Provide deeper understanding of inherent complexity of the design
Commit Physical (optDesign) during process by using commercial tools on moderately sized designs, thus
Changes optimizations students will better appreciate the effectiveness of the CAD algorithms
Incremental
N Constraints Placement & Routing Do not modify taught in the class.
Met ? currently
Placed/Routed References
Y objects. Use
Save Design ecoPlace/ecoRoute [1] W-J Dai, D. Huang, C-C Chang, M. Courtoy, Silicon virtual prototyping: the new cockpit for nanometer
Verify Design & High Congestion on to do incremental chip design, Proceedings of the Asia South Pacific Design Automation Conference, pp. 635 639, 2003.
Save Design the Routing Grid placement & routing
[2] Cadence Learning Management, http://leaning.cadence.com
(Vertical Edge View)