FPGA Research in Nepal

Internship Plan on FPGA R & D

1. Level First
VHDL/Verilog/Tcl Review
Basic Simulation and implementation

Objective (Knowledge Gain)

Knowledge of HDL Design Flow and basic
programming on HDL
Study of ISE design Suit and its Basic features

2. Level Second Figure: Spartan 6 FPGA, Xilinx

VHDL/Verilog/Tcl Reference guide preparation
HDL/Tcl programming with Sequential circuit design as ALU, RISC processor and
understanding I/O, file inclusion in HDL/Tcl

Objective (Knowledge Gain)

Knowledge of HDL Multiple features of HDL
Working with ISE design suit features including Resource utilization analysis, basic
optimization methods and other analysis works
Structural Design flow implementation

3. Level Third
VIVADO Design Flow implementation (Design , Simulation, synthesizing, implementing ,
programming and debugging features)
IP design and customization flow in Vivado

Objective (Knowledge Gain)

Understanding the VIVADO design methodology
IP design paradigm and procedures understanding
Idea of Bus protocols as AXI, PCIe etc.

4. Level Fouth
Implementing Algorithms in FPGA(Zynq 7000, Zybo)
with HDL/Tcl
Figure: Zybo FPGA, Xilinx

Internship Plan on FPGA Research and Development in Nepal

For any Queries please contact at: digitronixnepali@gmail.com or +977-9841078525
 PS and PL integrating and programming with VIVADO and SDK
C and C++ Programming for ARM Cortex A9 (PS ARM Host)
Creating First Stage Bootloder (FSB) and Building Linux Kernels for Zybo.

Objective (Knowledge Gain)

Preparing Customized RTOS targeted for Zybo
Understating PS and PL function , features and programming framework
Designing Custom IP with the algorithm as example Image processing, Neural Nets and
Machine Learning Algorithms.
Designing some unique IP and generating its HDL sources, Simulation testbenches, RTL
design, IO and timing constraints.

5. Level Fifth
Custom Hardware Design
Verification and Debugging of multiparty IPs
with ILA and different debugging methods
Timing and Design analysis and Optimization
Clock Domain Analysis, RTL analysis
Figure: Kintex Ultrascale FPGA, Xilinx
Objective (Knowledge Gain)
Skill enhancement with Core/IP Design , Verification and Optimizations
One single team can work with Complete Development module as Design (few
members) and Verification/debugging/optimization (remaining few members)

Internship Plan on FPGA Research and

Development in Nepal

Internship Plan on FPGA Research and Development in Nepal

For any Queries please contact at: digitronixnepali@gmail.com or +977-9841078525