Welcome

Hsieh-Hung Hsieh (PhD)

Technical Manager / RF
Design Program
TSMC

George Estep
RFIC Application
Development Engineer
Agilent EEsof

Copyright 2012 Agilent Technologies

April 5, 2012
Agenda

TSMC 60-GHz CMOS RDK

RDK Solution Approach
60-GHz CMOS Design Opportunities and Applications
60-GHz Reference Design

Comprehensive mm-Wave Simulation & Modeling Solutions

Top-down ESL architecture verification
RFIC circuit simulation & verification
EM analysis & verification
Consideration of off-chip components & parasitics

Summary and Q&A

2
 RDK Solution Approach TSMC Property

A silicon-proven RF reference circuits and methodology packaged into a

complete RF reference design kit (RDK):
Reference circuit design with correlated simulation and measurement data.
Methodology for simulation of substrate noise with substrate networks.
Provide RF basic cell (RBC) and RF building block (RBB) modules with
friendly navigator GUI support.
Enable complicated RF analyses including phase noise, substrate noise
analysis, and EM simulation.
Provide TSMC developed PDK superset devices and IP.
Design collaboration with key ecosystem partners.

2012 TSMC, Ltd

 RF RDK Introduction TSMC Property

EM Comprehensive Flow
Compliant to TSMC dummy rules
Seamless simulation flow
Auto behavior model generation

Substrate Noise Analysis Ecosystem Partners

Analyze substrate noise
coupling in RF circuits

RF Behavior Model Scalable VCO

Block Spec. Sizing, Cross Couple Logic Inductor
System KPI definition
System Yield RF Basic Cell
Optimization Differential
Cascoder
Pair
60GHz Wireless
Design
Core Feature (60G
Wireless design) Core Design
LNA, VCO and PA

2012 TSMC, Ltd

 60-GHz CMOS Design TSMC Property

Opportunities and Applications

ECMA TC48
MAC, PHY and
wireless
Wireless Uncompressed
HDMI HDTV Video

802.15.3c
Wireless PC interface
IEEE 802.11.ac/ad Mobile device
WirelessHD HDMI
802.11 serial
Target on wireless
Below 6G & 60G HDMI

2012 TSMC, Ltd

 Motivation of 60-GHz Design TSMC Property

60-GHz band:
High atmospheric attenuation
Higher throughput:
Never ending demand of high data rate
Support more and more users or applications
7 GHz of unlicensed spectrum (57-64 GHz)
Flexible use of spectrum resource
Communication in a wide range of frequency bands
Smaller on-chip passives Higher integration Single-chip transceivers
Technology scaling enables low-cost 60-GHz radio SoC in silicon.

Spectrum full within 5G Underused Spectrum 57G-64GHz

6

2012 TSMC, Ltd

 Applications of 60-GHz RFIC TSMC Property

Applications of 60-GHz RFIC:

Emerging technology, WiGig Alliance Newest Office

2012 TSMC, Ltd

 RDK 60G 65nm Design Package TSMC Property

60-GHz wireless design:

Setup millimeter wave very high throughput design flow
Achieve reliable measurement results
Enable RF top-down design methodology to perform system level
simulation with behavior model solution
Extra devices/ transmission line support

Provide RF frontend
Extra device support circuits (LNA, PA,
and VCO)

Provide reference Achieve reliable

design flow and simulation/measured
function validation results

2012 TSMC, Ltd

 TSMC 60-GHz RF Frontend Architecture TSMC Property

Based on a heterodyne architecture (two-step conversion).

Frequency planning: 60-GHz RF, 48GHz LO1, 12-GHz IF.

RDK circuit scope: LNA, PA, and VCO.

LNA IFA

LO1
LO2_I
VCO /4
LO2_Q

PA IFA

2012 TSMC, Ltd

 60-GHz Microstrip-Line-Based LNA TSMC Property

The proposed 60-GHz LNA is composed of three gain stages.

The transmission lines are realized in microstrip lines.

VDD1 VDD2 VDD3

Microstrip Line

M2 M4 M6

RFin M1 M3 M5 RFout

VB1 VB2 VB3

10

2012 TSMC, Ltd

 60-GHz Microstrip-Line-Based LNA TSMC Property

Operate at a supply voltage of 1.0 V.

30 30

20 20

10 10

S11 (dB)
S21 (dB)

0 0

-10 -10

-20 -20

-30 -30
40 45 50 55 60 65 70 75 80 40 45 50 55 60 65 70 75 80
Frequency (GHz) Frequency (GHz)

30 10

20
8
10
S22 (dB)

6
NF (dB)

4
-10

-20 2 Simulation
Measurement
-30
0
40 45 50 55 60 65 70 75 80
58 59 60 61 62 63 64 65
Frequency (GHz)
Frequency (GHz)
11

2012 TSMC, Ltd

 60-GHz Microstrip-Line-Based LNA TSMC Property

With 5T model, more accurate silicon correlation can be achieved.

30 30

20 20

Mag (S21) (dB)

10 10
S21 (dB)

0 0

-10 -10
Simulation
-20 -20
Measurement

-30 -30
40 45 50 55 60 65 70 75 80 40 45 50 55 60 65 70 75 80
Frequency (GHz) Frequency (GHz)

4T model 5T model

12

2012 TSMC, Ltd

 60-GHz Microstrip-Line-Based LNA TSMC Property

Impact of different metal scheme:

Difference of gain between 1P9M and 1P6M at 60 GHz is 3 dB.
Difference of NF between 1P9M and 1P6M at 60 GHz is 0.4 dB.
More metal stack is beneficial to circuit performance.

30

20
Mag (S21) (dB)

10

-10
1P6M
-20
1P9M

-30
40 45 50 55 60 65 70 75 80
Frequency (GHz)

13

2012 TSMC, Ltd

 60-GHz Slow-Wave-TL-Based LNA TSMC Property

Slow-wave-TL-based LNA:

With the use of slow-wave TL, the compact chip area can be obtained.

Due to the decrease of insertion loss, for a targeted gain, the required dc power
can be reduced while noise performance becomes better.

Similar Layout Style

(31% Reduction in Chip Area)

Take Advantage of GND Sidewall

(35% Reduction in Chip Area)

MS-LNA, Area = 1.5 x 1.3 mm2

SW-LNA1, Area = 1.5 x 0.9 mm2

SW-LNA2,
Area = 0.8 x 1.1 mm2
Total 55% Reduction in Chip Area
14

2012 TSMC, Ltd

 60-GHz ESD Reference Design TSMC Property

4kV ESD capability is achieved by using combination of short-circuited and open-

circuited stubs.
Difference of gain between LNA w/i and w/o ESD at 60 GHz is 0.2 dB.
Difference of NF between LNA w/i and w/o ESD at 60 GHz is 0.5 dB.

15

2012 TSMC, Ltd

 60-GHz Transformer-Based PA TSMC Property

Based on a three-stage differential transformer-coupled architecture.

To stabilize the circuit, the gate resistors are employed in three gain stages.

M1 M3 M4
Microstrip Line

VDD M2

RFin RFout

VDD

VDD
VDD

VG2

VG3
VG1

VDD M2

M1 M3 M4

16

2012 TSMC, Ltd

 60-GHz Transformer-Based PA TSMC Property

The frequency response of each stage is provided in the following figure.

With the increase of coupling capacitor Cc, the cross-coupled pair is formed in the
pseudo-differential common-source stage, leading to possible oscillation.

0 200
Cc = 0 fF
150 Cc = 20 fF
Normalized Gain (dB)

-3 Cc = 40 fF

Stability Factor
100 Cc = 60 fF
Cc = 80 fF
-6 50 Cc = 100 fF

Cc
0 Cc
-9 Input Matching + TF1 The 1st Gain Stage
-50 Ma1 Ma2
The 2nd Gain Stage The 3rd Gain Stage
-12 -100
50 55 60 65 70 75 80 10 20 30 40 50 60 70 80 90 100
Frequency (GHz) Frequency (GHz)

17

2012 TSMC, Ltd

 60-GHz Transformer-Based PA TSMC Property

Operate at a supply voltage of 1.0 V.

30 20

20

Output Power (dBm)

10
10
S21 (dB)

0 0

-10
-10
-20

-30 -20
40 45 50 55 60 65 70 75 80 -20 -15 -10 -5 0 5
Frequency (GHz) Input Power (dBm)

Meas
Sim

18

2012 TSMC, Ltd

 PVT EM Corner Simulation TSMC Property

The frequency shift is observed (~ 1 GHz) with the EM corner simulation.

The simulation results indicate that the wideband operation of 60-GHz circuit is
essential.

19

2012 TSMC, Ltd

 48-GHz Wideband VCO TSMC Property

The proposed 48-GHz VCO adopts a thermometer-weighted switched-capacitor array

for wideband operations.
VDD
VB_VCO

VTUNE

+VO -VO
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
M1 M2 B0 0 1V 1V 1V 1V 1V 1V 1V B0
B1 0 0 1V 1V 1V 1V 1V 1V B1
B2 0 0 0 1V 1V 1V 1V 1V B2
B3 0 0 0 0 1V 1V 1V 1V B3
B0
B4 0 0 0 0 0 1V 1V 1V B4
B5 0 0 0 0 0 0 1V 1V B5
B6 0 0 0 0 0 0 0 1V B6

B6

20

2012 TSMC, Ltd

 48-GHz Wideband VCO TSMC Property

Operate at a supply voltage of 1.0 V.

56 56

54 54
Osc. Frequency (GHz)

Osc. Frequency (GHz)

52 52

50 50

48 48

46 46

44 44
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
Controlled Voltage (V) Controlled Voltage (V)

Meas
Sim

21

2012 TSMC, Ltd

 Summary on 60-GHz Reference Design TSMC Property

Critical building blocks of 60-GHz RFIC: LNA, PA, and VCO.

Utilize new devices: transmission line for LNA.

Include circuit database, model, and complete design flow.

Circuit-level silicon validation with millimeter-wave models.

22

2012 TSMC, Ltd

 Agilent EEsof within the 60-GHz RDK
R1 R1 R1
M1 M3 M4

Focus of 60-GHz RDK summary: RFin

VDD
T1 M2

RFout

VDD

VDD
VDD

VG2

VG3
VG1
Combination of fundamental circuit blocks, design flows, VDD

R1
T1
M2

M1
R1
M3
R1
M4
CORE

LP1
VDD

Vctrl
Cvar Cvar
Ibias1

LP1
BUF

LP2

vout
VDD

LP2

documentation and models intended to introduce mm-wave design in

M3 M4

M1 M2

Ibias2

B0
C C

Msw1

TSMC 65GP process technology upgraded for 60-GHz application.

VDD VDD VDD

T6 T11 T16
B6
C C T7 T12 T17
Msw7

T5 T10 T15

L1 L2 L3
VDD M2 VDD M4 VDD M6

Circuit simulation in the 60-GHz RDK: RFin

T1

T2
T3

R1
T4
M1

T8
T9 C1

R2
M3

T13
T14 C2

R3
M5

T18
T19 C3
RFout

CB1 CB2 CB3 CB4

VB1 VB2 VB3

RDK bundled PDK elements:

RF MOS transistor, MOS-Varactor, MOM cap, poly resistor, and inductor
models specifically for 60-GHz design
Transmission line library
Pad structures
Design Elements:
60-GHz LNA, Power Amp and 48-GHz Wideband VCO circuit designs
complete with schematic and layout views plus simulation and verification
test benches
Design and simulation workshop covering:
RF circuit simulation with GoldenGate including advanced Monte Carlo and
corner technologies, advanced convolution and accurate ADS libraries
EM modeling of interconnects, transformers and inductors with Momentum
Bottoms up transistor level performance model generation for system level
verification with GoldenGate & SystemVue

23
Agilent EEsof 60-GHz RDK contributions

Inputs from System-level

Schematic Entry

Circuit Simulation

Layout

DRC/LVS

Parasitic Extraction

GDSII or SOC integration

24
Agilent EEsof 60-GHz RDK contributions
SystemVue Verification

Inputs from System-level

Component Options
Broadband
SPICE

GoldenGate FCE
Schematic Entry Model
Generator
S-parameter

Momentum Simulator

RF-ESL Analysis & Circuit Simulation Inductor & Passive

Design support GoldenGate Component Design

Package & Bond

GoldenGate RFIC Design and Verification Layout wire modeling
QFN Designer

DRC/LVS

Parasitic Extraction

GDSII or SOC integration

25
Agilent EEsof 60-GHz RDK contributions

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver prior to tape-out

EM analysis & verification

Enable EM analysis early and often through integrated solvers

Add off-chip effects & components in overall verification

Addressing integration issues early in the design cycle

26
Agilent EEsof 60-GHz RDK contributions

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver prior to tape-out

EM analysis & verification

Enable EM analysis early and often through integrated solvers

Add off-chip effects & components in overall verification

Addressing integration issues early in the design cycle

27
Top-down ESL architecture verification
Verify at every level vs. consistent 802.11ad TX/RX baseband references
1 3
Initial downconverter
Download to T&M
system architecture (use the same test vectors
(RF chain used directly in system-
for hardware verification,
level performance study)
- 12-Gsa/sec AWG,
- 32-GHz oscilloscope,
- same PHY measurement
algorithms)

PRE-COMPLIANCE
BB/RF Test Device

2
Fast Circuit Envelope verification
(PA model exported from GoldenGate extracted view,
includes freq response, nonlinearity, memory effects)

28
Initial 60GHz Transceiver Architecture
1

Initial architecture selection

and block spec refinement with
SpectraSys

Architecture and block spec validation vs.

consistent 802.11ad TX/RX baseband
references in SystemVue

29
0- to 200-GHz Spectrums & Noise at RX nodes

30
802.11ad PHY simulated results
with RFIC CMOS PA, multipath fading, noise: EVM=2.5%
2

31
Agilent EEsof 60-GHz RDK contributions

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver prior to tape-out

EM analysis & verification

Enable EM analysis early and often through integrated solvers

Add off-chip effects & components in overall verification

Addressing integration issues early in the design cycle

32
 TSMC 60-GHz CMOS mm-Wave RDK
Circuit Example: Transformer coupled Power Amp
Schematic Layout
R1 R1 R1
M1 M3 M4

T1 M2
VDD

RFin RFout

VDD

VDD
VDD

VG2

VG3
VG1

T1
VDD M2

R1 R1 R1
M1 M3 M4

Circuit simulation: EM simulation:

DC, S-Parameters, Pout vs Pin, IP3, Noise Component level: Input/output GSG
Figure, ACPR, PAE, Load Pull, Corners, pads, Transformers, Transmission lines.
Monte Carlo Block level: Passives + interconnects

33
 GoldenGate overview and 60-GHz RDK usage
Best-in-class RF circuit simulator:
R1 R1 R1
M1 M3 M4

Full characterization of complete RF transceivers prior to tape-out RFin

VDD
T1 M2

RFout

VDD

VDD
VDD
Supports all large and small signal RF and transient analyses including large

VG2

VG3
VG1
CORE VDD BUF VDD

T1 Ibias1
VDD M2
LP2 LP2
Vctrl
R1 R1 R1 LP1 LP1
Cvar Cvar vout
M1 M3 M4

signal stability and newly added X-parameter simulation support M1 M2

B0
M3 M4

Ibias2

C C

Msw1
VDD VDD VDD

T6 T11 T16

Advanced analysis support: C

Msw7
C
B6

L1
T5
T7

L2
T10
T12

L3
T15
T17

VDD M2 VDD M4 VDD M6

Broad statistical analysis support like for worst-case PVT corners, various RFin
T1

T2
T3

R1
T4
M1

T8
T9 C1

R2
M3

T13
T14 C2

R3
M5

T18
T19 C3
RFout

CB1 CB2 CB3 CB4

VB1 VB2 VB3

Monte Carlo options and Fast Mismatch & Yield Contributor Analysis
Unique transistor-level PLL Jitter and Noise option

Automation & ease-of use:

Built-in and easy access to multi-dimensional sweeps, Optimization, Monte Carlo
or load-pull analysis along with simulation management capabilities
Automated EVM, ACPR, Gain Compression, IP3, and load-pull

Unique mm-Wave design support:

Provides access to ADS Data Display with dedicated RF templates and
adsLib with over 150 RF distributed element library components
Handling largest S-Parameter blocks with Multi-Threaded Convolution

Wireless standard-compliant verification:

Verify full radio functionality using Agilents wireless libraries for LTE, WCDMA,
WiMAX, DTV...
Enables scalable system-level solutions from RF architecture exploration
through end-to-end verification with links to SystemVue

34
 TSMC 60-GHz CMOS mm-Wave RDK
Power Amp characterization in GoldenGate

R1 R1 R1
M1 M3 M4

T1 M2
VDD

RFin RFout
VDD

VDD
VDD

VG2

VG3
VG1

T1
VDD M2

R1 R1 R1
M1 M3 M4

Full characterization of performance metrics:

NF, Pout vs Pin, IP3, Load Pull, PAE, ACPR,
30

20
Mag (S21) (dB)

10

-10
Simulation
-20
Measurement

-30
40 45 50 55 60 65 70 75 80
Frequency (GHz)

Gain vs. Frequency

35
Agilent EEsof 60-GHz RDK contributions

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver prior to tape-out

EM analysis & verification

Enable EM analysis early and often through integrated solvers

Add off-chip effects & components in overall verification

Addressing integration issues early in the design cycle

36
 Momentum in the 60-GHz RDK
Most popular 3D planar electromagnetic simulator:
R1 R1 R1
M1 M3 M4

Advanced NlogN and multi-threading solver algorithms for optimal speed, RFin
VDD
T1 M2

RFout

VDD

VDD
VDD
accuracy and capacity

VG2

VG3
VG1
CORE VDD BUF VDD

T1 Ibias1
VDD M2
LP2 LP2
Vctrl
R1 R1 R1 LP1 LP1
Cvar Cvar vout
M1 M3 M4

Arbitrary polygonal meshing with mesh reduction M1 M2

B0
M3 M4

Ibias2

C C

Msw1

Thick metal analysis of side wall currents and efficient via modeling, accounting for
VDD VDD VDD

T6 T11 T16
B6
C C T7 T12 T17
Msw7

T5 T10 T15

skin and proximity effects VDD

L1
M2 VDD
L2
M4 VDD
L3
M6

T1 T3 T9 C1 T14 C2 T19 C3
RFin M1 M3 M5 RFout

T2 R1 T8 R2 T13 R3 T18
T4

Silicon-accurate nanometer RFIC process support: CB1

VB1
CB2
VB2
CB3
VB3
CB4

Automated layout pre-processing like via array merging

Dummy metal fill and process scaling support
Boolean layer operation for native MIM capacitor support

Cadence Virtuoso integration:

Seamlessly integrated into the Cadence Virtuoso 5.1.41 and 6.1.x platforms
Automated stack-up file creation from Cadence technology files
3D Viewer with embedded visualization of surface currents or radiated fields
provides insight on problem areas in layout
Broad-band Spice Model generation for efficient use in time-domain simulations

Going beyond 3D planar applications:

Fast, direct bond wire support
Through Silicon Via (TSV) modeling support
Virtuoso link to EMPro for full 3D EM simulations

37
 Momentum support in TSMC PDKs

Momentum officially qualified for TSMCs 90-, 65- and 40-nm

processes:
Momentum has passed TSMC extensive qualification tests against measurements
up to 30 GHz for different configurations
+20 inductors on average validated with different metal stacks for symmetric, un-
symmetric and center-tapped inductors configurations

Sample results for 40 nm:

Corresponding stack-up files can be downloaded at TSMC online:

Additional Momentum Modules and ADS PDKs available:

+50 Momentum Modules are available for TSMC processes down to 28 nm
~20 ADS front-end PDKs are available for TSMC processes
Full front-to-back ADS for TSMC Integrated Passive Device (IPD) process

For further details go to:

http://www.agilent.com/find/eesof-partners-tsmc

38
Momentum Qualification up to 110 GHz
Passive building blocks (Transformers, Transmission lines)
Momentum
Measurement

S11 dB(S21)

Cs Rs

S22 phase(S21)

Cg1+Cg2 Rg1//Rg2

39
Agilent EEsof 60-GHz RDK contributions

Top-down ESL architecture verification

Verify at every level vs. consistent 802.11ad TX/RX references

RFIC circuit simulation & verification

Full characterization of complete RF transceiver prior to tape-out

EM analysis & verification

Enable EM analysis early and often through integrated solvers

Add off-chip effects & components in overall verification

Addressing integration issues early in the design cycle

40
ADS QFN Designer
Predict Packaged Performance in Minutes
Configure QFN package

Accurately predict real performance

Quickly synthesize complex package,

combine with IC & PCB data
Performance w/ & w/o package

41
Summary
60-GHz RDK Introduction
A silicon-proven MS/RF reference circuit and methodology packaged into a
complete RF reference design kit (RDK)
Provides RF top-down design and bottom-up verification methodologies
from system-level simulation through tape-out
Enables design collaboration with key ecosystem partners to meet
customer needs

Complete RFIC design solutions with dedicated mm-Wave support

Scalable system-level solutions from algorithm development through RF
architecture exploration
Advanced RF design, analysis and simulation support
Silicon-accurate EM verification support
Broad modeling solutions across integration boundaries

Visit us at DAC and IMS for a demo!

42
You are Invited:

Dingqing LuTechnical
Sr. Application Specialist,
Agilent EEsof EDA

Daren McClearnon
ESL Product Planning
Manager
Agilent EEsof EDA

You can find more webcasts

www.agilent.com/find/eesof-innovations-in-eda
www.agilent.com/find/eesof-webcasts-recorded

Copyright 2012 Agilent Technologies

April 5, 2012