Documente Academic
Documente Profesional
Documente Cultură
Assembly Language
Advantages:
Disadvantages:
Need to know detail hardware implementation
Not portable
Slow to development and difficult to debug
Label
Assembly Language 3-3
ASSEMBLER
int num_request_submitters=0;
int i,j; 010000000010000100
000010001000100011
if (!(f = fopen(filename,"r"))) {
xbt_assert1(0,"Cannot open file %s",filename);
101001010010101011
} 000101010010010101
while(fgets(buffer,256,f)) { 010101010101010101
if (!strncmp(buffer,"SCHEDULER",9))
num_schedulers++; 101010101111010101
if (!strncmp(buffer,"REQUESTSUBMITTER",16)) 101010101010100101
num_request_submitters++;
}
111100001010101001
fclose(f);
tmpfilename = strdup("/tmp/jobsimulator_
Assembly code
sll $t3, $t1, 2
add $t3, $s0, $t3
sll $t4, $t0, 2
add $t4, $s0, $t4 Program counter register
lw $t5, 0($t3) register
register
CPU
lw $t6, 0($t4)
slt $t2, $t5, $t6
COMPILER
beq $t2, $zero, endif
add $t0, $t1, $zero
sll $t4, $t0, 2 Control
add $t4, $s0, $t4 ALU Unit
lw $t5, 0($t3)
Assembly Language lw
slt
$t6,
$t2,
0($t4)
$t5, $t6
3-4
beq $t2, $zero, endif
The Big (Simplified) Picture
Hand-written Machine code
High-level code Assembly code 010000101010110110
101010101111010101
101001010101010001
101010101010100101
sll $t3, $t1, 2
char *tmpfilename; 111100001010101001
int num_schedulers=0; add $t3, $s0, $t3
000101010111101011
ASSEMBLER
int num_request_submitters=0; sll $t4, $t0, 2
int i,j; 010000000010000100
add $t4, $s0, $t4
lw $t5, 0($t3)
000010001000100011
if (!(f = fopen(filename,"r"))) {
xbt_assert1(0,"Cannot open file %s",filename); lw $t6, 0($t4) 101001010010101011
} slt $t2, $t5, $t6 000101010010010101
while(fgets(buffer,256,f)) { 010101010101010101
if (!strncmp(buffer,"SCHEDULER",9))
beq $t2, $zero, endif
num_schedulers++; 101010101111010101
if (!strncmp(buffer,"REQUESTSUBMITTER",16)) 101010101010100101
num_request_submitters++;
}
111100001010101001
fclose(f);
tmpfilename = strdup("/tmp/jobsimulator_
Assembly code
sll $t3, $t1, 2
add $t3, $s0, $t3
sll $t4, $t0, 2
add $t4, $s0, $t4 Program counter register
lw $t5, 0($t3) register
register
CPU
lw $t6, 0($t4)
slt $t2, $t5, $t6
COMPILER
beq $t2, $zero, endif
add $t0, $t1, $zero
sll $t4, $t0, 2 Control
add $t4, $s0, $t4 ALU Unit
lw $t5, 0($t3)
Assembly Language
lw
slt
$t6,
$t2,
0($t4)
$t5, $t6
3-5
beq $t2, $zero, endif
ASSEMBLER
int num_request_submitters=0; sll $t4, $t0, 2
int i,j; 010000000010000100
add $t4, $s0, $t4
lw $t5, 0($t3)
000010001000100011
if (!(f = fopen(filename,"r"))) {
xbt_assert1(0,"Cannot open file %s",filename); lw $t6, 0($t4) 101001010010101011
} slt $t2, $t5, $t6 000101010010010101
while(fgets(buffer,256,f)) { 010101010101010101
if (!strncmp(buffer,"SCHEDULER",9)) beq $t2, $zero, endif
num_schedulers++; 101010101111010101
if (!strncmp(buffer,"REQUESTSUBMITTER",16)) 101010101010100101
num_request_submitters++;
}
111100001010101001
fclose(f);
tmpfilename = strdup("/tmp/jobsimulator_
Assembly code
sll $t3, $t1, 2
add $t3, $s0, $t3
sll $t4, $t0, 2
add $t4, $s0, $t4 Program counter register
lw $t5, 0($t3) register
register
CPU
lw $t6, 0($t4)
slt $t2, $t5, $t6
COMPILER
beq $t2, $zero, endif
add $t0, $t1, $zero
sll $t4, $t0, 2 Control
add $t4, $s0, $t4 ALU Unit
lw $t5, 0($t3)
Assembly Language
lw
slt
$t6,
$t2,
0($t4)
$t5, $t6
3-6
beq $t2, $zero, endif
Software Model for the 8086
Overview
Intel 8088 facts
20 bit address bus allow accessing VDD (5V)
1 M memory locations
16-bit internal data bus and 8-bit
external data bus. Thus, it need 20-bit
8-bit data
address
two read (or write) operations to
read (or write) a 16-bit datum control
8088 control
signals
Byte addressable and byte-swapping
signals
To 8088 from 8088
Word: 5A2F
CLK
Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)
Assembly Language 3-9
AH AL BH BL CH CL DH DL
AH AL BH BL CH CL DH DL
SI
DI
BP
SP
IP
= FLAGS
CS
DS
SS
ES
16 bits
Control
ALU
Assembly Language
Unit 3-17
BX BH BL Base
Data Group
CX CH CL Counter
DX DH DL Data
SP Stack Pointer
BP Base Pointer
Pointer and
Index Group
SI Source Index
DI Destination Index
Flag Register
Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
OF DF IF TF SF ZF AF PF CF
EU Operation
DS Data Segment
SS Stack Segment
ES Extra Segment
Assembly Language 3-25
Examples
CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0
DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
Assembly Language 3-26
Fetching Instructions
Where to fetch the next instruction?
8088 Memory
CS 1234
IP 0012 12352 MOV AL, 0
12352
Update IP
After an instruction is fetched, Register IP is updated as follows:
For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction,
the IP is updated to 0014
DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0
DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0
In-class Exercise
Instruction Format
General Format of Instructions
Label: It is optional. It provides a symbolic address that can be used in branch instructions
Opcode: It specifies the type of instructions
Operands: Instructions of 80x86 family can have one, two, or zero operand
Comments: Only for programmers reference
CODE ENDS
END TOTAL
Assembler Directives
SEGMENT directive
ENDS directive
END directive
ORG directive
DB: Define Byte; DW, .
ASSUME directive
Specifies the segment register (segment Register) that will be used to calculate the effective
addresses for all labels and variables defined under a given segment or group name (segment Na
RET
END TOTAL
Assembly Language 3-39
library
Assembler Linker
Source files
Syntax check OBJ
Translate source files
files into
machine code Executable
OBJ
files
files
Assemblers
Syntax check;
ML /c /Fl numoff.asm Translate assembly instructions into machine codes
Binary file