Documente Academic
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(Contact information)
PROFESSIONAL OBJECTIVE
Seeking a xxxxx engineering position with an opportunity for growth
SUMMARY
- Gained hands-on experience in xxxxx design projects by working with instructors who are
actively involved in industry projects, working as TA and lab assistant in related courses, and
supported by the school facility which maintains industry-grade design tools.
- Hardworking, self-motivated, highly responsible and dedicated to work, can work with team or
independently, good at solving problems, and interested in learn new things. Fluent in English and
xxxxx; good communication skills.
- CAD tools: Cadence Place and Route Tool SOCEncounter; Cadence Opus -Hspice
Synopsys Design Compiler Verilog.
- Other computer skills: C, Assembly, UNIX, Linux, Tcl, Delphi, SQL, VB, HTML
QUALIFICATIONS
Experience/Skills
1. Good understanding of the flow of ASIC design from front-end to backend
- Familiar with RTL design using Verilog
- Familiar with Logic synthesis using design compiler
- Familiar with Static Timing Analysis using Prime time
2. Hands-on projects of backend design
- Low Power Implementation in 65nm million-gate hierarchical design.
- Through the flow from Netlist to GDS II
- Strong knowledge of floor plan, power plan, placement, Clock tree synthesis, routing, STA, LVS,
DRC, tape out
- Familiar with antenna check, signal integrity, IR drop analysis, MSMV, and timing closure
- Using Tcl to simplify the processing of design