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24xx64
A1 2 7 WP
24LC64 2.5-5.5V 400 kHz I, E
100 A2 3 6 SCL
kHz for Vcc < 2.5V.
100 kHz for E temperature range.
Vss 4 5 SDA
FEATURES
Low power CMOS technology
- Maximum write current 3 mA at 5.5V SOIC
- Maximum read current 400 A at 5.5V 1 8
A0 VCC
- Standby current 100 nA typical at 5.5V
24xx64
A1 2 7 WP
2-wire serial interface bus, I2C compatible
Cascadable for up to eight devices A2 3 6 SCL
Self-timed ERASE/WRITE cycle
VSS 4 5 SDA
32-byte page or byte write modes available
5 ms max write cycle time
Hardware write protect for entire array
TSSOP
Output slope control to eliminate ground bounce 1 8
WP SCL
24xx64
Schmitt trigger inputs for noise suppression
Vcc 2 7 SDA
1,000,000 erase/write cycles guaranteed
A0 3 6 Vss
Electrostatic discharge protection > 4000V
A1 4 5 A2
Data retention > 200 years
8-pin PDIP, SOIC (150 and 208 mil) and TSSOP
packages; 14-pin SOIC package
Temperature ranges:
BLOCK DIAGRAM
- Industrial (I): -40C to +85C A0A2 WP
- Automotive (E) -40C to +125C HV GENERATOR
DESCRIPTION
I/O MEMORY
EEPROM
The Microchip Technology Inc. 24AA64/24LC64 CONTROL CONTROL XDEC ARRAY
LOGIC LOGIC
(24xx64*) is a 8K x 8 (64K bit) Serial Electrically Eras-
able PROM capable of operation across a broad volt- PAGE LATCHES
TF THIGH VHYS TR
SCL
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP
TBUF
TAA
SDA
OUT
WP (protected) THD:WP
TSU:WP
(unprotected)
2.3 SCL Serial Clock A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
This input is used to synchronize the data transfer from operations must end with a STOP condition.
and to the device.
4.4 Data Valid (D)
2.4 WP
The state of the data line represents valid data when,
This pin can be connected to either Vss, Vcc or left after a START condition, the data line is stable for the
floating. An internal pull-down resistor on this pin will duration of the HIGH period of the clock signal.
keep the device in the unprotected state if left floating. The data on the line must be changed during the LOW
If tied to Vss or left floating, normal memory operation period of the clock signal. There is one clock pulse per
is enabled (read/write the entire memory 0000-1FFF). bit of data.
If tied to VCC, WRITE operations are inhibited. Read Each data transfer is initiated with a START condition
operations are not affected. and terminated with a STOP condition. The number of
the data bytes transferred between the START and
3.0 FUNCTIONAL DESCRIPTION STOP conditions is determined by the master device.
SDA
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Transmitter must release the SDA line at this point Receiver must release the SDA line at this point
allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data.
acknowledge the previous eight bits of data.
A A A A A A A A A A
1 0 1 0 2 1 0 R/W X X X 12 11 10 9 8 7 0
CONTROL CHIP
CODE SELECT X = Dont Care Bit
BITS
6.1 Byte Write The write control byte, word address and the first data
byte are transmitted to the 24xx64 in the same way as
Following the start condition from the master, the in a byte write. But instead of generating a stop condi-
control code (four bits), the chip select (three bits), and tion, the master transmits up to 31 additional bytes
the R/W bit (which is a logic low) are clocked onto the which are temporarily stored in the on-chip page buffer
bus by the master transmitter. This indicates to the and will be written into memory after the master has
addressed slave receiver that the address high byte will transmitted a stop condition. After receipt of each word,
follow after it has generated an acknowledge bit during the five lower address pointer bits are internally incre-
the ninth clock cycle. Therefore, the next byte transmit- mented by one. If the master should transmit more than
ted by the master is the high-order byte of the word 32 bytes prior to generating the stop condition, the
address and will be written into the address pointer of address counter will roll over and the previously
the 24xx64. The next byte is the least significant received data will be overwritten. As with the byte write
address byte. After receiving another acknowledge sig- operation, once the stop condition is received, an inter-
nal from the 24xx64 the master device will transmit the nal write cycle will begin (Figure 6-2). If an attempt is
data word to be written into the addressed memory made to write to the array with the WP pin held high, the
location. The 24xx64 acknowledges again and the device will acknowledge the command but no write
master generates a stop condition. This initiates the cycle will occur, no data will be written and the device
internal write cycle, and during this time the 24xx64 will will immediately accept a new command.
not generate acknowledge signals (Figure 6-1). If an
attempt is made to write to the array with the WP pin 6.3 Write Protection
held high, the device will acknowledge the command
The WP pin allows the user to write protect the entire
but no write cycle will occur, no data will be written and
array (0000-1FFF) when the pin is tied to Vcc. If tied to
the device will immediately accept a new command.
VSS or left floating, the write protection is disabled. The
After a byte write command, the internal address
WP pin is sampled at the STOP bit for every write com-
counter will point to the address location following the
mand (Figure 1-1) Toggling the WP pin after the STOP
one that was just written.
bit will have no effect on the execution of the write cycle.
A A A A
BUS ACTIVITY C C C C
K K K K
X = dont care bit
S
T S
BUS ACTIVITY A CONTROL ADDRESS ADDRESS T
MASTER R BYTE HIGH BYTE LOW BYTE DATA BYTE 0 DATA BYTE 31 O
T P
SDA LINE A A A XXX P
S10 1 0 2 1 0 0
A A A A A
BUS ACTIVITY C C C C C
K K K K K
X = dont care bit
Did Device NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 8-1: CURRENT ADDRESS READ Sequential reads are initiated in the same way as a ran-
dom read except that after the 24xx64 transmits the
S
T S first data byte, the master issues an acknowledge as
BUS ACTIVITY A CONTROL DATA T
MASTER opposed to the stop condition used in a random read.
R BYTE BYTE O
T P This acknowledge directs the 24xx64 to transmit the
SDA LINE S 1 0 1 0 A AA 1 P
next sequentially addressed 8-bit word (Figure 8-3).
2 1 0 Following the final byte transmitted to the master, the
A N
BUS ACTIVITY C O
master will NOT generate an acknowledge but will gen-
K
A
erate a stop condition. To provide sequential reads the
C 24xx64 contains an internal address pointer which is
K incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 1FFF to address 0000 if the master acknowl-
edges the byte received from the array address 1FFF.
SDA LINE P
A A A A N
C C C C O
BUS ACTIVITY K K K K A
C
K
24xx64 /P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body, EIAJ standard), 8-lead
Package: SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead
ST = TSSOP, 8-lead
Temperature I = -40C to +85C
Range: E = -40C to -125C
All rights reserved. 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper.
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