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Documente Profesional
Documente Cultură
FACULTY OF ENGINEERING
COURSE ELECTRONICS
EXPERIMENT NO. 1
Total
COMMENTS
TABLE OF CONTENTS
1.0 INTRODUCTION 1
2.0 OBJECTIVES 1
3.0 APPARATUS 1
4.0 PRE-LAB DIAGNOSTIC TEST 2
5.0 PROCEDURES 3
5.1 PART I 3
5.1.1
74LS08 GATE EXPERIMENT 3
5.1.2
74LS32 GATE EXPERIMENT 3
5.1.3
74LS04 GATE EXPERIMENT 4
5.1.4
74LS00 GATE EXPERIMENT 5
5.1.5
74LS02 GATE EXPERIMENT 5
5.1.6
74LS86 GATE EXPERIMENT 6
5.2 PART II 7
5.2.1 OR GATE WITH INVERTER INPUTS 7
5.2.2 CASCADED 3-INPUT OR GATES 7
5.3 PART III 8
5.3.1 3-INPUT MAJORITY GATE CIRCUIT 8
6.0 RESULTS 8
6.1 PART I 8
6.1.1
74LS08 GATE EXPERIMENT 8
6.1.2
74LS32 GATE EXPERIMENT 9
6.1.3
74LS04 GATE EXPERIMENT 10
6.1.4 74LS00 GATE EXPERIMENT 10
6.1.5
74LS02 GATE EXPERIMENT 11
6.1.6
74LS86 GATE EXPERIMENT 12
6.2 PART II 13
6.2.1 OR GATE WITH INVERTER INPUTS 13
6.2.2 CASCADED 3-INPUT OR GATES 14
6.3 PART III 15
6.3.1 3-INPUT MAJORITY GATE CIRCUIT 15
7.0 TASK (HOMEWORK) 16
7.1.1
RESULT (HOMEWORK) 17
8.0 APPENDIX 19
CONTENTS OF TABLE
In this experiment, familiarity with the elementary logic gates and their
usage for designing and implementing logic circuits are introduced. In this
experiment, conventional methods will be used, ICs will be plugged on
a breadboard and connected with wires. In a binary digital system, infor
mation is represented by the combination of ONEs and ZEROs. Each
of these signal levels are indeed two non-overlapping ranges of voltages.
There are two ways to assign the Boolean 0 and 1 values to these
two voltage ranges: positive logic and negative logic interpretation. In
positive logic, the HIGH (H) voltage level is assigned as 1 whereas the
LOW (L) level is assigned as 0. A logic gate (AND, OR, NAND, etc.)
is defined based on it is input-output characteristic, which is determined
by its internal structure.
2.0 OBJECTIVES
3.0 EQUIPMENT/APPARATUS
i. Digital Trainer
ii. Breadboard
iii. Components (74LS00, 74LS04, 74LS08, 74LS10, 74LS32, 74LS86,
74LS02)
1
4.0 PRE-LAB DIAGNOSTIC TEST
QUESTION ANSWER
2
5.0 PROCEDURES
5.1 PART I
Figure 1: 74SL08 Connection
1. Observe Figure 1 (marked 74LS08), plug the IC the digital trainer. Connect the
INPUT A, B to Data Switch SW1, SW2. Connect the output Y to LED display.
2. Change Data Switches SW1, SW2 to turn the LED light on or off (that means the
OUTPUT is 1 or 0) observe the relationship between input & output, and then
record it in Table 2.
2. Change Data Switches SW1, SW2 from 0 to 1 and back to 0, then observe
the input and output situations, record them in Table 3.
4
5.1.4 74LS00 GATE EXPERIMENT
1. Observe Figure 4 (marked 74LS00), plug the IC the digital trainer. Connect the
INPUT A, B to Data Switch SW1, SW2 respectively. Connect the output Y to
LED display.
2. Change Data Switches SW1, SW2 to turn the LED light on or off (that means the
OUTPUT is 1 or 0, observe the relationship between input and output, and then
record it in Table 5.
5.1.5 74LS02 GATE EXPERIMENT
5
1. Observe Figure 5 (marked 74LS02), plug the IC the digital trainer. Connect the
INPUT A, B to Data Switch SW1, SW2 respectively. Connect the output Y to
LED display.
2. Change Data Switches SW1, SW2 from 0 to 1 and back to 0, then observe
the input and output situations, record them in Table 6.
5.1.6 74LS86 GATE EXPERIMENT
Figure 6: 74LS86 Connection
1. Observe Figure 6 (marked 74LS86), plug the IC the digital trainer. Connect the
INPUT A, B to Data Switch SW1, SW2 respectively. Connect the output Y to
LED display.
2. Change Data Switches SW1, SW2 from 0 to 1 and back to 0, then observe
the input and output situations, record them in Table 7.
6
5.2 PART II
5.2.1 OR GATE WITH INVERTER INPUTS
7
5.3 PART III
6.0 RESULTS
6.1 PART I
8
Boolean Expression: Y =AB
INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Table 3: OR Gate Truth Table
9
6.1.3 74LS04 GATE EXPERIMENT
INPUT OUTPUT
A Y
0 0
0 1
10
Boolean Expression: Y =AB
INPUT OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Table 6: NOR Gate Truth Table 11
6.1.6 74LS86 GATE EXPERIMENT
INPUT OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
12
6.2 PART II
6.2.1 OR GATE WITH INVERTER INPUTS
INPUT OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
13
6.2.2 CASCADED 3-INPUT OR GATES
INPUT OUTPUT
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
14
6.3 PART III
6.3.1 3-INPUT MAJORITY GATE CIRCUIT
INPUT OUTPUT
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
15
7.0 TASK (HOMEWORK)
16
7.1 RESULT (HOMEWORK)
A OUTPUT
0 1
1 0
INVERTER
A B OUTPUT
0 0 0
AND
0 1 0
1 0 0
1 1 1
A B OUTPUT
0 0 0
AND
0 1 1
1 0 1
1 1 1
A B OUTPUT
0 0 1
NOR 0 1 0
1 0 0
1 1 0
A B OUTPUT
XOR 0 0 0
0 1 1
1 0 1
1 1 0
18
8.0 APPENDIX
19