05165453

IEEE Standard for Describing
On-Chip Scan Compression

TM
1450.6.1
IEEE Computer Society

Sponsored by the
Test Technology Standards Committee
IEEE
3 Park Avenue IEEE Std 1450.6.1-2009
New York, NY 10016-5997, USA
13 July 2009
IEEE Std 1450.6.1-2009

Sponsor
Test Technology Standards Committee

of the
IEEE Computer Society
Approved 13 May 2009
IEEE-SA Standards Board

Abstract: This standard defines how the necessary information is passed from scan insertion to
pattern generation and from pattern generation to diagnosis such that different tool vendors could
be used for each step independent of on-chip scan compression logic used.
Keywords: chip design, design automation, on-chip scan compression, pattern generation, scan
insertion
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Introduction
This introduction is not part of IEEE Std 1450.6.1-2009, IEEE Standard for Describing On-Chip Scan Compression.
The purpose of this standard is to provide a sufficient description of on-chip scan compression structures,
operation, and connectivity such that EDA tools may interoperate for pattern generation and diagnosis. The
standard extends the CTL language (IEEE Std 1450.6), which provides such information for designs without
on-chip scan compression structures.
Notice to users
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iv Copyright 2009 IEEE. All rights reserved.

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Copyright 2009 IEEE. All rights reserved. v

Participants
At the time this standard was submitted to the IEEE-SA Standards Board for approval, the OCI (Open Com-
pression Interface) Working Group had the following membership:
Bruce Cory (NVIDIA), Chair
Dwayne Burek (Magma) Geir Eide (Magma) Brion Keller (Cadence)

Phil Burlison (Verigy) Rohit Kapur (Synopsys) Kee Sup Kim (Intel)
Al Crouch (Asset Intertech) Mark Kassab (Mentor Graphics) Steve Oakland (IBM)
Manish Dandekar (Intel) Rolf Schlagenhaft (Freescale)
The following members of the entity balloting committee voted on this standard. Balloters may have voted
for approval, disapproval, or abstention.
Accellera Intel Nvidia
Cadence Design Mentor Graphics Synopsys
When the IEEE-SA Standards Board approved this standard on 13 May 2009, it had the following
membership:
Robert M. Grow, Chair
Thomas Prevost, Vice Chair
Steve M. Mills, Past Chair
Judith Gorman, Secretary
John Barr Mark Epstein David J. Law
Karen Bartleson Alexander Gelman Ted Olsen
Victor Berman Jim Hughes Glenn Parsons
Richard H. Hulett Ronald C. Petersen
Ted Burse
Young Kyun Kim Narayanan Ramachandran
Richard DeBlasio Joseph L. Koepfinger* Jon Walter Rosdahl
Andy Drozd John Kulick Sam Sciacca
*Member Emeritus
Also included are the following nonvoting IEEE-SA Standards Board liaisons:
Howard L. Wolfman, TAB Representative

Michael Janezic, NIST Representative
Satish Aggarwal, NRC Representative
Lorraine Patsco
IEEE Standards Program Manager, Document Development
Michael Kipness
IEEE Standards Program Manager, Technical Program Development
vi Copyright 2009 IEEE. All rights reserved.

Contents
1. Overview............................................................................................................................................... 1
1.1 Scope .......................................................................................................................................... 1
1.2 General ....................................................................................................................................... 1
1.3 Conceptual data flow.................................................................................................................. 2
1.4 High-level implementation details ............................................................................................. 3
1.5 Limitations of this standard........................................................................................................ 5
1.6 Structure of this standard............................................................................................................ 5
2. Normative references............................................................................................................................ 6
3. Definitions, acronyms, and abbreviations ............................................................................................ 6

3.1 Definitions .................................................................................................................................. 6
3.2 Acronyms and abbreviations ...................................................................................................... 6
4. New blocksCompressionStructures .................................................................................................. 7

4.1 CompressionStructures block..................................................................................................... 7
4.2 CompressionStructures block syntax description ...................................................................... 7
4.3 CompressionStructures block example ...................................................................................... 8
5. STIL blockextensions to IEEE Std 1450-1999, Clause 8................................................................. 9

5.1 STIL syntax ................................................................................................................................ 9
5.2 STIL syntax description ............................................................................................................. 9
5.3 STIL syntax example ................................................................................................................. 9
6. Environment blockextensions to IEEE Std 1450.1-2005, Clause 17 ............................................. 10

6.1 Environment block ................................................................................................................... 10
6.2 Environment block syntax description ..................................................................................... 10
6.3 Environment block example..................................................................................................... 12
7. Semantics updates............................................................................................................................... 12
Annex A (informative) Examples.................................................................................................................. 14
Copyright 2009 IEEE. All rights reserved. vii

IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or
environmental protection in all circumstances. Implementers of the standard are responsible for
determining appropriate safety, security, environmental, and health practices or regulatory requirements.
This IEEE document is made available for use subject to important notices and legal disclaimers. These
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They can also be obtained on request from IEEE or viewed at http://standards.ieee.org/IPR/
disclaimers.html.
1. Overview
1.1 Scope
This standard defines how the necessary information is passed from scan insertion to pattern generation and
from pattern generation to diagnosis such that different tool vendors could be used for each step independent
of on-chip scan compression logic used.
1.2 General
Flows for scan-based test tools are broken into three main stages. Test logic insertion, pattern generation,
and diagnosis. Test logic insertion does insertion and verification of test logic. Pattern generation uses the
test logic to make test patterns that can be used to verify if the design is fabricated correctly. Diagnosis is
used to identify the failing location in a specific device. Diagnosis information can also be used to increase
future yield and to solve problems that keep a design from going to market.
This standard, the Open Compression Interface (OCI), defines on-chip scan compression structures
(OCSCS), which can be used to pass information from test logic insertion to pattern generation, and from
pattern generation to diagnosis, such that interoperability of electronic design automation (EDA) tools is
possible. These structures
Only reveal as much hardware implementation as necessary for pattern generation and diagnosis
Do not limit EDA companies from innovating and developing their own compression solutions
Copyright 2009 IEEE. All rights reserved. 1

IEEE Std 1450.6.1-2009 IEEE STANDARD FOR DESCRIBING
Support most types of structures for input and output compression
OCSCS are defined here as an extension of IEEE Std 1450.6TM-2005 [Core Test Language (CTL)].1 This
standard highlights the revised CTL syntax and then provides several examples that cover common
compression structure types. The actual OCI syntax and semantics appear prior to the examples.
1.3 Conceptual data flow
Figure 1 shows the OCI conceptual data flow from test logic insertion to pattern generation and from pattern
generation to diagnosis. Both the OCI flow (assuming a different vendor for each stage) and the current flow
(same vendor for each stage) are shown. Since same-vendor tools have their own way of linking different
stages of the flow together, OCI is only needed for changing stages when any previous step was completed
by a different vendor. If different vendors were used, then all the data OCI would normally add in the
previous stages is needed.
Current OCI
Inserts test structures
Test Logic Verifies test structures (DRC)
Insertion Adds information for Pattern Generation
- Allowed Sequences
- Compression structure description
OCI Transfer - Symbolic to netlist name mapping
Data
Assumes IP implemented correctly

Pattern Uses equations and sequences
Generation Writes out pattern data
Add information for Diagnosis
- identify key events
OCI Transfer
Data
Uses patterns, sequences, and event identifiers

Diagnosis - calculate failing defect candidates
Figure 1Conceptual OCI flow
The test logic insertion stage has the best understanding of the test structure being implemented. Test logic
insertion tools are developed based on specific compression structures and have many special design rule
checks implemented so customers have as good a chance as possible to generate working, highly effective
patterns the first time. The time and knowledge necessary to develop all of the design rule checks is
significant. Due to this, the OCI flow presumes the pattern generation tool does not need to perform test
structure verification. In the case where a design house is integrating a core with in-house design logic, the
test structure in the core is presumed to be verified by the core provider and all core-level OCI information
needed for pattern generation shall be in the OCI-compliant CTL file the core provider gives the design
house. The design house integrating the core is responsible for generating and verifying the final OCI
information passed to pattern generation.
The OCI-specific information passed from test logic insertion to pattern generation includes pattern
sequence restrictions, a description of compression hardware, netlist mapping points, and vendor-specific
data to ensure vendor flows are as easy to use as possible when using OCI. For a more detailed description
of how CTL is leveraged to pass information from test logic insertion to pattern generation, see 1.4.
The pattern generation stage can be very time consuming. The automatic test pattern generator (ATPG)
determines which logic values are needed on scan cells to detect the most faults by each test pattern. After a
pattern is generated, it is then simulated to determine how many faulty locations have been detected. This
1
For information on references, see Clause 2.
2 Copyright 2009 IEEE. All rights reserved.

ON-CHIP SCAN COMPRESSION IEEE Std 1450.6.1-2009
sequence is repeated until as many as possible faulty locations have been detected. For chips without on-
chip scan compression, the value loaded and unloaded from each scan cell can be mapped directly to a
unique value loaded into the chip and to a unique value unloaded from the chip. Only sequence definitions
that describe how to initialize, load, unload, and apply tests are needed by pattern generation for this case.
On-chip scan compression needs more information. Putting a logic value in a scan cell requires a value to be
loaded into the chip at a previous point in time and likely forces other scan cells to be put to certain logic
values. Checking that a value is in a scan cell may require values in masking logic or on other scan cells.
Also, on-chip scan compression hardware may restrict the length of a sequence or require a relationship
between sequences because of how the hardware is implemented. To do pattern generation efficiently, OCI
passes pattern generation sequences, sequence limitations/relationships, and symbolic descriptions of the
compression hardware created by the test logic insertion stage.
The output test patterns generated by pattern generation need to be diagnosable using both EDA diagnosis,
that can isolate to a gate or net, and on the tester, where isolation is possible due to the failing scan cell or
scan chain. To enable this capability, the pattern generation stage shall identify key events in the pattern data
and pass this information to diagnosis. The information is passed through OCI by updating the sequences
and/or by adding information to the test pattern data. For a more detailed description of how CTL is
leveraged to pass information from pattern generation to diagnosis, see 1.4.
The diagnosis stage uses the key event information added by pattern generation to map each automatic test
equipment (ATE) failure back to a list of defect candidates that might have caused that failure. The
diagnosis stage does not add any new information to the OCI file.
1.4 High-level implementation details
OCI data is passed from stage to stage to allow tool interoperability. The format of the OCI data passed
leverages CTL (IEEE Std 1450.6-2005) as a foundation with some new syntax and semantics added where
needed. Figure 2 shows the information in an OCI file after test logic insertion.

OCI File
Signals, Variables, Header Information
Timing Specifications
Sequences
Procedures or Macros {
Step 1
Step 2
Step 3
}
Scan Structures Definitions
ScanStructures my_chains {
Chain 1
Chain 2
}
Compression Structures Definitions
CompressionStructures my_comp_structs {
Compressor or Decompressor {
Symbolic description,
Sequence restrictions,
Vendor area
}
}
Environment
Environment env_name {
NameMaps {
}

}
Figure 2OCI file structure after logic insertion
The goal here is to provide a syntax such that tools support a uniform interface and no special
implementation is needed for the various compression technologies. This is achieved by using sequences to
handle the complexities of applying the pattern data and compression equations to handle the data
relationships between scan cells and the inputs and outputs of the design.
The sequences are procedures and macros provided by the compression technology implementor, while the
pattern data provides the data to the sequences. The data relationship of the scan data is provided in
equations in the compression structure block. Pattern generation uses the equations to translate the scan data
to the scan-in and scan-outs and provide the patterns that invoke the existing macros and procedures with the
data passed to them.

The Environment syntax (see Clause 6) can be used to define the compression structures for different
modes, allowing for a mix and match of multiple vendor solutions as needed.
1.5 Limitations of this standard
The limitations of this standard are as follows:

a) OCI does not support definition of compression structures if the internal scan chains can
dynamically change length from pattern-to-pattern.
b) OCI does not support interoperability of test logic insertion.
1.6 Structure of this standard
This standard is to be used with IEEE Std 1450TM-1999, IEEE Std 1450.1TM-2005, IEEE Std 1450.2TM-2002,
and IEEE Std 1450.6-2005. The conventions established and defined in IEEE Std 1450-1999 are used in this
standard and are included verbatim below.
Many clauses in this document add additional constructs to existing clauses in IEEE Std 1450-1999, IEEE
Std 1450.1, and IEEE Std 1450.6-2005 and are so identified in the title. Most constructs defined in this
standard are limited to the Environment and Test Mode structures that were extended by IEEE Std 1450.6-
2005.
The following is a copy of the conventions as defined in IEEE Std 1450-1999 and followed herein.
Different fonts are used as follows:

SMALL CAP TEXT is used to indicate user data.
courier text is used to indicate code examples.
In the syntax definitions

a) SMALL CAP TEXT is used to indicate user data.
b) bold text is used to indicate keywords.
c) italic text is used to reference metatypes.
d) () indicates optional syntax that may be used zero or one time.
e) ()+ indicates syntax that may be used one or more times
f) ()* indicates optional syntax that may be used zero or more times.
g) <> indicates multiple choice arguments or syntax.
h) Defaults, where appropriate, are underlined in the syntax.
In the syntax explanations, the verb shall is used to indicate mandatory requirements. The meaning of a
mandatory requirement varies for different readers of the standard:
To developers of tools that process OCI (readers), shall denotes a requirement that the standard
imposes. The resulting implementation is required to enforce this requirement and issue an error if
the requirement is not met by the input.
To developers of OCI files (writers), shall denotes mandatory characteristics of the language. The
resulting output shall conform to these characteristics.
To the users of OCI, shall denotes mandatory characteristics of the language. Users may depend on
these characteristics for interpretation of the CTL source.
The language definition clauses contain statements that use the phrase it is an error. This phrase indicates
improperly defined CTL information.

2. Normative references
OCI extends syntax defined by IEEE Std 1450-1999, IEEE Std 1450.1-2005, and IEEE Std 1450.6-2005.
Exceptions, if any, to these standards are defined in this standard. The following referenced documents are
indispensable for the application of this document (i.e., they must be understood and used, so each
referenced document is cited in text and its relationship to this document is explained). For dated references,
only the edition cited applies. For undated references, the latest edition of the referenced document
(including any amendments or corrigenda) applies.
IEEE Std 1450-1999, IEEE Standard Test Interface Language (STIL) for Digital Test Vectors.2, 3
IEEE Std 1450.1-2005, IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE
Std 1450-1999) for Semiconductor Design Environments.
IEEE Std 1450.2-2002, IEEE Standard for Extensions to Standard Test Interface Language (STIL) for DC
Level Specification.
IEEE Std 1450.6-2005, IEEE Standard for Standard Test Interface Language (STIL) for Digital Test Vector
DataCore Test Language (CTL).
3. Definitions, acronyms, and abbreviations
3.1 Definitions
For the purposes of this standard, the following terms and definitions apply. Since OCI is the union of the
syntax defined in four documents, the terminology defined in the other documents (IEEE Std 1450-1999,
IEEE Std. 1450.1-2005, IEEE Std. 1450.2-2002, and IEEE Std 1450.6-2006) is applicable in this document.
IEEE 100, The IEEE Standard Dictionary of Electrical and Electronics Terms, Seventh Edition, should be
referenced for terms not defined in this standard.
3.1.1 compressor: Test logic that compacts internal scan-chain data (before it gets to output signal pins).
3.1.2 decompressor: Test logic that expands input signal pin data (before it gets to internal scan-chains).
3.2 Acronyms and abbreviations
1450_0 IEEE Std 1450-1999

ATE automatic test equipment
ATPG automatic test pattern generator
CTL Core Test Language (aggregate syntax of IEEE Std 1450.6-2005, IEEE Std 1450.1-2005, IEEE Std
1450.2-2002, and IEEE Std 1450-1999)
DFT design for test (it represents circuit modifications such as scan chains that are created for test)
EDA electronic design automation
LFSR linear feedback shift register
2IEEE publications are available from the Institute of Electrical and Electronics Engineers, Inc., 445 Hoes Lane, Piscataway, NJ 08854,
USA (http://standards.ieee.org/).
3
The IEEE standards or products referred to in this standard are trademarks of the Institute of Electrical and Electronics Engineers, Inc.

MISR multiple input shift register

OCI Open Compression Interface
OCSCS on-chip scan compression structures
SoC System on Chip
STIL Standard Test Interface Language (combination of IEEE Std 1450-1999, IEEE Std 1450.1-2005,
and IEEE Std 1450.2-2002)
4. New blocksCompressionStructures
This clause defines a new block CompressionStructures that is allowed at the top level of a CTL file and
within CoreType blocks.
4.1 CompressionStructures block
The CompressionStructures block is required for chips with on-chip scan compression logic when a
different tool vendor is used for test logic insertion, pattern generation, or diagnosis. A CTL file, including a
CompressionStructures block, standardizes how on-chip scan compression information is passed to enable
different vendor tool interoperability.
The CompressionStructures block is primarily used to describe the on-chip scan compression compressor
and decompressor logic, including how they connect to the internal scan chains and signal pins. A
combination of the CompressionStructures, ScanStructures, CTLMode, MacroDefs, and Procedures
blocks shall describe the behavior of the compressor and decompressor logic from the internal scan chains to
signal pins. Optionally, the CompressionStructures block can also be used to identify vendors and include
vendor-specific information.
(CompressionStructures (COMPRESSION_STRUCTURE_NAME) { (1)
(<Decompressor | Compressor> COMPRESSION_BLOCK_NAME { (2)
(Vendor vendor_name < ; (3)
| { (vendor_value1 = vendor_value2 ; )+ }>)
(SIGNAL_OR_VARIABLE_NAME logic_expression ; )* (4)
(Wire WIRE_NAME logic_expression ; )* (5)
(State state_name {Data logic_expression ; Clock logic_expression ; (6)
(Reset logic_expression ; ) (Set logic_expression ; )
(FuncX logic_expression ; )} )*
})+
})*
(CoreType CORE_TYPE_NAME {
.
(CompressionStructures (COMPRESSION_STRUCTURE_NAME) { (7)
compression_structure_definitions
})*
})*
4.2 CompressionStructures block syntax description
(1) CompressionStructures COMPRESSION_STRUCTURE_NAME: This statement begins the definition of a

block that defines all, or part of, an on-chip scan compression structure. All compression structures shall be
defined in this block. The COMPRESSION_STRUCTURE_NAME shall be unique. If this name is not specified,
this structure is global across all modes (the default case).

All shift registers or scan chains only used within compression logic can be defined via ScanStructures
statements (see 20.1 of IEEE Std 1450-1999) or as States in Decompressor and Compressor blocks.
CompressionStructures specified via DomainReferences in a CTL block are interoperable.
(2) Decompressor | Compressor COMPRESSION_BLOCK_NAME: This statement separates the definition of

the input decompressor and output compressor portion of the on-chip scan compression structure. Masking
logic can be defined in either block. The COMPRESSION_BLOCK_NAME shall be unique in its domain name
scoping level (see 6.9 of IEEE Std 1450-1999 and 14.3 of IEEE Std 1450.1-2005). The Decompressor and
Compressor blocks shall not be empty. Compressor block outputs shall not feed into decompressor block
inputs during shifting.
(3) Vendor: This block specifies the vendor of the on-chip scan compression hardware, where
vendor_name is a string (see 9.2 of IEEE Std 1450.6-2005).
The original vendor may also choose to include a list of expressions in this block (where
vendor_value1 and vendor_value2 are strings). This list is not guaranteed to be usable by anyone other
than the originating vendor.
(4) SIGNAL_OR_VARIABLE_NAME logic_expression: This statement specifies the hardware relationship

between a signal or Variable and the logic feeding it (where logic_expression is a single quoted expression
of Signals, Wires, States, Variables, scan cells, and signal groups operating on each other), by using the
following set of Verilog operators: MUX (?:), OR (|), XOR (^), AND (&), or INVERT (~).
(5) Wire WIRE_NAME logic_expression: This statement specifies the hardware relationship between a Wire
and the logic feeding it, by using the following set of Verilog operators: MUX (?:), OR (|), XOR (^), AND
(&), or INVERT (~). The Wire keyword defines the WIRE_NAME signal as a Pseudo whose scope is only
valid within the specified Decompressor or Compressor block.
(6) State state_name: This statement defines positive edge flip-flops used in the on-chip scan compression
hardware. The state_name shall be unique within CompressionStructures blocks. If a state element is
defined in both the ScanStructures and CompressionStructures blocks, and both are referenced in the
same CTL mode DomainReference block, the ScanStructures cell name shall be the same as the
CompressionStructures state name. state_names inherit all naming capabilities and rules of ScanCell
names.
Any Data for the defined state element specifies generic data input. The Clock, Reset, Set, and FuncX
for the defined state element are (presumed) active high. When Set and Reset are both active, any
resulting behavior is undefined. When FuncX is active, the state element is set to an undefined state.
(7) Added CompressionStructures syntax to CoreType blocks to enable hierarchical definition of

compression logic. All symbolic logic_expression and State names can be scoped using the :: and :
operators, as defined in 5.1 of IEEE Std 1450.6-2005.
4.3 CompressionStructures block example
This is a CompressionStructures example for a chip with a combinational compressor and decompressor.
There are four input signals (in0 in3), two output signals (out0 and out1), and three internal scan
chains whose scan inputs are the internal nets chip.si1, chip.si2, and chip.si3 and whose scan
outputs are the internal nets chip.so1, chip.so2, and chip.so3. More complex examples are
provided in Annex A.
CompressionStructures my_compression {
Decompressor my_decompressor {

Vendor Synopsys {
Decompressor_architecture = mux;
}
chip.si1 in0?in2:in1;
}
Compressor my_compressor {
Vendor Synopsys {
Compressor_architecture = xor;
}
out0 chip.so1 ^ chip.so2;
out1 chip.so2 ^ chip.so3;
}
}
5. STIL blockextensions to IEEE Std 1450-1999, Clause 8
The STIL statement, as defined in IEEE Std 1450-1999, identifies the primary version of IEEE Std 1450-
1999 information contained in a STIL file and the presence of one or more standard Extension constructs.
All other constructs and restrictions for Clause 8 of IEEE Std 1450-1999 are in effect here.
5.1 STIL syntax
STIL IEEE_1450_0_IDENTIFIER {
( EXT_NAME EXT_VERSION; )+ (1)
} // end STIL
5.2 STIL syntax description
(1) EXT_NAME: The specific name of the Extension. This syntax of this standard is identified by the name
Compression. While the Compression concept and mechanisms include IEEE 1450.6, the associated
EXT_NAME for IEEE 1450.6 [namely CTL (and Design)] should be used to indicate use of syntax defined
by IEEE Std 1450.6-2005. Refer to IEEE Std 1450.1-2005 and IEEE Std 1450.6-2005 for details.
EXT_VERSION: The primary version of an EXT_NAME. This version of the standard is identified by the
value 2006.
5.3 STIL syntax example
STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}

6. Environment blockextensions to IEEE Std 1450.1-2005, Clause 17
This section shows the extensions OCI defines for usage within Environment blocks.
6.1 Environment block
(Environment (ENV_NAME) {

(CTLMode (CTLMODE_NAME) {
(PatternInformation {
(<Pattern | PatternBurst> (pat_or_burst_name) {
(Identifiers (PATTERN_OR_BURST_ENUM)*{
(EventType identifier_event_enum { (1)
.
})*
})*
})*
(<Procedure | Macro> PROCEDURE_OR_MACRO_NAME {
( Purpose ( procedure_or_macro_enum )+ ;) (2)
.
})*
})
(Internal {
(sig_ref_expr {

(DataType (data_type_enum)+ { (3)

(DataRateForProtocol <Average | Maximum | Minimum> INTEGER;)* (4)
(ConstrainedDuringCapture constrain_value;) (5)
})*
})+
})
(External {
(sig_ref_expr {
...
(PadType <PrePad | PostPad | NoPad>;) (6)
(PadValue default_state;) (7)
})+
})
(DomainReferences (CORE_INSTANCE_NAME) * {
(CompressionStructures (COMPRESSION_STRUCT_NAME)+;) (8)

})*

})*
})
6.2 Environment block syntax description
(1) Added new identifier_event_enum options (see 16.1 of IEEE Std 1450.6-2005) called TestReset and
PreviousTestEnd. These values shall be specified for logic tested with CompressionStructures. The labels

or X_REF_ID structures defined for these new identifier_event_enums can be specified in MacroDefs,
Procedures, or Pattern statements.
TestReset: Identifies the locations in the pattern data where simulations from that point forward do not
rely on previous pattern data, assuming the test mode is established and some compare data leveraging the
PreviousTestEnd enum is ignored. If TestReset is not specified, no assumptions can be made for using
PreviousTestEnd.
PreviousTestEnd: Identifies the location in patterns where compares from patterns in the previous
TestReset point end.
(2) Added new procedure_or_macro_enum fields (see 16.1 of IEEE Std 1450.6-2005) called LoadMask,
ObserveSignature, and ResetSignature. LoadMask identifies MacroDefs or Procedures that load mask
data. ObserveSignature identifies MacroDefs or Procedures that are required to observe compressed
representations of captured data. ResetSignature identifies MacroDefs or Procedures that reset the
compressed representations of captured data, thus discarding all the captured responses that have been
captured up to that point. If a MacroDef or Procedure has LoadMask, ObserveSignature, or
ResetSignature as a purpose and does not have any of the purposes: ShiftIn, ShiftOut, Control, Observe,
DoTest, ControlObserve, or DoTestOverlap, then this MacroDef or Procedure can be applied without
disturbing scan cells.
(3) Added new fields to testcontrol_subtype_enum and test_data_subtype_enum (the options for
data_type_enum) called MaskDisable, MaskData, and MaskAll. Use of these new fields is optional (no
default setting is presumed for masking).
MaskDisable: Identifies a place in the design that is not scan enable, test mode, or clock which controls
the selection (mask) logic so, when all MaskDisable are active, it disables selection control (masking) for
scan chains fed by that design location. When inactive, the selection control logic may be masking (or
not).
MaskAll: Identifies a place in the design that is not scan enable, test mode, or clock which controls the
selection (mask) logic so, when all MaskAll are active, it enables selection control (masking) for all scan
chains fed by that design location. When inactive, the selection control logic may be masking or not.
MaskData: Identifies a place in the design that is not scan enable, test mode, or clock which modifies
internal scan chain data streams.
Combinational masking logic specifies these attributes on signal pins. Sequential mask logic specifies
these attributes on scan cells or States in the compression equations. These attributes cannot be placed on
symbolic names.
(4) DataRateForProtocol <Average | Maximum | Minimum> INTEGER;): Added new option to

DataRateForProtocal called Minimum. Minimum INTEGER: The required minimum number of times a
signal changes value per protocol for the patterns that are applied in the current configuration of the design.
Multiple DataRateForProtocol statements are also now allowed.
(5) ConstrainedDuringCapture constrain_value: This statement specifies the required signal values for
Procedures or MacroDefs that have a Capture Purpose specified in the PatternInformation portion of the
Environment block. constrain_value can be D, U, or Z waveform characters (see 18.2 of IEEE Std 1450-
1999).
(6) PadType <PrePad | PostPad | NoPad>: This statement specifies that, if the test data going to the
defined signal pin is not fully specified (not enough values are specified based on size of the MacroDef or
Procedure), it needs to be pre, post, or not padded (extra logic values need to be added to the start, end, or
should not be added). A signal pin of type ScanIn is pre-padded (by default). A signal pin of type ScanOut
is post-padded (by default).

(7) PadValue default_state: When a PadType of PrePad or PostPad is specified, the default_state is in the
PadValue statement defines the padding value. default_state should not be specified for NoPad. Valid
default_state values are the set of Waveform event definitions (see 18.2 of IEEE Std 1450-1999).
(8) Added new DomainReferences type called CompressionStructures that can be included in a
CTLMode block (see 9.2 of IEEE Std 1450.6-2005).
6.3 Environment block example
For examples of this usage, refer to Annex A.
7. Semantics updates
This clause details any semantics that were extended or changed (no syntax changes).
a) All Loops defined in MacroDef or Procedure statements for on-chip scan compression logic imply
a full load/unload sequence.
b) Mapping symbolic signal names to design netlist names (anchor points) are mandatory for each
ScanIn and ScanOut of each ScanStructures block that defines an internal scan chain. Scan
chains used by test logic do not need this mapping. When a scanin/scanout of a ScanStructures
block matches a design netlist pin path name, no anchor point is needed. All inversions that occur on
the ScanStructures side of the anchor point shall be included in the ScanStructures definition and
those on the CompressionStructures side in the CompressionStructures definition.
Anchor points (see Figure 3) can be defined on any port of any netlist gate and are specified by using
the ScanCells and Signals NameMaps defined in 18.3 of IEEE Std 1450.1-2005. Setting anchor
points on state elements can be useful, since these names do not change as much as logic gates do
during design.
When anchor points are defined using NameMaps for ScanStructures defined inside a CoreType
block, the ScanIn and ScanOut name being mapped shall be scoped using the core instance name
followed by a colon (:).
When a CoreType block uses design netlist pin path names to identify internal core anchor points to
the level of design hierarchy of the CoreType block, the CoreInstance CORE_TYPE_NAME can be
mapped to a design netlist instance name using NameMaps. If no NameMap assignment exists for
the CORE_TYPE_NAME or the SI/SO ports in the internal core chains, the CORE_TYPE_NAME defaults
to the design netlist instance name. In the case where the SI/SO ports in the internal core chains are
not mapped (using NameMaps), the core anchor points shall be mapped using the CoreInstance
design netlist instance name (the default) or the mapped name (if mapped via NameMaps), plus a
hierarchical delimiter and the core anchor point design netlist pin path name.
c) All on-chip scan compression logic shall be fully specified from anchor points to input and output
signal pins through State, logic_expression, or MacroDef or Procedure statements.
d) Core non-pseudo ScanIn and ScanOut signal pins cannot be daisy-chained with other scan chains
during core integration when on-chip scan compression logic is defined using those pins.
e) Any core with on-chip scan compression logic shall have fully specified patterns; it shall not rely on
padding assumptions from the Signal block.
f) When Pseudo signals are specified in the MacroDef and Procedure blocks with no waveform, it is
assumed to not be pulsed and to change at time 0. If a pulse is needed on a Pseudo signal, a
Waveforms specification is required.
g) When test logic insertion uses a different tool than pattern generation and a MacroDef or
Procedure has a Control, Observe, or ControlObserve Purpose assigned in the
PatternInformation portion of the Environment block, that Procedure or MacroDef shall not be
modified by the pattern generation tool.

scanenable
clk
in0
ScanStructures Out0
ScanStructures
Out1
in1
Decompressor Internal Compressor
Logic Scan Chains Logic
Out2
ScanStructures
in2
Out3
ScanStructures
in3
Anchor Points on Anchor Points on

First Flop in Each Last Flop in Each
Internal Scan Chain Internal Scan Chain
Figure 3Anchor point placement example
h) If an identifier used in a logic_expression refers to a local identifier (wire or state) and a non-local
identifier, then the local identifier supersedes the non-local identifier.
i) Add a convention to waveform characters 0 and 1 (see 18.2 of IEEE Std 1450-1999) such that they
are equal to logic values 0 and 1 when the signals are used in a logic_expression. When a waveform
is defined for a signal that is used in a logic_expression, at least a 0 and a 1 has to be defined.
j) When the pattern generation tool and test logic insertion come from different vendors, all
Procedures and MacroDefs shall have fully defined PatternInformation purposes to specify the
intent of the Procedures and MacroDefs.

Annex A
(informative)
Examples
This annex shows various examples demonstrating practical usage of OCI. New OCI syntax and semantics
are shown in bold.
A.1 Combinational compression
This circuit has four scan inputs and four scan outputs. The inputs use MUXes to break data dependency; the
outputs use XOR gates, which allow some ability to isolate failures. The same clock (CLK) and scan enable
(SE) go to each flop. For simplicity, each scan chain has only one flop. The anchor points are not specified
using NameMap because the first and last scancell port names are used to define the ScanIn and ScanOut
in the ScanStructures block. Figure A.1 shows the circuit diagram.
clk
CLK
0 Flop1
SI
1 SI Q
S SE
in0
Out0
0 CLK Flop2
SI Q
1
S SE
Out1
in1 CLK Flop3
0
SI Q
1
S SE
Out2
0 CLK Flop4
SI Q
in2 1 SE
S SI Q
Out3
0 CLK Flop5
SI
SI Q
1
S SE
in3 CLK Flop6

0
SI
SI Q
1
S SE
scanenable
Figure A.1Four scan inputs and outputs
This sample CTL defines the compression for this structure.

STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}

Header {
Title CTL to define combinational compression circuitry;
Date 2005
}
Signals {
in0 In {ScanIn;}
in1 In {ScanIn;}
in2 In {ScanIn;}
in3 In {ScanIn;}
clk In; scanenable In;
Out0 Out {ScanOut;}
Out1 Out {ScanOut;}
Out2 Out {ScanOut;}
Out3 Out {ScanOut;}
Flop1/SI Pseudo; Flop2/SI Pseudo; Flop3/SI Pseudo;
Flop4/SI Pseudo; Flop5/SI Pseudo; Flop6/SI Pseudo;
Flop1/Q Pseudo; Flop2/Q Pseudo; Flop3/Q Pseudo;
Flop4/Q Pseudo; Flop5/Q Pseudo; Flop6/Q Pseudo;
}
Timing comp_timing {
WaveformTable time {
Period 100ns;
Waveforms {
in0+in1+in2+in3+clk+scanenable { 01X {0nsD/U/N;}
clk {01P {0ns D/U/D;50ns D/U/U;60ns D/U/D;}
Out0+Out1+Out2+Out3 { lhX {0ns X; '20ns l/h/X; 30ns X;}
}
}
}
}
MacroDefs comp_macros {
comp_load_unload_and_capture {
W time;
C { scanenable = 1;}
X Previous_End_Point;
Shift { V {in0=#; in1=#; in2=#; in3=#; clk=P; Out0=#; Out1=#;
Out2=#; Out3= #;}}
}
comp_capture {
W time;
V {clk=#; in0=#; in1=#; in2=#; in3=#; Out0=#; Out1=#; Out2=#;
Out3=#;}
}
}
ScanStructures comp_internal_chains {
ScanChain intchain1 {ScanCells Flop1; ScanLength 1; ScanIn Flop1/SI;
ScanOut Flop1/Q; ScanMasterClock clk;}


}
CompressionStructures my_compression { // can have multiple
// choices are Decompressor, Compressor .. can have multiple
Vendor Synopsys { // vendor syntax optional
}
Flop1/SI in0?in2:in1;
}
Vendor Synopsys {
// vendor syntax optional
}
Out0 Flop1/Q ^ Flop2/Q ^ Flop3/Q;
}
}
Environment combcompression {
CTLMode comp_atpg {
DomainReferences {
Timing comp_timing;
Macrodefs comp_macros;
ScanStructures comp_internal_chains;
CompressionStructures my_compression;
}
Internal {
in0+in1+in2+in3 { DataType TestData ScanDataIn; }
scanenable {DataType TestControl ScanEnable
{ ActiveState U; AssumedInitialState D;}}
clk {DataType CaptureClock ScanMasterClock
MasterClock {ActiveState U; AssumedInitialState D;}}
Out0+Out1+Out2+Out3 {DataType TestData ScanDataOut;}
}
PatternInformation {
Macro comp_load_unload_and_capture {Purpose DoTestOverlap;
Identifiers { EventType PreviousTestEnd
{Xref Previous_End_Point{Complete;End;}}}}
Macro comp_capture {Purpose Capture;}
}
}
}

A.2 LFSR-MUX
This example uses a reseeding LFSR decompressor and a selectable MUX output compressor. A shift chain
updates both during the capture clock. The load signal is defined as a Pseudo and presumed to change value
at time 0. Figure A.2 shows the circuit diagram.
c lk
CLK Flop1
c o_1
D Q
SI Q
C LK
lfsrFlop 6 SE 0 Out0
SI Q
CLK
lfs rloadFlop 6
SE
1
0 D Q CLK Flop2 1
Q
CLK
SI Q
SI
CLK
lfs rloadFlop 5 lfs rFlop5

SE
SE
1
0
SI Q
CLK Flop3
CLK
lfs rloadFlop 4
SE
SI Q
D Q
CLK
lf srFlop4 0
SE Out1
SI Q
CLK
lfs rloadFlop 3
SE
CLK Flop4
1
0
1
SI Q
D Q
CLK
SI Q
lfs rloadFlop 2
CLK
lfs rFlop3 SE
SE
CLK Flop5
1
0
lfs rloadFlop 1
SI Q
Q
CLK
SI 0
SE
D Q
C LK
lfsrFlop 2 SE Out2
c i_1
CLK Flop6
1
1
0
SI Q
SE
D Q
CLK
c_reset lf srFlop1
1
0
SelFlop1 SelFlop2 SelFlop3

Q
Q
Counter
Q
load
CLK
CLK
C LK
D
Testcloc k
D
D
LoadSel LoadSel LoadSel

Flop1 Flop2 F lop3
CLK CLK CLK
ci_2 co_2
SI Q SI Q SI Q
SE SE SE
sc anenable
Figure A.2LFSR with MUX decompressor
This sample CTL defines the compression for this structure after test logic insertion. Because the TestReset
and PreviousTestEnd are defined to pattern generation, no modifications to these CTL blocks are needed
after pattern generation and the pattern generation tool shall assume no state can be kept between captures.
STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}
Header {
Title CTL for reseeding LFSR decompressor and mux compressor;
Date 2006
}
Signals {
Testclock In;
ci_1 In {ScanIn;}
ci_2 In {ScanIn;}

co_1 Out {ScanOut;}

co_2 Out; {ScanOut;}
Out0 Out {ScanOut;}
Out1 Out {ScanOut;}
Out2 Out {ScanOut;}
load Pseudo {DefaultState D;}
si1 Pseudo; si2 Pseudo; si3 Pseudo; si4 Pseudo; si5 Pseudo;
si6 Pseudo;
so1 Pseudo; so2 Pseudo; so3 Pseudo; so4 Pseudo; so5 Pseudo;
so6 Pseudo;
c_reset In;
}
Period 100ns;
Waveforms {
ci_1+ci_2+clk+scanenable+c_reset {
01PX { 0ns D/U/D/N; 30ns D/U/U/N; 40ns D/U/D/N;}
}
Testclock {
01PX {0ns D; 60ns U; 70ns D;}
}
co_1+co_2+Out0+Out1+Out2 {
lhX {0ns X; 10ns l/h/X; 20ns X;}
}
}
}
}
comp_load_unload {
W time;
V {ci_1 = #; ci_2 = #; Testclock=P; clk=0; Out0=#; Out1=#; Out2=#;
co_1=#; co_2=#; load=1;}
X ResetPoint;
Shift { V {ci_1=#; ci_2=#; Testclock=P; clk=P; Out0=#; Out1=#;
Out2=#; co_1=#; co_2=#; load = 0;}}
}
comp_capture {
W time;
X PreviousEndPoint;
C { scanenable = 0; Testclock = 0; ci_1=0; ci_2=0; load = 1;}
V {clk=#; Out0=#; Out1=#; Out2=#; co_1=X; co_2=X;}
}
init_test {
W time;
V {clk=0; ci_1=0; ci_2=0; Testclock=0; Out0=X; Out1=X; Out2=X;
co_1=X; co_2=X; load=X; c_reset=0; scanenable = 0;}
co_1=X; co_2=X; load=0; c_reset=1; scanenable = 0;}
co_1=X; co_2=X; load=0; c_reset=0; scanenable = 0;}

}
ScanStructures selector_load_chains {
ScanChain maskffs { ScanCells LoadSelFlop1 LoadSelFlop2 LoadSelFlop3;
ScanLength 3; ScanMasterClock testclock;
ScanIn ci_2;ScanOut co_2; ScanEnable scanenable;
ScanInversion 0; }
}
ScanStructures lfsr_load_chains {
ScanChain load_chains {ScanCells lfsrloadFlop1 lfsrloadFlop2
lfsrloadFlop3 lfsrloadFlop4 lfsrloadFlop5
lfsrloadFlop6;
ScanLength 6; ScanIn ci_1; ScanOut co_1;
ScanMasterClock testclock; ScanInversion 0;
ScanEnable scanenable}
}
ScanChain intchain1 {ScanCells Flop1; ScanLength 1; ScanIn si1;
ScanOut so1; ScanMasterClock clk;
}
CompressionStructures comp_decompressor {
Vendor Synopsys;
State SelFlop1 { Data LoadSelFlop1; Clock Testclock & load;}
Out0 SelFlop1?so6:so5;
Out1 SelfFop2?so4:so3;
Out2 SelFlop3?so2:so1;
}
Vendor Synopsys;
State lfsrFlop1 { Data load?lfsrloadFlop1:lfsrFlop1 ^ lfsrFlop6;
Clock Testclock;}
State lfsrFlop2 { Data load?lfsrloadFlop2:lfsrFlop1;
Clock Testclock;}
Clock Testclock;}


Clock Testclock;}
Clock Testclock;}
State lfsrFlop6 { Dataload?lfsrloadFlop6:lfsrFlop5;
Clock Testclock;}
si1 lfsrflop1;
si2 lfsrflop2;
si3 lfsrflop3;
si4 lfsrflop4;
si5 lfsrflop5;
si6 lfsrflop6;
}
}
Environment compression {
NameMaps anchor_points {
Signals {
si1 Flop1[SI]; so1 Flop1[Q];
si2 Flop2[SI]; so2 Flop2[Q};
}
}
CTLMode comp_atpg {
DomainReferences {
Timing comp_timing;
ScanStructures comp_internal_chains selector_load_chains
lfsr_load_chains;
CompStructures comp_decompressor;
}
Internal {
ci_1 {DataType TestData ScanDataIn { DataRateForProtocol
Minimum 6; DataRateForProtocol Maximum 6;}}
ci_2 {DataType TestData ScanDataIn { DataRateForProtocol
Minimum 3;}}
scanenable {DataType TestControl ScanEnable
{ ActiveState U; AssumedInitialState D;}}
clk+Testclock {DataType CaptureClock ScanMasterClock
MasterClock {ActiveState U; AssumedInitialState D;}}
Out0+Out1+Out2 {DataType TestData ScanDataOut;
DataRateForProtocol Average 1;}
SelFlop1 + SelFlop2 + SelFlop3 {DataType TestData MaskData;}
co_1 {DataType TestData ScanDataOut { DataRateForProtocol
Minimum 6; DataRateForProtocol Maximum 6;}}
co_2 {DataType TestData ScanDataOut { DataRateForProtocol
Minimum 3;}}
c_reset {DataType Reset {ActiveState U; AssumedInitialState D;}}
}

Macro comp_load_unload {Purpose ControlObserve;
Identifiers { EventType TestReset {Xref ResetPoint
{Complete;Begin;}}}}
Macro comp_capture { Purpose Capture;
Identifiers {EventType PreviousTestEnd
{ Xref PreviousEndPoint{Complete;Begin;}}}}
Macro init_test {Purpose ModeControl;
UseByPattern EstablishMode;}
}
}
}
A.3 EDT-like compression circuitry
Figure A.3 and Figure A.4 show the decompressor and compactor, respectively, for this example.
phase shifter
int_si[0]
chain1
int_si[1]
chain2
edt_channels_in1
LFSM
(decompressor
edt_channels_in2 ring generator)
int_si[11]
chain12
edt_reset
mask_in
edt_clock
(to compactor)
Figure A.3Decompressor

mask gates space compactors
chain1
chain2
edt_channels_out1
chain3
edt_channels_out2
chain12
mask decoder
edt_update
mask_hold register
mask_in (from decompressor)

mask_shift register
edt_clock
Figure A.4Compactor (including mask logic)
// OCI example based on Embedded Deterministic Test (EDT)-like

// compression circuitry.
//
// EDT compression is covered by several U.S. and International patents
// held by Mentor Graphics Corporation. They include coverage of the
// compression method, the decompressor, and space compactors with
// masking.
//
// New OCI syntax is shown in bold.
//
// For simplicity, test signals are not shared or internally generated.
//
// Terminology:
// - Chains: Refers to internal scan chains.
// - Channels: Refers to external compressed "virtual" scan chains.
//
// Design characteristics:
// - 2 compressed scan channels
// - 12 internal scan chains

// - 8 Mux-D scan cells per scan chain

// - Design functional pins: fin[2:0], fout[1:0], clk
STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}
Header {
Title "CTL describing EDT-like compression circuitry";
Date "Mon Feb 27 15:53:58 PST 2006";
}
Signals {
// functional signals
//
clk In;
fin[2..0] In;
fout[1..0] Out;
// test signals
//
edt_clock In;
edt_reset In;
edt_update In;
scan_en In;
edt_channels_in1 In; // ScanIn, scan length defined in ScanGroups
edt_channels_out1 Out; // ScanOut, scan length defined in ScanGroups
// internal signals
//
int_si[0..11] Pseudo;
int_so[0..11] Pseudo;
mask_in Pseudo;
}
SignalGroups {
// Lengths of compressed scan input and output signals are the
// same.
// Patterns generated are padded.
// Specifying "12" below is redundant since this is specified
// in DataRateForProtocol.
_si_ = 'edt_channels_in1 + edt_channels_in2' { ScanIn 12; }
_so_ = 'edt_channels_out1 + edt_channels_out2' { ScanOut 12; }
_clks_ = 'clk + edt_clock';

_pi_ = '_si_ + edt_reset + edt_update + scan_en + fin[2..0]';
_po_ = '_so_ + fout[1..0]';
}

Period '100ns';
Waveforms {
_pi_ {01X { '0ns' D/U/N; }}
_clks_ {0P { '0ns' D; '40ns' D/U; '50ns' D; }}
_po_ {LHXZ { '0ns' X; '10ns' l/h/X/t; '40ns' X; }}
}
}
}
load_unload_and_update_masks {
W time;
V { clk = 0; edt_clock = P; edt_update = 1; edt_reset = 1;
scan_en = 1; }
C { edt_update = 0; edt_reset = 0; scan_en = 1; }
Shift { V { clk = P; edt_clock = P; _si_ = #; _so_ = #; } }
}
combinational_pattern {
Macro load_unload_and_update_masks { _si_ = #; _so_ = #; }
W time;
V { _pi_ = %; _clks_ = %; _po_ = %; }
}
}
ScanChain chain1 { ScanCells chain1_cells[7..0];
ScanLength 8;
ScanIn int_si[0];
ScanOut int_so[0];
ScanMasterClock clk; }
ScanLength 8;
ScanIn int_si[1];
ScanOut int_so[1];
ScanLength 8;
ScanIn int_si[2];
ScanOut int_so[2];
ScanLength 8;
ScanIn int_si[3];
ScanOut int_so[3];
ScanLength 8;
ScanIn int_si[4];
ScanOut int_so[4];
ScanLength 8;

ScanIn int_si[5];
ScanOut int_so[5];
ScanLength 8;
ScanIn int_si[6];
ScanOut int_so[6];
ScanLength 8;
ScanIn int_si[7];
ScanOut int_so[7];
ScanLength 8;
ScanIn int_si[8];
ScanOut int_so[8];
ScanLength 8;
ScanIn int_si[9];
ScanOut int_so[9];
ScanLength 8;
ScanIn int_si[10];
ScanOut int_so[10];
ScanLength 8;
ScanIn int_si[11];
ScanOut int_so[11];
}
CompressionStructures comp_compstructures {
Decompressor decompressor {
Vendor MentorGraphics {
// Vendor-specific information. Ignored by other vendors.
ip_version = "1";
n_channels = "2";

}
// LFSM (decompressor ring generator)
//
State lfsm[0] { Data '~edt_reset & (lfsm[1])';
Clock edt_clock; }
State lfsm[1] { Data '~edt_reset & (lfsm[2] ^ edt_channels_in2)';
Clock edt_clock; }
Clock edt_clock; }
State lfsm[3] { Data '~edt_reset &
(lfsm[4] ^ lfsm[3] ^ edt_channels_in2)';
Clock edt_clock; }

State lfsm[4] { Data '~edt_reset & (lfsm[5] ^ lfsm[2] ^ lfsm[3])';

Clock edt_clock; }
Clock edt_clock; }
State lfsm[6] { Data '~edt_reset & (lfsm[7] ^ lfsm[1])';
Clock edt_clock; }
Clock edt_clock; }
// phase shifter
//
int_si[0] 'lfsm[0] ^ lfsm[3] ^ lfsm[4]';
mask_in 'lfsm[1] ^ lfsm[2] ^ lfsm[3]';
}
Compressor compressor {
Vendor MentorGraphics;
// mask shift register

//
State mask_shift[5] { Data mask_in; Clock edt_clock; }
State mask_shift[4] { Data mask_shift[5]; Clock edt_clock; }
// mask hold register

//
State mask_hold[0] { Data 'edt_update ? mask_shift[0] :
mask_hold[0]';
Clock edt_clock; }
mask_hold[1]';
Clock edt_clock; }
mask_hold[2]';
Clock edt_clock; }
mask_hold[3]';
Clock edt_clock; }


mask_hold[4]';
Clock edt_clock; }
mask_hold[5]';
Clock edt_clock; }
// mask decoder
//
// Note: 'A function of mask_hold[0..5]' is a combinational
// expression whose inputs are connected to mask_hold[0..5].
//
Wire channel1_chain_masks[0] 'A function of mask_hold[0..5]';
// space compactor (XOR trees)

//
edt_channels_out1 = '(int_so[0] & channel1_chain_masks[0]) ^
(int_so[1] & channel1_chain_masks[1]) ^
(int_so[5] & channel1_chain_masks[5])';
}
}
Environment edt_compression {
CTLMode comp_atpg {
DomainReferences {
Timing comp_timing;
MacroDefs comp_macros;
CompressionStructures comp_compstructures;
}
Internal {

_si_ { DataType TestData ScanDataIn { DataRateForProtocol

Minimum 12; } }
_so_ { DataType TestData ScanDataOut { DataRateForProtocol
Minimum 12; } }
scan_en { DataType TestControl ScanEnable
{ ActiveState ForceUp; AssumedInitialState ForceDown; } }
clk { DataType TestControl ScanMasterClock MasterClock CaptureClock
{ ActiveState U; AssumedInitialState D; } }
edt_clock { DataType TestControl ScanMasterClock MasterClock
{ ActiveState U; AssumedInitialState D;
ConstrainedDuringCapture D;} }
edt_update { DataType TestControl
edt_reset { DataType TestControl
}
// Specify padding rules for compressed scan channels

//
External {
_si_ { PadType PrePad; PadValue D; }
_so_ { PadType PostPad; PadValue X; }
}
// Define anchor points for internal scan inputs and outputs

//
NameMaps scan_chain_anchor_points {
Signals {
int_si[0..11] edt.scan_in[0..11];
int_so[0..11] edt.scan_out[0..11];
}
}
Macro load_unload_and_update_masks { Purpose ControlObserve
LoadMask; }
Macro combinational_pattern { Purpose DoTestOverlap
LoadMask; }
PatternExec scanexec;
}
}
}
PatternExec scanexec {
Timing comb_timing;
PatternBurst scanpats;
}
PatternBurst scanpats {
Purpose Scan;
Identifiers {
EventType TestPatternUnit {
Label pattern { Prefix; Begin; }
}

PatList {
pattern_0 { Protocol Macro "combinational_pattern"; }
}
}
Pattern pattern_0 {
Ann {* Pattern:0 *}
"pattern 0": P {
edt_channels_in1 = 000000110000;
edt_channels_out1 = XXXXXXXXXXXX;
_pi_ = XXXX0XXX;
_clks_ = 00;
_po_ = XXXX;
}
Ann {* Pattern:1 *}
"pattern 1": P {
edt_channels_out1 = LLLLHHHLXXXX;
edt_channels_out2 = LLLHLHHLXXXX;
_pi_ = XXXX0XXX;
_clks_ = 00;
_po_ = XXXX;
}
}

A.4 EDT-like compression circuitry with two-stage compactor
Figure A.5 and Figure A.6 show the decompressor and compactor, respectively, for this example.
phase shifter
int_si[0]
chain 1
int_si[1]
chain 2
edt_channels_in1
edt_channels_in2 LFSM
(decompressor
ring generator)
int_si[11]
chain 12
edt_reset
edt_fast_clock
Figure A.5Decompressor

mask gates 1 space compactors 1 mask gates 2 space compactors 2
chain1
Overdrive serial shift register (8 bits)

chain2
edt_channels_out1
chain3
edt_channels_out2
chain12
clk edt_fast_clock
mask decoder
shift timing
clk
edt_update edt_fast_clock
mask_hold register
edt_slow_clock
edt_slow_clock
edt_channels_in1
edt_channels_in2 mask_shift register
Figure A.6Compactor (including mask logic and shift timing)
// OCI example based on Embedded Deterministic Test (EDT)-like

// compression circuitry with two-stage compactor.
//
// EDT compression is covered by several U.S. and International patents
// held by Mentor Graphics Corporation. They include coverage of the
// compression method, the decompressor, and space compactors with
// masking.
//
// New OCI syntax is shown in bold.
//
// For simplicity, test signals are not shared or internally generated.
//
// Terminology:
// - Chains: Refers to internal scan chains.
// - Channels: Refers to external compressed "virtual" scan chains.
//
// Design characteristics:
// - 2 compressed scan channels
// - 12 internal scan chains
// - 64 Mux-D scan cells per scan chain
// - 8x ratio between internal and external shift rates

// - Design functional pins: fin[2:0], fout[1:0], clk
STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}
Header {
Title "CTL describing EDT-like compression circuitry with two-stage
compactor";
Date "Mon Jan 24 20:23:05 PST 2008";
}
Signals {
// functional signals
//
clk In;
fin[2..0] In;
fout[1..0] Out;
// test signals
//
edt_slow_clock In;
edt_fast_clock In;
edt_reset In;
edt_update In;
scan_en In;
// internal signals
//
}
SignalGroups {
// Lengths of compressed scan input and output signals are the same.
// Patterns generated are padded.
// Specifying "12" below is redundant since this is specified
// in DataRateForProtocol.
_si_ = 'edt_channels_in1 + edt_channels_in2' { ScanIn 12; }
_so_ = 'edt_channels_out1 + edt_channels_out2' { ScanOut 12; }
_clks_ = ' edt_fast_clock + edt_slow_clock + clk';
_pi_ = '_si_ + edt_reset + edt_update + scan_en + fin[2..0]';
_po_ = '_so_ + fout[1..0]';

Period '100ns';
Waveforms {
_pi_ {01X { '0ns' D/U/N; }}
_clks_ {0P { '0ns' D; '40ns' D/U; '50ns' D; }}
_po_ {LHXZ { '0ns' X; '10ns' l/h/X/t; '40ns' X; }}
}
}
}
W time;
V { clk = 0; edt_fast_clock = P; edt_slow_clock = P;}
Shift {
V { clk = P; edt_fast_clock = P; edt_slow_clock = P;
_si_ = #; _so_ = #; }
V { clk = P; edt_fast_clock = P; edt_slow_clock = 0; }
}
}
Macro load_unload_and_update_masks { _si_ = #; _so_ = #; }
W time;
C { edt_fast_clock = 0; edt_slow_clock = 0; }
V { _pi_ = #; clk = #; _po_ = #; }
}
}
ScanLength 64;
ScanIn int_si[0];
ScanOut int_so[0];
ScanLength 64;
ScanIn int_si[1];
ScanOut int_so[1];

ScanLength 64;
ScanIn int_si[2];
ScanOut int_so[2];
ScanLength 64;
ScanIn int_si[3];
ScanOut int_so[3];
ScanLength 64;
ScanIn int_si[4];
ScanOut int_so[4];
ScanLength 64;
ScanIn int_si[5];
ScanOut int_so[5];
ScanLength 64;
ScanIn int_si[6];
ScanOut int_so[6];
ScanLength 64;
ScanIn int_si[7];
ScanOut int_so[7];
ScanLength 64;
ScanIn int_si[8];
ScanOut int_so[8];
ScanLength 64;
ScanIn int_si[9];
ScanOut int_so[9];
ScanLength 64;
ScanIn int_si[10];
ScanOut int_so[10];
ScanLength 64;
ScanIn int_si[11];
ScanOut int_so[11];
}

// Vendor-specific information. Ignored by other vendors.

ip_version = "1";
n_channels = "2";

}

//
Clock edt_fast_clock; }
(lfsm[5] ^ lfsm[2] ^ lfsm[3])';
State lfsm[6] { Data '~edt_reset & (lfsm[7] ^ lfsm[1])';
// phase shifter
//
}

//
State mask_shift[5] { Data edt_channels_in1; Clock edt_slow_clock; }
State mask_shift[4] { Data mask_shift[5]; Clock edt_slow_clock; }
State mask_shift[2] { Data edt_channels_in2; Clock edt_slow_clock; }


//
State mask_hold[0] { Data 'edt_update ?
mask_shift[0] : mask_hold[0]';
Clock edt_slow_clock; }
// mask decoder 1
//
//
// space compactor 1 (XOR trees)

//
Wire space_compactor_out1 = '(int_so[0] & channel1_chain_masks[0]) ^

State overdrive_reg[0] { Data space_compactor_out1;

State overdrive_reg[1] { Data overdrive_reg[0];
// mask decoder 2
//
// space compactor 2 (XOR trees)

//
edt_channels_out1 = '(overdrive_reg[0] & channel2_chain_masks[0]) ^
(overdrive_reg[1] & channel2_chain_masks[1]) ^
(overdrive_reg[3] & channel2_chain_masks[3])';
edt_channels_out2 = '(overdrive_reg[4] & channel2_chain_masks[4]) ^

(overdrive_reg[7] & channel2_chain_masks[7])';
}
}
Environment edt_compression {
CTLMode comp_atpg {
DomainReferences {
Timing comp_timing;
MacroDefs comp_macros;
CompressionStructures comp_compstructures;

Internal {
_si_ { DataType TestData ScanDataIn { DataRateForProtocol Minimum
12; } }
_so_ { DataType TestData ScanDataOut { DataRateForProtocol Minimum
12; } }
{ ActiveState ForceUp; AssumedInitialState ForceDown; } }
clk { DataType TestControl ScanMasterClock MasterClock CaptureClock
edt_fast_clock { DataType TestControl ScanMasterClock MasterClock
edt_slow_clock { DataType TestControl ScanMasterClock MasterClock
edt_update { DataType TestControl
edt_reset { DataType TestControl
}
// Specify padding rules for compressed scan channels

//
External {
_si_ { PadType PrePad; PadValue D; }
_so_ { PadType PostPad; PadValue X; }
}
// Define anchor points for internal scan inputs and outputs

//
Signals {
int_si[0..11] edt.scan_in[0..11];
int_so[0..11] edt.scan_out[0..11];
}
}
Macro load_unload_and_update_masks { Purpose ControlObserve
LoadMask; }
Macro combinational_pattern { Purpose DoTestOverlap
LoadMask; }
PatternExec scanexec;
}
}
}
PatternExec scanexec {
Timing comb_timing;
PatternBurst scanpats;

PatternBurst scanpats {
Purpose Scan;
Identifiers {
EventType TestPatternUnit {
Label pattern { Prefix; Begin; }
}
}
PatList {
pattern_0 { Protocol Macro "combinational_pattern"; }
}
}
Pattern pattern_0 {
Ann {* Pattern:0 *}
"pattern 0": P {
_pi_ = XXXX0XXX;
clk = P;
_po_ = XXXX;
}
Ann {* Pattern:1 *}
"pattern 1": P {
edt_channels_out1 = XLLLHHHLHXXX;
edt_channels_out2 = XLLHLHHLLXXX;
_pi_ = XXXX0XXX;
clk = P;
_po_ = XXXX;
}

A.5 Two core compression
This System on Chip (SoC) comprises of two cores. Each core has its own compression logic. The system
integrator brings the cores together in a top SoC called TOP. The two cores used are combinational core
(from A.1) and EDT-like core (from A.3) and each core has independent on-chip scan compressor and
decompressor logic. The ToP SoC is tested using one test mode with both compression schemes being used
in parallel. No test patterns are being remapped for the cores.
Combinational core: This circuit has four scan inputs and four scan outputs. The inputs use MUXes to break
data dependency; the outputs use XOR gates, which allow some ability to isolate failures. The same clock
(clk) and scan enable (scanenable) go to each flop. For simplicity, each scan chain has only one flop.
Figure A.7 shows the circuit diagram.
EDT-like core: This core requires an edt_clock. There are two scan inputs called edt_channels_in
and two scan outputs called edt_channels_out. The core has 12 internal scan chains with 8 Mux-D
scan cells per scan chain.
TOP
tk_in1 edt_channels_in1
Core: EDT
tk_in2 edt_channels_in2
edt_channels_out1 tk_out1
tk_reset edt_reset
edt_channels_out2 tk_out2
tk_update edt_update
tk_clock edt_clock tk_fout[1..0]
fout[1..0]
tk_fin[2..0] fin[2..0]
scan_en scan_en
clk clk
in0
in0 Core: Comb
out0
out0
in1
in1
out1 out1
in2
in2
out2 out2
in3
in3
out3 out3
scanenable
clk
Figure A.7Compressing two cores

This sample CTL defines the compression for the cores.

STIL 1.0 {
Design 2005;
CTL 2005;
Compression 2006;
}
Header {
Title CTL to define multiple core compression circuitry;
Date 2005
}
Signals {
//All EDT signals to top-level
tk_fin[2..0] In;
tk_fout[1..0] Out;
tk_clock In;
tk_reset In;
tk_update In;
scan_en In;
clk In;
tk_in1 In;
tk_in2 In;
tk_out1 Out;
tk_out2 Out;
//All Comb signals to top-level
in0 In {ScanIn;}
in1 In {ScanIn;}
in2 In {ScanIn;}
in3 In {ScanIn;}
out0 Out {ScanOut;}
out1 Out {ScanOut;}
out2 Out {ScanOut;}
out3 Out {ScanOut;}
}
// Top level signal group names, which are referenced in the

// Macros and Environment blocks to describe different characteristics.
SignalGroups {
_sitk_ = 'tk_in1 + tk_in2' { ScanIn 12; }
_sotk_ = 'tk_out1 + tk_out2' { ScanOut 12; }
_somx_ = 'out0 + out1 + out2 + out3';
_simx_ = 'in0 + in1 + in2 + in3';
_topclks_ = 'tk_clock + clk';
_pitk_ = '_sitk_ + tk_reset + tk_update + scan_en +tk_fin[2..0]';
_potk_ = '_sotk_ + tk_fout[1..0]';
}
CoreType TK {
// All the example #3 syntax of the TK core is defined here except the
// Environment, Timing, and MacroDefs blocks. Compression equations are
// written to the boundary of the core. The connection to the top level
// is taken from the environment IsConnected statements.
Signals {
clk In;
fin[2..0] In;
fout[1..0] Out;

edt_clock In;
edt_reset In;
edt_update In;
scan_en In;
edt_channels_in1 In;
edt_channels_in2 In;
edt_channels_out1 Out;
edt_channels_out2 Out;
mask_in Pseudo;
} //Signals
SignalGroups {
_si_ = 'edt_channels_in1 + edt_channels_in2;
_so_ = 'edt_channels_out1 + edt_channels_out2';
_clks_ = 'edt_clock + clk';
_pi_ = '_si_ + edt_reset + edt_update + scan_en+fin[2..0]';
_po_ = '_so_ + fout[1..0]';
}
ScanStructures tk_internal_chains {
ScanLength 8;
ScanIn int_si[0];
ScanOut int_so[0];
ScanLength 8;
ScanIn int_si[1];
ScanOut int_so[1];
ScanLength 8;
ScanIn int_si[2];
ScanOut int_so[2];
ScanLength 8;
ScanIn int_si[3];
ScanOut int_so[3];
ScanLength 8;
ScanIn int_si[4];
ScanOut int_so[4];
ScanLength 8;
ScanIn int_si[5];
ScanOut int_so[5];


ScanLength 8;
ScanIn int_si[6];
ScanOut int_so[6];
ScanLength 8;
ScanIn int_si[7];
ScanOut int_so[7];
ScanLength 8;
ScanIn int_si[8];
ScanOut int_so[8];
ScanLength 8;
ScanIn int_si[9];
ScanOut int_so[9];
ScanLength 8;
ScanIn int_si[10];
ScanOut int_so[10];
ScanLength 8;
ScanIn int_si[11];
ScanOut int_so[11];
}
// The equations for the structures used for compression within the core.
// The equations are written to the boundary of the core which means to
// the signals defined within this CoreType. If Variables are used in the
// original equations for TK they need to be either defined as Pseudo
// Signals within this core, or Variables need to be defined outside the
// CoreType in the CTL.
// Vendor-specific information.
ip_version = "1";
n_channels = "2";

}
State lfsm[0] {
Data '~edt_reset & (lfsm[1])';
Clock edt_clock; }
State lfsm[1] {
Data '~edt_reset & (lfsm[2]êdt_channels_in2)';
Clock edt_clock; }

State lfsm[2] {
Data '~edt_reset & (lfsm[3])';
Clock edt_clock; }
State lfsm[3] {
Data '~edt_reset&(lfsm[4]^lfsm[3]êdt_channels_in2)';
Clock edt_clock; }
State lfsm[4] {
Data '~edt_reset & (lfsm[5] ^ lfsm[2] ^ lfsm[3])';
Clock edt_clock; }
State lfsm[5] {
Data '~edt_reset&(lfsm[6]^lfsm[2]êdt_channels_in1)';
Clock edt_clock; }
State lfsm[6] {
Data '~edt_reset & (lfsm[7] ^ lfsm[1])';
Clock edt_clock; }
State lfsm[7] {
Data '~edt_reset & (lfsm[0]êdt_channels_in1)';
Clock edt_clock; }
// phase shifter
//
mask_in 'lfsm[1] ^ lfsm[2] ^ lfsm[3]';
}
//
State mask_shift[5] { Data mask_in; Clock edt_clock; }
//
State mask_hold[0] { Data 'edt_update ? mask_shift[0]
: mask_hold[0]';
Clock edt_clock; }
: mask_hold[1]';
Clock edt_clock; }


: mask_hold[2]';
Clock edt_clock; }
: mask_hold[3]';
Clock edt_clock; }
: mask_hold[4]';
Clock edt_clock; }
: mask_hold[5]';
Clock edt_clock; }
// mask decoder
//
//
// space compactor (XOR trees)
//
} //compressor
} //CompressionStructures
} // CoreTypeTK
// Instantiation of EDT core. As a result of this instantiation all

// signal names in the core when referenced outside the core would be
// coretk:signalname. Similarly states and scan_cell names all take on
// this naming convention. Thus if the same core-type is instantiated
// twice there would be no clash in the names within each of the cores.
CoreInstance TK { coretk; }

// The hierarchy that uses the combinational compression scheme is

// defined here. Just like the other core, all the equations for
// compression are written to the boundary of the core itself and
// are copied from the original CTL description of the design.
CoreType SY {
Signals {
in0 In {ScanIn;}
in1 In {ScanIn;}
in2 In {ScanIn;}
in3 In {ScanIn;}
out0 Out {ScanOut;}
out1 Out {ScanOut;}
out2 Out {ScanOut;}
out3 Out {ScanOut;}
Flop1/SI Pseudo;
Flop2/SI Pseudo;
Flop3/SI Pseudo;
Flop4/SI Pseudo;
Flop5/SI Pseudo;
Flop6/SI Pseudo;
Flop1/Q Pseudo;
Flop2/Q Pseudo;
Flop3/Q Pseudo;
Flop4/Q Pseudo;
Flop5/Q Pseudo;
Flop6/Q Pseudo;
}
ScanChain intchain1 {
ScanCells Flop1; ScanLength 1; ScanIn Flop1/SI;
}
CompressionStructures my_compression {
Vendor Synopsys {
}

}
Vendor Synopsys {// vendor syntax optional
}
out0 Flop1/Q ^ Flop2/Q ^ Flop3/Q;
}
}
} // CoreType
// Instantiation of core with combinational compression. Names of the

// pseudo signals now become coresy:Flop1/SI. Since Flop1/SI
// represents an actual net name of the original design, coresy would
// need to be the exact name of the hierarchy in the design to maintain
// the link to the anchor points of the scan chains.
CoreInstance SY { coresy; }
// The following reflect the timing of signals at the top level of the
// design. Typically one timing block would be written for both cores if
// the cores are compatible and the patterns are run simultaneously.
Timing {
Period '100ns';
Waveforms {
_pitk_ {01X { '0ns' D/U/N; }}
_topclks_ {0P { '0ns' D; '40ns' D/U; '50ns' D; }}
_potk_ {LHXZ { '0ns' X; '10ns' l/h/X/t; '40ns' X; }}
_simx_{ 01X {0ns D/U/N;}}
_somx_ {lhX {0ns X;'20ns l/h/X;30ns X;}}
}
}
}
// Macros are written to the top level signals. The LHS of the
// assignments are defined in the Signals{} of the current CTL. The RHS
// of the equations represent variables or signal-names at the
// core-level. MacroDefs are same as the ones in the CTL of the core.
MacroDefs both {
W time;
V { clk = 0; tk_clock = P; tk_update = 1; tk_reset = 1;
scan_en = 1; }
C { tk_update = 0; tk_reset = 0; scan_en = 1; }
X Previous_End_Point;

Shift { V { clk = P; tk_clock = P; _sitk_ = #; _sotk_ = #;

_simx_= #; _somx_ = #;} }
}
Macro load_unload_and_update_masks { _sitk_ = #; _sotk_ = #;
_simx_ = #;_somx_ = #;}
W time;
V { _pitk_ = %; _topclks_ = %; _potk_ = %;_simx_ = %;_somx_ =%; }
}
} //MacroDefs TK1
Environment {
CTLMode both1 {
DomainReferences {
MacroDefs both;
ScanStructures coresy:comp_internal_ch coretk:tk_internal_chains;
CompressionStructures coresy:my_compression,
coretk:comp_compstructures;
}
// Information on the top level signals on how they are used.

Internal {
//EDT core (coretk) signals

_sitk_ { DataType TestData ScanDataIn
{ DataRateForProtocol Minimum 12; }
IsConnected In {
CoreSignal coretk:_si_;
}
}
_sotk_ { DataType TestData ScanDataOut {
DataRateForProtocol Minimum 12; }
IsConnected Out {
CoreSignal coretk:_so_;
}
}
{ ActiveState ForceUp; AssumedInitialState ForceDown; }
IsConnected Out {
CoreSignal coretk:scan_en+ coresy:scanenable;
}
}
clk {DataType TestControl ScanMasterClock MasterClock
CaptureClock {ActiveState U; AssumedInitialState D;}
IsConnected In {
CoreSignal coretk:clk + coresy:clk;
}
}
tk_clock { DataType TestControl ScanMasterClock
MasterClock { ActiveState U; AssumedInitialState D;
ConstrainedDuringCapture D;}
IsConnected In {

CoreSignal coretk:edt_clock;
}
}
tk_update { DataType TestControl

{ ActiveState U; AssumedInitialState D; }
IsConnected In {
CoreSignal coretk:edt_update;
}
}
tk_reset { DataType TestControl
{ ActiveState U; AssumedInitialState D; }
IsConnected In {
CoreSignal coretk:edt_reset;
}
}
// specifying tk_fin and tk_fout is not required since we

// are not remapping existing patterns.
tk_fin[2..0] {IsConnected In {
CoreSignal coretk:fin[2..0]; }}
tk_fout[1..0] {IsConnected Out {
CoreSignal coretk:fout[1..0];}}
//Combination core (coresy) signals

in0+in1+in2+in3 { DataType TestData ScanDataIn;
IsConnected In {
CoreSignal coresy:in0+coresy:in1+coresy:in2+coresy:in3;
}
}
out0+out1+out2+out3 {DataType TestData ScanDataOut;
IsConnected Out {
CoreSignal coresy:out0+coresy:out1+coresy:out2+coresy:out3;
}
}
}
External {
_sitk_ { PadType PrePad; PadValue D; }
_sotk_ { PadType PostPad; Padvalue X; }
}
Signals {
coretk:int_si[0] top.edt.scan_in[0];

coretk:int_so[0] top.edt.scan_out[0];
// for this case, only the coreinstance needs to be

// mapped since the combinational namemaps in the
// core have been maintained.
coresy top.sycore;
}
}
Macro load_unload_and_update_masks {
Purpose ControlObserve LoadMask;
Identifiers { EventType PreviousTestEnd {
Xref Previous_End_Point{Complete;End;}}}
}
Macro combinational_pattern {
Purpose DoTestOverlap;
}
} // PatternInfo
} //CTLMode both1
}//Environment

A.6 Mutliple input shift register (MISR) with masking
The general compression structure used in this example is shown in Figure A.8. It uses scan-in, fan-out for
decompression and MISRs with a space compactor for compression. Because MISRs do not handle
compression of unknown or unpredictable response values, compression using MISRs often include some
form of masking to mask out these unpredictable values before they can get into the MISR. In this case, the
data can be loaded into mask registers using the data path provided by the scan inputs. One or two additional
inputs are used to select for each scan cycle whether masking is to be done and if so, which mask register to
use or to just mask all chains.
Figure A.8General structure for compression
The example circuit has four scan inputs (SI[0:3]) and four MISR Observation (MO[0:3]) outputs. The
input decompression is a simple scan-in, fan-out. To keep the example simple, the fan-out factor is 2,
yielding eight internal chains. The output compression uses two MISRs and a space compactor to allow
observation of a composite MISR signature in a single tester cycle. The same clock (CLK) and scan enable
(SE) go to each scan flop and the MISR. For simplicity, each scan chain has only two flops. The scan-in bus
is used to feed both the internal chains, as well as the mask registers.

In this example, there is a separate clock (CML) that is used when loading the mask registers. Two chain
mask enable (CME) signals select one of four possible circuit states on each scan cycle: 00 is no masking;
01 is mask using reg 0, 10 is mask using reg 1, and 11 is mask all channels. Figure A.9 shows the
circuit diagram displaying the logic detail for this compression example.
For this example, there are two mask registers of four bits each. Each mask register bit is shared between
two scan chains such that when masking chain 0 or 1, both chain 0 and 1 are masked; similarly chains 2 and
3, 4 and 5, 6 and 7 are paired and shall be masked together. This helps reduce the overhead for the masking
logic, while somewhat reducing the flexibility of the masking.
SI [0]
SI [1] SI[2] SI[ 3]
0 0 0 0 0 0 0 0
1s
D Q 1s D Q 1s
D Q 1s D Q 1s
D Q 1s D Q 1s
D Q 1s D Q
CLK CLK CLK CLK CLK CLK CLK CLK
0 0 0 0 0 0 0 0
1s D Q 1s D Q 1s D Q 1s D Q 1s D Q 1s D Q 1s D Q 1s D Q
SE
CME0
CME1
D Q D Q D Q D Q
CM L CML CM L CM L
D Q D Q D Q D Q
CM L CML CM L CM L
RESET
D RQ D RQ DRQ D RQ DRQ DRQ DRQ DRQ
M O[0] M O[1] M O[2] MO[3]
Figure A.9Example circuit
This sample CTL defines the compression for this structure.
STIL 1.0 {

Design 2005;
CTL 2005;
Compression 2006;
}
Header {
Title CTL to define compression circuitry;
Date 17 April 2006
}
Signals {
SI[0:3] In {ScanIn 2;}
CLK In;
CML In;
RESET In;
SE In;
CME0 In; CME1 In;
MO[0:3] Out;
si0 Pseudo; si1 Pseudo; si2 Pseudo; si3 Pseudo; si4 Pseudo;
si5 Pseudo; si6 Pseudo; si7 Pseudo;
so0 Pseudo; so1 Pseudo; so2 Pseudo; so3 Pseudo; so4 Pseudo;
so5 Pseudo; so6 Pseudo; so7 Pseudo;
}
WaveformTable scanW {
Period 100ns;
Waveforms {
SI[0]+SI[1]+SI[2]+SI[3]+SE+CME0+CME1 {
01X {0nsD/U/N;
}
}
CLK+CML+RESET {
01PX {0nsD/U/D/N;
50nsD/U/U/N;
60nsD/U/D/N;
}
}
MO[0]+MO[1]+MO[2]+MO[3] {
lhX {0ns X, 10ns l/h/X; 20ns X;}
}
}
}
}
comp_load_unload {
// this macro assumes overlapping of scan-in with scan-out into the MISRs
W scanW;
C { SE = 1;}
// unload current tests response into MISRs while loading
// the next tests stimulus
Shift { V {SI[0]=#; SI[1]=#; SI[2]=#; SI[3]=#; CME0=#; CME1=#;
CLK=P;}}
// Measure the composite MISR signatures (a single cycle)
V {MO[0]=#; MO[1]=#; MO[2]=#; MO[3]=#;}
// Reset the MISR for the next test
V {RESET=P;}

}
comp_mask_load {
// this macro is invoked prior to comp_load_unload,
// but only if mask registers need to be loaded
W scanW;
C { SE = 1;}
// if both mask registers need to be loaded, the total 8 mask
// register bits get loaded in two cycles.
// if one mask register needs to be loaded, the 4 bits for that
// register can be loaded in a single cycle (like a partial load).
Shift { V {SI[0]=#, SI[1]=#, SI[2]=#, SI[3]=#, CML=P;}}
}
}
// These internal scan chains are anchored by internal nets si0 si7 and
// so0 so7.
ScanChain intchain0 {ScanCells flop[0] flop[1]; ScanLength 2;
ScanIn si0; ScanOut so0; ScanMasterClock CLK; ScanEnable SE;}
}
ScanStructures comp_mask_chains {
// Note: these are control-only registers
ScanChain maskchain0 {ScanCells mflop[0] mflop[1]; ScanLength 2;
ScanIn SI[0]; ScanMasterClock CML;}
}
CompressionStructures opmisr_mask_fanout {
Compressor opmisr_mask2 {
Vendor Cadence; { // vendor syntax optional
Compressor_Architecture = OPMISR+;
}
Wire masked0 so0 & (~(CME0 & CME1) & ~(CME0 & mflop[0]) &
~(CME1 & mflop[1]);
~(CME1 & mflop[1]);

~(CME1 & mflop[3]);
~(CME1 & mflop[3]);
~(CME1 & mflop[5]);
~(CME1 & mflop[5]);
~(CME1 & mflop[7]);
~(CME1 & mflop[7]);
State MISR1[0] { Data MISR1[3] ^ masked0; Clock CLK;
Reset RESET;}
State MISR1[1] { Data MISR1[0] ^ MISR1[3] ^ masked1; Clock CLK;
Reset RESET;}
Reset RESET;}
Reset RESET;}
Reset RESET;}
Reset RESET;}
Reset RESET;}
State MISR2[3] { Data MISR2[2] ^ MISR2[3] ^ masked7; Clock CLK;
Reset RESET;}
MO[0] MISR1[0] ^ MISR2[3];
MO[1] MISR1[1] ^ MISR2[2];
MO[2] MISR1[2] ^ MISR2[1];
MO[3] MISR1[3] ^ MISR2[0];
}
Decompressor fan_out_2 {
Vendor Cadence { // vendor syntax optional
Decompressor_Architecture = fan-out;
}
si0 SI[0];
si1 SI[1];
si2 SI[2];
si3 SI[3];
si4 SI[0];
si5 SI[1];
si6 SI[2];
si7 SI[3];
}
}
Environment opmisr_compression {
NameMaps anchor_points {
Signals { // These signals are in the netlist but not in the diagram
si0 chip.si0;
si1 chip.si1;
si2 chip.si2;
si3 chip.si3;

IEEE Std 1450.6.1-2009
si4 chip.si4;
si5 chip.si5;
si6 chip.si6;
si7 chip.si7;
so0 chip.so0;
so1 chip.so1;
so2 chip.so2;
so3 chip.so3;
so4 chip.so4;
so5 chip.so5;
so6 chip.so6;
so7 chip.so7;
}
}
CTLMode comp_atpg {
DomainReferences {
Timing comp_timing;
ScanStructures comp_internal_chains comp_mask_chains;
CompressionStructures opmisr_mask_fanout;
}
Internal {
SI[0:3] { DataType TestData ScanDataIn MaskData
{DataRateForProtocol Minimum 2;}}
// rate is 2 if no mask registers loaded, 3 if loading,
// 1 mask register, and 4 when loading both mask registers
SE {DataType TestControl ScanEnable { ActiveState U;
AssumedInitialState D;}}
// CME1+CME0: 00=no_masking, 01=mask_reg0, 10=mask_reg1,
// 11=mask_all
CME1+CME0 {DataType TestData MaskEnable {DataRateForProtocol
Minimum 2;}
MaskDisable {ActiveState D;} MaskAll {ActiveState U;}}
CLK {DataType TestClock ScanMasterClock MasterClock
{ActiveState U; AssumedInitialState D;}}
CML {DataType TestClock ScanMasterClock MaskData {ActiveState U;
RESET {DataType TestClock Reset (ActiveState U;
MO[0:3] {DataType TestData ResponseCompactor
{DataRateForProtocol Average 1;}}
}
External {
SI[0:3] {PadType PrePad; PadValue D;}
MO[0:3] {PadType PostPad; PadValue X;}
}
Macro comp_load_unload {Purpose ControlObserve, ResetSignature,
ObserveSignature;}
Macro comp_mask_load {Purpose LoadMask;}
}
}
}

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IEEE Standard for Describing

On-Chip Scan Compression

IEEE Computer Society

IEEE Standard for Describing

Test Technology Standards Committee

Approved 13 May 2009

IEEE-SA Standards Board

The Institute of Electrical and Electronics Engineers, Inc.

Copyright 2009 by the Institute of Electrical and Electronics Engineers, Inc.

PDF: ISBN 978-0-7381-5962-1 STD95936

Laws and regulations

Updating of IEEE documents

iv Copyright 2009 IEEE. All rights reserved.

Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee/interp/

Copyright 2009 IEEE. All rights reserved. v

Bruce Cory (NVIDIA), Chair

Dwayne Burek (Magma) Geir Eide (Magma) Brion Keller (Cadence)

Howard L. Wolfman, TAB Representative

vi Copyright 2009 IEEE. All rights reserved.

3. Definitions, acronyms, and abbreviations ............................................................................................ 6

4. New blocksCompressionStructures .................................................................................................. 7

5. STIL blockextensions to IEEE Std 1450-1999, Clause 8................................................................. 9

6. Environment blockextensions to IEEE Std 1450.1-2005, Clause 17 ............................................. 10

Annex A (informative) Examples.................................................................................................................. 14

Copyright 2009 IEEE. All rights reserved. vii

Copyright 2009 IEEE. All rights reserved. 1

Support most types of structures for input and output compression

1.3 Conceptual data flow

Assumes IP implemented correctly

Uses patterns, sequences, and event identifiers

Figure 1Conceptual OCI flow

2 Copyright 2009 IEEE. All rights reserved.

1.4 High-level implementation details

Copyright 2009 IEEE. All rights reserved. 3

Signals, Variables, Header Information

Scan Structures Definitions

Compression Structures Definitions

Figure 2OCI file structure after logic insertion

4 Copyright 2009 IEEE. All rights reserved.

1.5 Limitations of this standard

The limitations of this standard are as follows:

1.6 Structure of this standard

Different fonts are used as follows:

In the syntax definitions

Copyright 2009 IEEE. All rights reserved. 5

3. Definitions, acronyms, and abbreviations

3.2 Acronyms and abbreviations

1450_0 IEEE Std 1450-1999

6 Copyright 2009 IEEE. All rights reserved.

MISR multiple input shift register

4.1 CompressionStructures block

4.2 CompressionStructures block syntax description

(1) CompressionStructures COMPRESSION_STRUCTURE_NAME: This statement begins the definition of a

Copyright 2009 IEEE. All rights reserved. 7

CompressionStructures specified via DomainReferences in a CTL block are interoperable.

(2) Decompressor | Compressor COMPRESSION_BLOCK_NAME: This statement separates the definition of

(4) SIGNAL_OR_VARIABLE_NAME logic_expression: This statement specifies the hardware relationship

(7) Added CompressionStructures syntax to CoreType blocks to enable hierarchical definition of

4.3 CompressionStructures block example

8 Copyright 2009 IEEE. All rights reserved.

5. STIL blockextensions to IEEE Std 1450-1999, Clause 8

5.1 STIL syntax

5.2 STIL syntax description

5.3 STIL syntax example