Advanced Power MOSFET SFP9620

FEATURES
BVDSS = -200 V
Avalanche Rugged Technology
Rugged Gate Oxide Technology
RDS(on) = 1.5
Lower Input Capacitance ID = -3.5 A
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : -10 A (Max.) @ VDS = -200V
TO-220
Low RDS(ON) : 1.111 (Typ.)
1
2
3

1.Gate 2. Drain 3. Source

Absolute Maximum Ratings

Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage -200 V
o
Continuous Drain Current (TC=25 C) -3.5
ID o A
Continuous Drain Current (TC=100 C) -2.2
IDM Drain Current-Pulsed O
1 -14 A
VGS Gate-to-Source Voltage +
_ 30 V
EAS Single Pulsed Avalanche Energy O
2 327 mJ
IAR Avalanche Current O1 -3.5 A
EAR Repetitive Avalanche Energy O1 3.8 mJ
dv/dt Peak Diode Recovery dv/dt O3 -5.0 V/ns
o
Total Power Dissipation (TC=25 C) 38 W
PD o
Linear Derating Factor 0.3 W/ C
Operating Junction and
TJ , TSTG - 55 to +150
Storage Temperature Range
o
Maximum Lead Temp. for Soldering C
TL 300
Purposes, 1/8 from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
RJC Junction-to-Case -- 3.29
RCS o
Case-to-Sink 0.5 -- C/W
RJA Junction-to-Ambient -- 62.5

Rev. B

1999 Fairchild Semiconductor Corporation

 P-CHANNEL
SFP9620 POWER MOSFET

Electrical Characteristics (TC=25oC unless otherwise specified)

Symbol Characteristic Min. Typ. Max. Units Test Condition
BVDSS Drain-Source Breakdown Voltage -200 -- -- V VGS=0V,ID=-250A
BV/TJ Breakdown Voltage Temp. Coeff. -- -0.18 --
o
V/ C ID=-250A See Fig 7
VGS(th) Gate Threshold Voltage -2.0 -- -4.0 V VDS=-5V,ID=-250A
Gate-Source Leakage , Forward -- -- -100 VGS=-30V
IGSS nA
Gate-Source Leakage , Reverse -- -- 100 VGS=30V
-- -- -10 VDS=-200V
IDSS Drain-to-Source Leakage Current A o
-- -- -100 VDS=-160V,TC=125 C
Static Drain-Source
RDS(on) -- -- 1.5 VGS=-10V,ID=-1.8A O
4
On-State Resistance
gfs Forward Transconductance -- 2.3 -- VDS=-40V,ID=-1.8A O
4

Ciss Input Capacitance -- 415 540

VGS=0V,VDS=-25V,f =1MHz
Coss Output Capacitance -- 70 105 pF
See Fig 5
Crss Reverse Transfer Capacitance -- 26 40
td(on) Turn-On Delay Time -- 12 35
VDD=-100V,ID=-3.5A,
tr Rise Time -- 22 55
ns RG=18
td(off) Turn-Off Delay Time -- 33 75
See Fig 13 4 O
tf Fall Time -- 15 40 O 5

Qg Total Gate Charge -- 15 19 VDS=-160V,VGS=-10V,

Qgs Gate-Source Charge -- 3.3 -- nC ID=-3.5A
Qgd Gate-Drain( Miller ) Charge -- 7.5 -- See Fig 6 & Fig 12 4 O
O 5

Source-Drain Diode Ratings and Characteristics

Symbol Characteristic Min. Typ. Max. Units Test Condition
IS Continuous Source Current -- -- -3.5 Integral reverse pn-diode
A
ISM Pulsed-Source Current O
1 -- -- -14 in the MOSFET
o
VSD Diode Forward Voltage O4 -- -- -5.0 V TJ=25 C,IS=-3.5A,VGS=0V
o
trr Reverse Recovery Time -- 125 -- ns TJ=25 C,IF=-3.5A
Qrr Reverse Recovery Charge -- 0.59 -- C diF/dt=100A/s O
4

Notes ;
O Repetitive Rating : Pulse Width Limited by Maximum Junction
1
o
Temperature
O2 L=40mH, I =-3.5A, V =-50V, R =27*, Starting T =25 C
AS DD G J

O3 ISD <_ -3.5A, di/dt _< 300A/s, VDD_<BVDSS , Starting T J =25oC

O4 Pulse Test : Pulse Width = 250 s, Duty Cycle < _ 2%
O5 Essentially Independent of Operating Temperature
 P-CHANNEL
POWER MOSFET SFP9620
Fig 1. Output Characteristics Fig 2. Transfer Characteristics

101 V GS
101
Top : - 15 V
[A]

[A]
- 10 V
- 8.0 V
- 7.0 V
-ID , Drain Current

-ID , Drain Current

- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
100
100 150 oC

25 oC @ Notes :
1. VGS = 0 V
@ Notes : 2. VDS = -40 V
10-1 1. 250 s Pulse Test 3. 250 s Pulse Test
- 55 oC
2. TC = 25 oC
10-1
10-1 100 101 2 4 6 8 10
-VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]
[A]

Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
Drain-Source On-Resistance

5
-IDR , Reverse Drain Current

101

4
RDS(on) , [ ]

3
VGS = -10 V

100
2
150 oC

@ Notes :
1 25 oC 1. VGS = 0 V
VGS = -20 V 2. 250 s Pulse Test
@ Note : TJ = 25 oC

0 10-1
0 2 4 6 8 10 12 14 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]

Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
800
[V]

Ciss= Cgs+ Cgd ( Cds= shorted )

Coss= Cds+ Cgd VDS = -40 V
10
[pF]

-VGS , Gate-Source Voltage

Crss= Cgd VDS = -100 V

600 VDS = -160 V
C iss
Capacitance

400
C oss
5
@ Notes :
1. VGS = 0 V
200 C rss
2. f = 1 MHz

@ Notes : ID =-3.5 A

0 0
100 101 0 3 6 9 12 15
-VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
 P-CHANNEL
SFP9620 POWER MOSFET

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Drain-Source Breakdown Voltage

1.2 3.0

Drain-Source On-Resistance
-BVDSS , (Normalized)

RDS(on) , (Normalized)
2.5
1.1
2.0

1.0 1.5

1.0
0.9 @ Notes :
@ Notes :
1. VGS = 0 V 0.5 1. VGS = -10 V
2. ID = -250 A 2. ID = -1.8 A

0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
o
TJ , Junction Temperature [ C] TJ , Junction Temperature [oC]

Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
[A]

4
[A]

Operation in This Area

-ID , Drain Current

is Limited by R DS(on)
-ID , Drain Current

101 3
0.1 ms

1 ms

10 ms 2
100 DC
@ Notes :
1. TC = 25 oC
2. TJ = 150 oC 1
3. Single Pulse
10-1

0
100 101 102 25 50 75 100 125 150
-VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC]

Fig 11. Thermal Response

Thermal Response

D=0.5

10 0 @ Notes :
0.2 1. Z J C (t)=3.29 o C/W Max.
2. Duty Factor, D=t1 /t 2
0.1 3. TJ M -T C =P D M *Z J C (t)
P.DM
0.05
(t) ,

0.02 t1.
10- 1
0.01 t2.
JC

single pulse
Z

10- 5 10- 4 10 - 3 10 - 2 10 - 1 100 10 1

t 1 , Square Wave Pulse Duration [sec]
 P-CHANNEL
POWER MOSFET SFP9620
Fig 12. Gate Charge Test Circuit & Waveform

Current Regulator
VGS
Same Type
50K as DUT Qg
12V 200nF
300nF -10V

VDS
VGS Qgs Qgd

DUT

-3mA
R1 R2

Current Sampling (IG) Current Sampling (ID)

Charge
Resistor Resistor

Fig 13. Resistive Switching Test Circuit & Waveforms

RL
t on t off
Vout tf
td(on) tr td(off)
Vin VDD
( 0.5 rated VDS ) Vin
10%
RG
DUT

-10V
90%
Vout

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

BVDSS
LL 1
EAS = ---- LL IAS2 --------------------
VDS 2 BVDSS -- VDD
Vary tp to obtain ID tp Time
required peak ID
VDD VDS (t)
RG C VDD ID (t)
DUT
-10V IAS
tp BVDSS
 P-CHANNEL
SFP9620 POWER MOSFET

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

VDS
DUT
--

IS
L

Driver
VGS
Compliment of DUT
RG
(N-Channel) VDD

VGS dv/dt controlled by RG

IS controlled by Duty Factor D

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

Body Diode Reverse Current

IRM
IS
( DUT )
di/dt

IFM , Body Diode Forward Current

Vf
VDS
( DUT )
Body Diode VDD
Forward Voltage Drop

Body Diode Recovery dv/dt

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In Design product development. Specifications may change in
any manner without notice.

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supplementary data will be published at a later date.
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changes at any time without notice in order to improve
design.

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The datasheet is printed for reference information only.