DESIGN AND SIMULATION OF A MEMORY SYSTEM FOR MIPS

PROCESSOR

MUSA, MUAWIYYA MODIBO

IORNAV, KOHOL VALENTINE
OJIUGWO, CHUKWUKA

GROUP 3 PROJECT REPORT FOR CSE 510 DIGITAL AND

COMPUTER SYSTEMS
DEPARTMENT OF COMPUTER SCIENCE, AFRICAN UNIVERSITY
OF SCIENCE AND TECHNOLOGY ABUJA.

PROF. BEN ABDALLAHABDERAZEK

COURSE LECTURER

SEPTEMBER, 2016.
Abstract
A final project for CSE 510 : Digital and Computer Systems at African
University of Science and Technology, Abuja is presented. The projects
purpose was to design and simulate the memory system of a MIPS processor
using the Verilog hardware description language. The objectives of the project
consisted of furthering our understanding the memory system of a MIPS
Processor and to further understand the MIPS instruction set. Discussions and
results of the projects are included in this report.
1.0 Introduction
The memory is the part of a computer in which data or program instructions can
be stored for retrieval. (I.e Holds both instructions and data of a computer
program).There are two basic operations of a memory which are; load and store.
The MIPS processor has two memory type; Instruction memory and Data
Memory. Data is loaded from the memory using load instructions and as well
stored using store instructions. Each off this has an address from which data is
fetched or stored (written) to. In this project, we focused on a unified memory
system for the MIPS-32 bit processor.

Read data

Data add Data Out

Write data

clk
1.1 Purpose of the Memory System
This design was built with the MIPS instruction set in mind. Using

2.0 Design methodology

The planning of the project was broken down into steps. Each step was
completed before going on to the next step. The testing steps are described in
testing methodology below. The steps were done in this order:
1. Create modules that are the components of a unified memory
2. Test individual modules for functionality
3. Piece all of the individual modules together
4. Write a test bench program for functional test.
5. Generate waveform to view the simulation.
Tools used
The work was done using:
(i) Quartus II 64-bit software which was used as editor in writing the
programme for the full adder. It was also used for simulating
waveform.
(ii) Iverilog
(iii) Notepad ++: for writing a file for the test bench

3.0 Testing and Simulation methodology:

We used a test bench to test our design.
4.0 Conclusion
This project helped us understand how the memory system of a MIP processor
works. It showed us the importance of how the write and read data actually
work with respect to memory addresses.
This was a difficult project, mostly because of time limit and been novice in the
HDL especially Verilog. Understanding the HDL to develop this project was
quiet challenging. We had to research and get some codes since we had little
idea of starting it from the scratch. Deciding which of the components needed
to be clocked and which ones didnt was a pretty major part of this project.
This was an interesting project, but we could have used more time to work on it.
A suggestion would be to have more time with our faculty member so that we
had more time to dedicate to this project and learn more practically.
The final code was compiled and simulated in Quartus II. The RTL view of the
design is shown in the appendices.

4.1 Lessons Learned

At first the topic simple but it was a challenging one indeed. Little mistakes can
take a long time to debug. Most of the time we spent on this project was
actually to understand the structure of the memory system of MIPS processor.
After kicking off, debugging secondary source codes took a lot of our time.
Logical errors are the most costly errors to make because only debugging can
discover them. To avoid logical errors we had to make sure that we knew
exactly how the MIPS memory system works causing us to learn a lot among
varying literatures in existence.