A new proposal for ground leakage current reduction
in Transformerless Grid-Connected Converters for
Photovoltaic Plants
D. Barater, G. Buticchi, A.S. Crinto, G. Franceschini, E. Lorenzani
DII-University of Parma
Parma, Italy
davide.barater@studenti.unipr.it, giampaolo.buticchi@studenti.unipr.it, andreastefano.crinto@rawpowergroup.it,
giovanni.franceschini@unipr.it, emilio.lorenzani@unipr.it
Abstract -- In domestic grid connected PV applications a single
phase converter is usually used. In such a low power plants it is
possible to adopt converter topologies without galvanic isolation
between the photovoltaic panels and the grid. The absence of a
high or low frequency transformer permits to reduce power
losses, cost and size of the converter. On the other side in
presence of a galvanic connection a large ground leakage current
could arise due to parasitic PV panel capacitance. Leakage
currents cause electric safety problems, EMI increase and,
consequently, a reduction of the converter power quality. This
paper presents a converter topology able to minimize the ground
leakage current also in case of unipolar PWM modulation
without increasing inductive common mode filter size and
preserving efficiency. Simulations and experimental results show
the feasibility of the proposed solution.
I. INTRODUCTION
Renewable energy sources are key issues in the attempt to
address energy problems. Among them photovoltaic (PVs) is
one of the most up to date techniques. However their diffusion
is limited by relatively high cost in comparison with
traditional energy sources. Nevertheless the downward
tendency in the price of the PV modules together with their
increasing efficiency make electronic converter under the spot
lights as the enabling technology for integrating PV systems
into the grid.
In low-power grid connected applications a single phase
converter is used: its architecture embeds usually a line
transformer or a high frequency transformer. In new converter
designs the tendency is to abandon line frequency
transformers because of size, weight and price in favour of
high frequency transformer. The presence of high frequency
transformer needs several power stages and, as a consequence,
increasing efficiency and reducing costs may be a hard task.
In low power PV applications it is possible to remove
transformer at all in order to reduce losses, costs and size. This
results in a galvanic connection between the grid and the DC
source introducing an additional ground leakage current due to
the solar panel big parasitic capacitance [1,2], e. g. 10-
100nF/kWp. A higher ground leakage current gives rise to
EMC problems and increases the harmonics injected into the
grid. Some standards, like the DIN VDE 0126-1-1 impose the
disconnection of the converter if the ground leakage current
exceeds prefixed limits. The harmonic content and the
amplitude of this current depend on the converter topology
978-1-4244-4649-0/09/$25.00 2009 IEEE 4531
and on the resonant circuit formed by the PV parasitic
capacitance, the converter filters and the grid impedance (Fig.
1). Due to system efficiency optimisation the damping of this
resonant circuit can be very small and, as a consequence, the
ground leakage current can reach significant amplitudes. A
possible solution to reduce the ground leakage current
decreasing the excitation of the resonant circuit is not feasible
because resonance parameters depend on environmental
conditions.
In the full bridge topology of Fig. 1 the ground leakage
current, i.e. the common-mode current, is caused by the
common-mode voltage vcm variations at mid points A and B
of the converter legs:
v +v
vcm = A 0 BO (1)
2
To avoid it converter topologies free from common-mode
voltage variations can be adopted [3,4].
Converter topologies intrinsically safe from leakage
currents are the Half-Bridge (HB) and the Neutral Point
Clamped (NPC) ones [5,6]. Nevertheless the need of twice the
input voltage represents an important drawback.
A low ground leakage current can be obtained also through
a full bridge converter driven by bipolar PWM [4]. PWM full
bridge requires lower (half) input voltage if compared with
HB and NPC solutions but exhibits a lower efficiency in
rejecting common mode. From a power quality point of view
all these solutions present current ripple at switching
frequency.
As far as converter architecture using transformers, the full
bridge converter with unipolar PWM is widespread used
thanks to a good trade-off between efficiency, complexity and
price. The main advantages of unipolar PWM are a current
ripple at twice switching frequency and a unipolar voltage
across the AC output filter (lower core losses). As a result the
resulting maximum current ripple is four times smaller then
the maximum current ripple of the bipolar PWM [7]. However
the common mode voltage generated by the full bridge
converter driven by unipolar PWM is at switching frequency
with a peak-to-peak amplitude equals to DC voltage Bus [8].
As a consequence, a big common-mode filter is required in
photovoltaic transformerless applications.
The architecture proposed in this paper presents a classical
full bridge driven by unipolar PWM with two added blocks
assuring no common-mode voltages variations in presence of
actual (asymmetrical) commutations. In the following
extensive simulation results and experimental results, showing
the effectiveness of the proposed topology, are presented.
T1 D1 T 3 D3
VDC vA0 A
Vgrid
vB 0 B
T2 D2 T 4 D4
icm
Fig. 1. Ground leakage current in a transformerless PV converter.
II. FULL BRIDGE TOPLOGIES FOR PV TRANSFORMERLESS
CONVERTERS
An ideal full bridge converter with bipolar PWM is
intrinsically free from common-mode output voltage
variations. For this reason its adopted nowadays in some
commercial transformerless converters.
Through the support of Fig. 1 its possible to compute the
common-mode voltage applied during a switching cycle in
case of bipolar PWM. The switching cycle consists of two
possible configurations:
1) T1 and T4 On (T2, T3 Off):
V through D2, T4, vcm = 0 .
v A0 = VDC , vB 0 = 0, vcm = DC
2
2) T2 and T3 On (T1,T4 Off):
V 2
v A0 = 0, vB 0 = VDC , vcm = DC
2
If the turn on and turn off occur at the same time (ideal
commutation), there would be no changes on the common-
mode voltage and thus no additional ground leakage current
would appear. However, in real converters, a small common-
mode high-frequency filter is necessary to avoid an increase
of the ground leakage current due to switching mismatch and
different dv / dt at converter output terminals A and B.
Modifications to the full bridge with bipolar PWM have
been recently proposed. Fig. 2 presents the full-bridge
topology with two additional blocks used alternatively, the
former is inserted in the DC converter side and the latter in the
AC converter side and both reduce the ground leakage current
[9,10]. The use of DC or AC decoupling allows, during the
freewheeling diode conductions, the disconnection of the grid
voltage from photovoltaic panel. Again asymmetrical PWM
commutations can determine a little leakage ground current.
These two topologies achieve an output voltage similar to
that obtained in the full bridge with unipolar modulation, but
the frequency of the current ripple is still at the switching one.
The AC decoupling shown in figure 2, called Highly Efficient
Reliable Inverter Concept (HERIC), is used in Sunways
converters while the DC decoupling, called H5 topology, is
used in SMA converters.
978-1-4244-4649-0/09/$25.00 2009 IEEE
A
v A0
Vgrid
B
vB 0
Fig. 2. Full Bridge topology with DC and AC decoupling additional
blocks.
III. PROPOSED ARCHITECTURE FOR SINGLE PHASE
TRANSFORMERLESS GRID-CONNECTED CONVERTER
The most widespread single phase topology is the full
bridge one. This topology allows either bipolar or unipolar
PWM modulation.
Referring to Fig. 1 the common-mode voltage resulting
during a switching cycle in case of unipolar PWM is
computed in the following. Reference is made to positive
output voltage and current (first quadrant operations); output
voltage is indicated as v AB = v A0 vB 0 . The switching cycle
consists of four possible configurations:
V
1) T1, T4 On (T2 and T3 Off): v AB = VDC , vcm = DC .
2
2) T2, T4, D2 On: v AB = 0 . Low side current freewheeling
VDC
3) T1,T4 On (T2 and T3 Off): v AB = VDC , vcm = .
4) T1, T3, D3 On: v AB = 0 . High side current freewheeling
through T1,D3, vcm = VDC .
The common mode voltage vcm varies from 0 to VDC and a
large ground leakage current will flow.
Fig. 3 shows the proposed basic idea able to solve this
problem. Two additional blocks are added: the former, named
DC Decoupling block, locks the common mode voltage to
VDC/2 value while the latter, named No-Ideal Compensation
block, helps to keep constant the vcm in presence of non ideal
(asymmetrical) commutations.
The DC decoupling disconnects the H-bridge from DC
Source during the current freewheeling phases. During high
side freewheeling T5 is switched off while during low side
freewheeling T6 is switched off. In case of ideal
commutations this block is sufficient to guarantee no
variations of the common mode voltage vcm . In actual
converter, to lock vcm at VDC 2 during asymmetrical
commutations, two additional low power switches should be
added. In order to avoid the complexity introduced by two
controlled switches an attempt was made using two diodes
instead. The idea relies on the following explanation. Once the
decoupling switch T5 opens, the voltage of the high side of the
DC bus at the right side is floating. Its to be expected that this
voltage, due to parasitic capacitances, starts to decrease but the
4532
inserted diode will clamp it to VDC/2. Similar considerations
can be made when the other DC decoupling switch, T6, opens.
Simulation results confirm the hypothesis. The two diodes
impose a maximum voltage equal to VDC/2 across T5 and T6
when they are off. Nevertheless the performances of this
simple solution are affected by the value of the PCB parasitic
capacitances and inductances.
In order to fix this drawback, locking the common mode
voltage to a desired value independent from parasitic
components, it is possible to turns off (opens) the transistors of
the DC decoupling block in advance with respect to the begin
of every freewheeling phase. In this way, during this leading
time (0.3-0.5s), the two diodes of the No-Ideal Compensation
block are forced on, imposing, in turn, the voltage of the high
side and of the low side of the H-bridge bus to VDC/2.
Experimental results have shown that this solution reduces
strongly the variations of the common mode voltage.
In figure 3 x and y represent the PWM signals used for
driving the legs of the full bridge. The figure shows that a
simple combination of PWM signals can be used for driving
the controlled switches of the DC decoupling block.
Since the maximum voltage across these switches is VDC/2,
of the converter. The H-bridge block works, in a V-I plane,
only in the first and third quadrant: the first quadrant in the
positive semi-period and the third quadrant in the negative
one. Being the H-bridge output voltage fixed by the grid, only
two on four controlled switches are needed for each semi-
period: T1 and T4 for the positive semi-period; T2 and T3 for
negative one (Fig. 4). In this way the switches T2 and T3 are
held off during the whole positive semi-period while T1 and
T4 are held off during the whole negative semi-period.
Fig. 4 shows the PWM modulation of the all controlled
switches in a period of the grid voltage.
T 1, T 3 = Off
T 5 = x ,T 6 = y
T 2, T 4 = Off
T 5 = y ,T 6 = x
y x x y
vgrid
vgrid

latest generation Mosfets are eligible in order to reduce power igrid igrid
losses. x
y
y
x

Fig. 4. Optimal PWM Control Strategy for every semi-period.

Assigning the logic value 1 to the boolean variable S during

the positive semi-period of the grid voltage and the logic value
0 during the negative one the proposed strategy modulation is
shown in Fig. 5.

x
Fig. 3. Basic Idea for Unipolar PWM for transformerless converters. y x
S
y
S
Lf Lgrid
S
A
In an actual converter the PWM modulation strategy of the VDC
VDC
2 B
Cf
vgrid
DC decoupling block has to be modified because of the icm y x y
Rf

S S Lf Lgrid
presence of dead times between the two complementary PWM CPVground
vground x
S Rground
signals of every leg of the H-bridge. In presence of dead times
the PWM strategy of the basic idea (Fig. 3) is not able to lock
the common mode output voltage vcm of the converter at Fig. 5. PWM Strategy Modulation for the proposed topology.

VDC/2. The command signals of T5 and T6, obtained from the With reference to the schematic of fig. 5 and to positive
unipolar PWM signals x and y through simple logic output voltage and current (first quadrant operations) the
operators (NAND, OR) dont assure a synchronized following four configurations are sequentially operated in a
disconnection of the H-bridge from DC source at the switching cycle:
beginning of a freewheeling phase. The synchronization can V
1) T1, T4, T5,T6 ON : v AB = VDC , vcm = DC .
be obtained driving the two transistors of the DC decoupling 2
block through the same PWM signals that cause the 2) T2, T4, T5, D2 ON: v AB = 0 . Low side current freewheeling
freewheeling phases in that semi-period. In the positive semi-
VDC
period the high-side freewheeling is caused by the turn-off of through T4, D4, vcm = v A 0 = vB 0 = .
T4, and the PWM signal of T4, y , is used to drive T5 as well. 2
On the other side the low-side freewheeling is caused by the VDC
3) T1, T4, T5, T6 ON: v AB = VDC , vcm = .
turn-off of T1, and the PWM signal of T1, x , is used to drive 2
T6. Similar considerations can be repeated for the negative 4) T1, T3, T6, D3 ON: v AB = 0 . High side current freewheeling
semi-period. VDC
The H-bridge PWM modulation strategy of the basic idea through T1, D3, vcm = v A 0 = vB 0 = .
2
can be improved thanks to the unitary power factor operations

978-1-4244-4649-0/09/$25.00 2009 IEEE 4533

 The proposed topology adopts 6 power switches and two Figures 6a, 6b, 6c show respectively the common mode
low power diodes in order to reduce the effects of non ideal voltage vcm , the ground voltage vground and the ground leakage
commutations. The high number of power semiconductors
current icm without the DC Decoupling and the No-Ideal
requires an analysis of power losses in order to compare the
proposed topology with the classic full bridge driven by Compensation blocks. These simulations are performed to
unipolar modulation. Table I resumes the theoretical highlight the common mode voltage and the ground leakage
semiconductor power losses for the two topologies. current arising when a unipolar PWM is used in
transformerless full bridge converters (Fig. 1).
TABLE I SEMICONDUCTOR POWER LOSSES COMPARISON (THEORETICAL) Figures 6a1, 6b1, 6c1 show the simulation results obtained
Power Losses in a switching cycle
Topology Conduction N of commutations Diode when the two additional blocks and the improved unipolar
(switching voltage) Recovery modulation previously described are adopted. Figure 6a1
Full bridge 2 IGBT
with classical 4 turn on (VDC) 2 shows the common mode voltage vcm that is locked to
unipolar PWM 1 IGBT + 1 Diode 4 turn off (VDC)
freewheeling
VDC 2 ; as a consequence the ground voltage vground doesnt
2 IGBT +2 Mosfet 2 turn on (VDC), 2 contain high frequency components and only the fundamental
Proposed turn on (VDC/2), 2
topology 1 IGBT + 1 Diode 2 turn off (VDC), 2 grid frequency is present (Fig. 6b1). The resulting leakage
freewheeling turn off (VDC/2) ground current is very small, as shown by Fig. 6c1.
The comparioson shows that, despite of the greater number of 500 500

Common-mode Voltage [V]

Common-mode Voltage [V]

power switches, the switching power losses of the proposed
400 400
topology, because of T5 and T6 switching voltage reduction,
300 300
are lower with respect to the full bridge driven by unipolar
200 200
modulation. On the contrary the conduction power losses
increases due to the series of four power switches during ton 100 100

operations. Since two of them, T5 and T6, have to manage 0 0

half the DC Link voltage power Mosfets can be used to 0 0.005

Time [s]
0.01 0 0.005
Time [s]
0.01

bound conduction power losses. (a) (a1)

Ground Voltage[V]

Ground Voltage[V]
IV. SIMULATION RESULTS 500 500

The proposed topology (Fig. 5) has been simulated using 0 0

PLECS toolbox, which allows fast simulations of power
electronic circuits in Simulink environment. -500 -500
A simple PI+feed forward current controller is used to
0 0.05 0.1 0 0.05 0.1
inject, with unitary power factor, a sinusoidal current of Time [s] Time [s]
13Arms into the grid. This corresponds to an injected active (b) (b1)
Ground Leakage Current [mA]
Ground Leakage Current [A]

power of 3kW. 2 1

Extensive simulations have been performed with the 1 0.5

attempt to put in evidence the performance of the proposed
converter topology about common mode voltage and leakage 0 0

ground current rejection. In particular they show the abilities -1 -0.5

of the proposed topology to hold the common voltage at the
-2 -1
constant value VDC/2. In such a way the resulting common 0 0.05 0.1 0 0.05 0.1
Time [s] Time [s]
mode current is negligible. Moreover some simulations in (c) (c1)
order to compute the power losses of the proposed topology
Fig. 6. Simlulation results. Common mode voltage (blue trace), ground
versus the unipolar full bridge one have been performed. voltage (red trace) and ground leakage current (black trace) in case of
Table II reports the main parameters used for simulations. unipolar full bridge topology (a),(b),(c) and in case of the proposed topology
(a1),(b1),(c1).
TABLE II SIMULATION PARAMETERS
3KW PV POWER CONVERTER AND GRID IMPEDANCE The semiconductor power losses are calculated through the
Bus voltage VDC = 450V
PLECS thermal description of the power switches and diodes.
Grid voltage Vgrid = 230Vrms The Mitsubishi IPM (Intelligent Power Module)
Ground to neutral resistance Rground = 2 PM50B4LA060 (600V, 50A), specific for PV applications,
PV Parasitic capacitance CPVground = 14nF was used for power losses models of IGBT and diodes. The
Inductor output filter L f = 2mH
power losses model of Mosfets reflects the characteristics of
the power Mosfet IXFH88N30P (300V, 75A), manufactured
Capacitor output filter C f = 2.2 F by IXIS. Table III shows the results of power losses
Passive damping resistance R f = 0.5 simulations.
Grid inductance Lgrid = 40 H
Switching frequency f sw = 10 kHz

978-1-4244-4649-0/09/$25.00 2009 IEEE 4534

 TABLE III SEMICONDUCTOR POWER LOSSES @ 3KW OF INJECTED POWER
H-bridge DC
Topology fsw Tot.
Decoupling
Full bridge with 10kHz 43,9W Absent
classical unipolar PWM
Proposed topology 10kHz 36,9W 10,7W
V. EXPERIMENTAL RESULTS
In order to verify the performances of the proposed
architecture about power converter performances and leakage
current reduction some experimental results are here reported.
A d-q current controller synchronous with the grid voltage
was developed to control the injected current [11]. The 3kW
power converter prototype, shown in Fig. 7, is based on a low
cost DSP (56F83XX by Freescale) that implements the d-q
controller, the grid synchronization by a digital PLL and the
proposed PWM modulation strategy. The H-bridge relies on
four 600V 30A IGBT while two 300V 30A Mosfets form the
DC decoupling block. A simple LC filter, based on two 1mH
inductances and one 2.2F capacitance, is adopted at the
output of the power converter. The detailed design and
optimization of the output filter is not investigated in this
paper. Two cheap inductive common mode filters (2mH) are
presented one at the input and the other at the output of the
power converter prototype.
Experiments refer to a switching frequency fsw=20kHz and
to a grid voltage Vgrid=230Vrms@50Hz. A low distortion DC
voltage source VDC =380V is used instead of photovoltaic
string to supply the power converter.
Fig. 7. Transformerless grid connected converter prototype.
Fig. 8 shows the test bed used to evaluate the proposed
topology in comparison with the unipolar full bridge one.
In order to evaluate the performances of the proposed
topology in presence of a PV parasitic capacitance two
equivalent parasitic capacitances, 4.4nF and 184.4nF, were
connected across the negative pole of the DC voltage source
and the earth. In case of unipolar full bridge converter the
lower equivalent parasitic capacitance value gives rise to a
very high ground leakage current value. Therefore results
referring only to 4.4nF capacitance are reported.
Ground leakage current is measured with a current probe
put around the two wires of the single phase connection.
978-1-4244-4649-0/09/$25.00 2009 IEEE
A
VDC Vgrid
43,9W
B
47,6W 0 icm
180nF 4.4nF
vground
Fig. 8. Test bed for leakage current measurement.
Fig. 9 shows the injected grid current and the grid voltage
for the unipolar full bridge topology (Fig.9a) and for the
proposed topology (Fig.9b) in case of an injected active
power of 3kW. As it can be seen the proposed topology
doesnt deteriorate current waveform.
(a) (b)
Fig. 9. Injected grid current (red trace 10A/div) and grid voltage (blue
one 100V/div). Unipolar full bridge topology (a), proposed one (b).
Fig. 10 refers to the unipolar PWM full bridge converter in
case of unipolar modulation and without the proposed
compensating blocks.
Fig. 10a shows VA0 and VB0 waveforms while Fig. 10b
shows their sum VA0+VB0 i.e. twice the common mode
voltage vcm . It is to be noted that during freewheeling phases
the common mode voltage oscillates alternatively from zero
to VDC. As it can be expected the resulting high frequency
contents give rise to a strong ground leakage current (about
120mArms) shown in Fig. 11. In the same figure the ground
voltage is reported.
(a) (b)
Fig. 10. Unipolar PWM full bridge converter, time/div 20s. In (a) VA0
(red trace 200V/div), VB0 ( blue trace 200V/div) and injected grid current
(violet trace 5A/div); in (b) 2 v cm (150V/div).
Fig. 12 refers to the proposed topology. In particular Fig.
12a shows VA0 and VB0 waveforms while Fig. 12b shows their
sum VA0+VB0 i.e. twice the common mode voltage cm.
Differently from previous solution, during free wheeling
phases VA0 and VB0 are clamped to VDC/2 and this results in a
quite constant common mode voltage (Fig. 12b).
4535

Fig. 11. Unipolar PWM full bridge converter, time/div 10ms. Ground
leakage current (black trace 100mA/div) and ground voltage (blue one
200V/div); 4.4nF parasitic capacitance.
(a) (b)
Fig. 12. Proposed topology, time/div 20s. In (a) VA0 (red trace
200V/div), VB0 ( blue trace 200V/div) and injected grid current (violet trace
5A/div); in (b) 2 v cm (150V/div).
Fig. 13 shows the behaviour of the proposed topology in
presence of an equivalent parasitic capacitance; both ground
leakage current and ground voltage are reported. In particular
Fig. 13a shows the effect of a 4.4nF parasitic capacitance, its
presence causes a ground leakage current of about 4mArms.
Fig. 13b refers to 184.4nF parasitic capacitance, in this case
the leakage current increases to 18mArms. Comparing Fig. 13
and Fig. 11 the improvement introduced by the proposed
topology can be pointed out.
(a) (b)
Fig. 13. Proposed topology, time/div 10ms.Ground leakage current (black
trace 20mA/div) and ground voltage (blue one 100V/div), 4.4nF (a) and
184.4nF (b) parasitic capacitance.
Eventually Fig.14 shows the efficiency of the proposed
topology versus output electric power. Despite the greater
number of switches it results quite good.
Fig. 14. Efficiency of the power converter prototype driven by the
proposed PWM modulation strategy.
978-1-4244-4649-0/09/$25.00 2009 IEEE
VI. CONCLUSIONS
In this paper a feasible solution to reduce ground leakage
current in transformerless full bridge converter driven by
unipolar PWM is presented. It relies on two suitable blocks
added to a typical full bridge converter scheme: the DC
decoupling block with the aim to lock the common mode
voltage to VDC/2 and the No-Ideal compensation block to keep
the vcm constant in presence of non ideal commutations. Since
the performances of the No-Ideal Compensation block are
affected by PCB parasitic effects to avoid the presence of
heavy inductive common mode filters a suitable PWM
modulation strategy was developed. Simulation results and
extensive experimental results, focused mainly on ground
leakage current analysis, showed the effectiveness of the
proposed solution.
Eventually a power losses comparison between the classic
unipolar full bridge topology and the proposed one has been
performed. Despite the higher number of involved switches
the proposed topology presents only a very slight increase of
power losses and the measured efficiency is quite good.
REFERENCES
[1] M. Calais and V. G. Agelidis, Multilevel converters for single-phase
grid connected photovoltaic systemsAn overview in Proc. IEEE Int.
Symp. Ind. Electron., 1998, vol. 1, pp. 224229.
[2] M. Calais, J. M. A. Myrzik, and V. G. Agelidis, Inverters for
singlephase grid connected photovoltaic systemsOverview and
prospects in Proc. 17th Eur. Photovoltaic Solar Energy Conf.,
Munich, Germany, Oct. 2226, 2001, pp. 437440.
[3] Lopez, Oscar; Teodorescu, Remus; Freijedo, Francisco; DovalGandoy,
Jesus; Leakage current evaluation of a singlephase transformerless
PV inverter connected to the grid Applied Power Electronics
Conference, APEC 2007 - Twenty Second Annual IEEE Feb. 25 2007-
March 1 2007 Page(s):907 912.
[4] Gonzalez, R.; Lopez, J.; Sanchis, P.; Marroyo, L.; Transformerless
Inverter for Single-Phase Photovoltaic Systems Power Electronics,
IEEE Trans. on Volume 22, Issue 2, March 2007 Page(s):693 697.
[5] Gonzalez, R.; Gubia, E.; Lopez, J.; Marroyo, L.; Transformerless
Single-Phase Multilevel-Based Photovoltaic Inverter Industrial
Electronics, IEEE Transactions on Volume 55, Issue 7, July 2008
Page(s):2694 2702.
[6] Lopez, Oscar; Teodorescu, Remus; Doval-Gandoy, Jesus; Multilevel
transformerless topologies for single-phase grid-connected converters
IEEE Industrial Electronics, IECON 2006 - 32nd Annual Conference
on Nov. 2006 Page(s):5191 5196.
[7] N. Mohan, T. Undeland, W.P.Robbins, Power Electronics:
Converters, Applications and Design, 3rd ed. Wiley.
[8] Lopez, Oscar; Teodorescu, Remus; Freijedo, Francisco; Doval-Gandoy,
Jesus; Eliminating ground current in a transformerless photovoltaic
application Power Engineering Society General Meeting, 2007. IEEE
24-28 June 2007 Page(s):1 5.
[9] Kerekes, T.; Teodorescu, R.; Borup, U.; Transformerless
Photovoltaic Inverters Connected to the Grid Applied Power
Electronics Conference, APEC 2007 - Twenty Second Annual IEEE
Feb. 25 2007-March 1 2007 Page(s):1733 1737.
[10] Gonzalez, R.; Lopez, J.; Sanchis, P.; Gubia, E.; Ursua, A.; Marroyo, L.;
High-Efficiency Transformerless Single-phase Photovoltaic Inverter
Power Electronics and Motion Control Conference, 2006. EPE-PEMC
2006. 12th International Aug. 2006 Page(s):1895 1900.
[11] Bellini, A.; Franceschini, G.; Lorenzani, E; Tassoni, C.; Synchronous
reference frame grid current control for single-phase photovoltaic
converters , in Proc. of IAS 2008, Edmonton (Canada), October 5-9
2008, pp 1 7.
4536