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1 Introduction
In high-power server applications to meet high-efficiency and green standards some power-supply
designers have found it easier to use a phase-shifted, full-bridge converter. This is because the
phase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter
reducing switching losses, and EMI and increasing overall efficiency. The purpose of this application
report is to review the design of the 600-W, phase-shifted, full-bridge converter for one of these power
systems, using TIs new UCC28950 Phase-Shifted, Full-Bridge Controller, and was based on typical
values. In a production design the values need to be modified for worst case conditions. Hopefully this
information will aid other power supply designers in their efforts to design an efficient phase-shifted,
full-bridge converter. Also note there is a MathCAD Design Tool, (TI Literature Number SLUC210), that
goes along with this application note as well.
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Functional Schematic www.ti.com
2 Functional Schematic
CT
+
QA DB QC
OUTA OUTC
R RE QB
V IN C IN
d QD d
LS
DA QB QD
OUTB OUTD
DC
RS
_
T1
CS
L OUT
C BP1 +
VREF
QE QF C OUT V OUT
OUTE OUTF
V OUT 1uF
_
RB RA
RI UCC28950 CS
C BP2
CP 1uF R LF1
1 VREF 24
GND 22 ohm
RC 2 EA+ VDD 23 12V Bias
4 21 R LF2
COMP OUTB OUTB
1k
5 SS/EN OUTC 20 OUTC
VREF
3 Power Budget
To meet the efficiency goal a power budget needs to be set.
1- h
PBUDGET = POUT 45.2 W
h (1)
2 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Preliminary Transformer Calculations (T1)
a1 =
(VINMIN - 2 VRDSON ) DMAX 21
VOUT + VRDSON (5)
Turns ratio rounded to the nearest whole turn.
a1 = 21 (6)
Calculated typical duty cycle (DTYP) based on average input voltage.
DTYP =
(VOUT + VRDSON ) a 0.66
(VIN - 2 VRDSON ) (7)
Output inductor ripple current is set to 20% of the output current.
POUT 0.2
DILOUT = = 10 A
VOUT (8)
Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance
(LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the
transformer (T1) to ensure the converter operates in current-mode control. If LMAG is too small the
magnetizing current could cause the converter to operate in voltage mode control instead of peak-current
mode control. This is because the magnetizing current is too large, it will act as a PWM ramp swamping
out the current sense signal across RS.
VIN (1 - DTYP )
LMAG 2.76mH
DILOUT 0.5
fS
a1 (9)
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Preliminary Transformer Calculations (T1) www.ti.com
Figure 2 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with
respect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1s secondary
winding currents as well. Variable D is the converters duty cycle.
IPP
IPRIMAY
IMP2 IMP2 IPP -DILOUT/ (2 a1)
IMP
0A
On
QEg
Off
On
QFg
Off
IQE
0A
IQF
IPS
IMS2
IMS
IMS2 IPS -DILOUT/2
0A
DILOUT/2
4 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Preliminary Transformer Calculations (T1)
(I - I )
2
D
ISRMS1 = MAX IPS IMS + PS MS 29.6 A
2 3
(13)
Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are
both on.
1 - DMAX (I - I )
2
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Preliminary Transformer Calculations (T1) www.ti.com
T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.
(IPP - IMP )2
IPRMS1 = (DMAX ) IPP IMP +
2.5 A
3
(21)
T1 Primary RMS (IPRMS2) current when the converter is free wheeling.
(IPP - IMP2 )
2
NOTE: This is just an estimate and the total losses may vary based on magnetic design.
(
PT1 2 IPRMS 2 DCRP + 2 ISRMS 2 DCRS 7.0 W ) (29)
Calculate remaining power budget:
PBUDGET = PBUDGET - PT1 38.1W (30)
6 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com QA, QB, QC, QD FET Selection
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Selecting LS www.ti.com
6 Selecting LS
Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage
switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch
node. The following equation selects LS to achieve ZVS at 100% load down to 50% load based on the
primary FETs average total COSS at the switch node.
NOTE: There may be more parasitic capacitance than was estimated at the switch node and LS
may have to be adjusted based on the actual parasitic capacitance in the final design.
VINMAX 2
LS (2 COSS _ QA _ AVG ) 2
- LLK 26 mH
IPP DILOUT
2 - 2 a1
(39)
For this design a 26-H Vitec inductor was chosen for LS, part number 60PR964. The shim inductor had
the following specifications.
LS = 26 mH (40)
LS DC Resistance:
DCRLS = 27mW (41)
Estimate LS power loss (PLS) and readjust remaining power budget:
PLS = 2 IPRMS 2 DCRLS 0.5 W (42)
PBUDGET = PBUDGET - PLS 29.2 W (43)
8 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Output Inductor Selection (LOUT)
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Output Capacitance (COUT) www.ti.com
10 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Select FETs QE and QF
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Select FETs QE and QF www.ti.com
To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the
gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate
charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS.
QE MILLER _ MIN
52 nC
NOTE: The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drive
current.
IP 4 A (69)
Estimated FET Vds rise and fall time:
100nC - 52nC 48nC
tr t f = = 24ns
IP 4A
2 2 (70)
Estimate QE and QF FET Losses (PQE):
POUT f f f
PQE = IQE _ RMS 2 Rds(on)QE + VdsQE (tr + t f ) s + 2 COSS _ QE _ AVG VdsQE 2 s + 2 QgQE VgQE s
VOUT 2 2 2
(71)
PQE 9.3 W (72)
Recalculate the power budget.
PBUDGET = PBUDGET - 2 PQE 6.5 W (73)
12 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Input Capacitance (CIN)
NOTE: The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
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Input Capacitance (CIN) www.ti.com
14 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
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Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com
Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design
we chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for
most applications but maybe adjusted to suit individual layouts and EMI present in the design.
RLF = 1kW (93)
CLF = 330pF (94)
1
fLFP = = 482kHz
2pf RLF CLF (95)
The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency
noise. This pin needs at least 1 F of high frequency bypass capacitance (CBP1). Please refer to figure 1
for proper placement.
CBP1 = 1 mF (96)
The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (RA, RB), for this
design example we are going to set the error amplifier reference voltage (V1) to 2.5 V. Select a standard
resistor value for RB and then calculate resistor value RA.
UCC28950 reference voltage:
VREF = 5 V (97)
Set voltage amplifier reference voltage:
V1 = 2.5 V (98)
RB = 2.37kW (99)
RB (VREF - V1)
RA = = 2.37kW
V1 (100)
Voltage divider formed by resistor RC and RI are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).
Select a standard resistor for RC:
RC = 2.37kW (101)
Calculate RI:
Rc (VOUT - V1)
RI = 9kW
V1 (102)
Then choose a standard resistor for RI:
Rc (VOUT - V1)
RI = 9.09kW
V1 (103)
16 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
Compensating the feedback loop can be accomplished by properly selecting the feedback components
(RF, CZ and CP). These components are placed as close to pin 3 and 4 as possible of the UCC28950.
Calculate load impedance at 10% load (RLOAD):
VOUT 2
RLOAD = = 2.4 W
POUT 0.1 (104)
Approximation of control to output transfer function (GCO(f)) as a function of frequency:
DVOUT R 1 + 2pj f ESRCOUT COUT 1
GCO (f ) = a1 a2 LOAD
DVC RS 1 + 2pj f RLOAD COUT S(f ) S(f )
2
1+ +
2p fPP 2p fPP
(105)
Double pole frequency of GCO(f):
fs
fPP = 50kHz
4 (106)
Angular velocity:
S(f ) = 2p j f (107)
Compensate the voltage loop with type 2 feedback network. The following transfer function is the
compensation gain as a function of frequency (GC(f)). Please refer to Figure 1 for component placement.
DVC 2pj f RF CZ + 1
GC (f ) = =
DVOUT 2pj f CZ CP RF
2pj f (CZ + CP )RI + 1
CZ + CP (108)
th
Calculate voltage loop feedback resistor (RF) based on crossing the voltage (fC) loop over at a 10 of the
double pole frequency (fPP).
fPP
fC = = 5kHz
10 (109)
RI
RF = 27.9kW
fPP
GCO
10 (110)
Select a standard resistor for RF.
RF 27.4kW (111)
Calculate the feedback capacitor (CZ) to give added phase at crossover.
1
CZ = 5.8nF
f
2 p RF C
5 (112)
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Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com
NOTE: It is wise to check your loop stability of your final design with transient testing and/or a
network analyzer and adjust the compensation (GC(f)) feedback as necessary.
60 135
40 90
Phase in Degrees
20 45
Gain in dB
0 0
-20 -45
-40 -90
TvdB(f)
-60 -135
?Tv(f)
-80 -180
100 1000 10000 100000
Frequency in Hz
To limit over shoot during power up the UCC28950 has a soft-start function (SS, Pin 5) which in this
application was set for a soft start time of 15 ms (tSS).
t ss = 15ms (117)
t SS 25 mA
CSS = 123nF
V1 + 0.55 (118)
18 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
NOTE: The 2.25 factor of the tABSET equation was derived from empirical test data and may vary
based on individual design differences.
2.25
t ABSET = 346ns
f R 4 (122)
The resistor divider formed by RDA1 and RDA2 programs the tABSET, tCDSET delay range of the UCC28950.
Select a standard resistor value for RDA1.
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Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com
NOTE: Once you have a prototype up and running it is recommended you fine tune tABSET at light
load to the peak and valley of the resonance between LS and the switch node capacitance. In
this design the delay was set at 10% load. Please refer to Figure 5.
Set t ABSET
at resonant tank Peak and Valley
t ABSET = t 1 - t 0 t ABSET = t 4 - t 3
QB d
QA g
Miller Plateau
tMILLER = t 2 - t1
QB g Miller Plateau
t MILLER = t 5 - t 4
t0 t1 t2 t3 t4 t5
20 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
The initial starting point for the QC and QD turn on delays (tCDSET) should be initially set for the same delay
as the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays
(tCDSET) by properly selecting resistor RDELCD (Pin 7).
t ABSET = t CDSET (129)
Resistor RDELCD programs tCDSET:
(t ABSET - 5ns) (0.15 V + VADEL 1.46) 103 1
RDELCD = 30.4kW
ns 5 1A (130)
Select a standard resistor for the design:
RDELCD = 30.1kW (131)
NOTE: Once you have a prototype up and running it is recommended to fine tune tCDSET at light
load. In this design the CD node was set to valley switch at roughly 10% load. Please refer
to Figure 6. Obtaining ZVS at lighter loads with switch node QDd is easier due to the
reflected output current present in the primary of the transformer at FET QD and QC
turnoff/on. This is because there was more peak current available to energize LS before this
transition, compared to the QA and QB turnoff/on.
Set t CDSET
at resonant tank Peak and Valley
t CDSET =t 1
- t0 t CDSET =t 4
- t3
QD d
QC g
Miller Plateau
t MILLER =t 2 -t1
QD g Miller Plateau
t MILLER =t 5
-t4
t 0 t1 t 2 t 3 t4 t 5
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Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com
There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of
FET QE after FET QB turnoff (tBESET). A good place to set these delays is 50% of tABSET. This will ensure
that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it
will cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on
FETs QE and QF.
t AFSET = tBESET = t ABSET 0.5 (132)
The resistor divider formed by RCA1 and RCA2 programs the tAFSET and tBESET delay range of the UCC28950.
Select a standard resistor value for RCA1.
RDELEF =
(t AFSET 0.5 - 4ns ) (2.65 V - VADELEF 1.32 ) 103 1
14.1kW
ns 5 1A (137)
22 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
NOTE: The change in magnetizing current on the primary dILMAG contributes to slope compensation.
VIN (1 - DTYP )
DILMAG = = 234mA
LMAG fs (144)
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Setting Up the Current Sense Network (CT, RS, RRE, DA) www.ti.com
To help improve noise immunity VSLOPE is set to have a total slope that will equal 10% of the maximum
current sense signal (0.2 V) over one inductor switching period.
0.04 V
VSLOPE1 = 0.2 V fS =
ms (145)
dILOUT
a1 2 - dILMAG RS fS
VSLOPE2 = 1mV
=
a2 (1 - DTYP ) ms (146)
If VSLOPE2 < VSLOPE1 set VSLOPE = VSLOPE1
If VSLOPE2 VSLOPE1 set VSLOPE = VSLOPE2
2.5 V 103 W
RSUM = 125.4kW
VSLOPE 0.5 ms (147)
Select a standard resistor for RSUM.
RSUM = 127kW (148)
To increase efficiency at lighter loads the UCC28950 is programmed (Pin 12, DCM) under light load
conditions to turn off the synchronous FETs on the secondary side of the converter (QE and QF). This
threshold is programmed with resistor divider formed by RE and RG. This DCM threshold needs to be set
at a level before the inductor current goes discontinues. The following equation sets the synchronous
rectifiers to turnoff at roughly 15% load current.
POUT 0.15 DILOUT
+ RS
VOUT 2
VRS = = 0.29 V
a1 a2 (149)
Select a standard resistor value for RG.
RG = 1kW (150)
Calculate resistor value RE.
RG (VREF - VRS )
RE = 16.3kW
VRS (151)
Select a standard resistor value for this design
RE = 16.9kW (152)
24 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
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+
+
+
+
+
+
+
NOTE: It is recommended to use an RCD clamp to protect the output synchronous FETs from over
voltage due to switch node ringing. This RCD clamp is formed by diodes D4, D6 and resistor
R6, R8 and R9 and capacitor C1 in the power stage schematic, .
26 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com Setting Up the Current Sense Network (CT, RS, RRE, DA)
96%
95%
94%
93%
92%
91%
90%
89%
88%
87%
83%
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Full bridge gate drives and primary switch nodes (QBd and QDd) at VIN = 390 V, IOUT = 5 A.
Valley Switching
QB d/Q4 d
QD d/Q3 d Valley Switching
Q3
Q4 g g
0V 0V
QA/Q1 = on QC/Q2 = on QC/Q2 = off
QA/QB = off
Figure 10. Q4g Q4d, VIN = 390 V, IOUT = 5 A Figure 11. Q3g Q3d, VIN = 390 V, IOUT = 5 A
NOTE: The gate drives look slightly different than Figure 5 and Figure 6. This is because they were
driven with 1:2 gate drive transformers instead of 1:1. At 10% load the primary switch nodes
were valley switching
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Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 10 A
Q4 g Q3 g
ZVS
0V
QB/Q4 = off QD/Q3 = off
QB/Q4 = on QD/Q3 = on
0V 0V
QA/Q1 = on QC/Q2 = on
QA/QB = off QC/Q2 = off
Figure 12. Q4g Q4d, VIN = 390 V, IOUT = 10 A Figure 13. Q3g Q3d, VIN = 390 V, IOUT = 10 A
NOTE: Switch node QBd/Q4d is valley switching and node QDd/Q3d has achieved ZVS. Please refer
to Figure 12 and Figure 13. It is not uncommon for switch node QDd/Q3d to obtain ZVS
before QBd/Q4d. This is because during the QDd/Q3d switch node voltage transition, the
reflected output current provides immediate energy for the LC tanking at the switch node.
Where at the QBd/Q4d switch node transition the primary has been shorted out by the high
side or low side FETs in the H bridge. This transition is dependent on the energy stored in LS
and LLK to provide energy for the LC tanking at switch node QBd/Q4d making it take longer to
achieve ZVS.
Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 25 A
ZVS Achieved
QB d/Q4 d
QD d/Q3 d
Q3 g
ZVS
Q4 g
QB/Q4 = off QD/Q3 = off
QB/Q4 = on QD/Q3 = on
0V 0V
QA/Q1 = on QC/Q2 = on
QA/QB = off QC/Q2 = off
t ABSET t CDSET
Figure 14. Q4g Q4d, VIN = 390 V, IOUT = 25 A Figure 15. Q3g Q3d, VIN = 390 V, IOUT = 25 A
NOTE: When the converter is running at 25 A both switch nodes are operating into zero voltage
switching (ZVS). It is also worth mentioning that there is no evidence of the gate miller
plateau during gate driver switching. This makes sense because the voltage across the drain
and source of FETs QA through QD has already transition before the gate drives have
transitioned.
28 UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report SLUA560B September 2010 Revised October 2010
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www.ti.com References
Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 50 A
ZVS
QB d /Q4 d
QD d/Q3 d
Q3 g
ZVS
Q4 g
QB/Q4 = off QD/Q3 = off
QB/Q4 = on QD/Q3 = on
0V 0V
QA/Q1 = on QC/Q2 = on
QA/QB = off QC/Q2 = off
t ABSET t CDSET
Figure 16. Q4g Q4d, VIN = 390 V, IOUT = 25 A Figure 17. Q3g Q3d, VIN = 390 V, IOUT = 25 A
12 References
1. Bill Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM
Controller Unitrode Application Note SLUA107, 9/5/1999
2. Lazlo Balogh, Design and Application Guide for High Speed MOSFET Gate Drive Unitrode Power
Supply Design Seminar 1400, Topic 2, 2001
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DSP dsp.ti.com Industrial www.ti.com/industrial
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Power Mgmt power.ti.com Transportation and www.ti.com/automotive
Automotive
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