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Chapter 1 Introduction
Original Authors:
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 1
Lienig
Chapter 1 Introduction
KLMH
1.1 Electronic Design Automation (EDA)
1.2 VLSI Design Flow
1.3 VLSI Design Styles
1.4 Layout Layers and Design Rules
1.5 Physical Design Optimizations
1.6 Algorithms and Complexity
1.7 Graph Theory Terminology
1.8 Common EDA Terminology
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 2
Lienig
1.1 Electronic Design Automation (EDA)
KLMH
Moores Law
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 3
Lienig
1.1 Electronic Design Automation (EDA)
KLMH
Impact of EDA technologies on
overall IC design productivity and
IC design cost
100.0
80.0
55.7
79.0 46.7
60.0 42.5 46.6
56.4 33.6 35.2 40.5
40.0 40.7 31.1 34.0
27.2 29.4
29.6 21.4
20.0 44.9 39.8 43.5
32.9 29.5 32.6 36.9 31.7
26.3 25.2 27.0 23.1
15.7 20.3 19.4 16.9
0.0
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
Total HW
Total HW Engineering
Engineering Costs
Costs +
+ EDA
EDA Tool
Tool Costs
Costs Total SW
Total SW Engineering
Engineering Costs
Costs +
+ ESDA
ESDA Tool
Tool Costs
Costs
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 4
Lienig
1.1 Electronic Design Automation (EDA)
KLMH
Time Period Circuit and Physical Design Process Advancements
1965 -1975 Layout editors, e.g., place and route tools, first developed for
printed circuit boards.
1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated
algorithms.
1990 -2000 First over-the-cell routing, first 3D and multilayer placement and
routing techniques developed. Automated circuit synthesis and
routability-oriented design become dominant. Start of parallelizing
workloads. Emergence of physical synthesis.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 5
Lienig
1.2 VLSI Design Flow
KLMH
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design
Physical Design
Clock Tree Synthesis
Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication
Timing Closure
Chip
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 6
Lienig
1.3 VLSI Design Styles
KLMH
Layout editor
Menu Bar Toolbar
Drawing Tools
Layer Palette
Locator
Cell Browser
Layout Windows
Status Bar
2011 Springer
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 7
Lienig
1.3 VLSI Design Styles
KLMH
Common digital cells
IN1 IN2 OUT IN1 IN2 OUT IN OUT IN1 IN2 OUT IN1 IN2 OUT
0 0 0 0 0 0 0 1 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1 0 1 1 0 0
0 1 0 0 1 1 1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1 1 1 0 1 1 0
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 8
Lienig
1.3 VLSI Design Styles Vdd Contact
Metal layer
KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor
GND n-type
transistor
GND
IN1
OUT
IN2
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 9
Lienig
1.3 VLSI Design Styles Vdd Contact
Metal layer
KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor
GND n-type
transistor
GND
IN1
OUT
IN2 Power (Vdd)-Rail
Ground (GND)-Rail
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 10
Lienig
1.3 VLSI Design Styles
KLMH
Standard cell layout with Standard cell layout using
a feedthrough cell over-the-cell (OTC routing
A A
VDD VDD
GND
A GND
Lienig
1.3 VLSI Design Styles
KLMH
Layout with macro cells
RAM
PLA
VDD
RAM
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 12
Lienig
1.3 VLSI Design Styles
KLMH
Field-programmable gate
array (FPGA)
Logic Element
LB LB LB
Switchbox Connection
SB SB
LB LB LB
SB SB
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 13
Lienig
1.4 Layout Layers and Design Rules
KLMH
Layout layers of an inverter cell
with external connections
Inverter Cell
Vdd
Metal2 Contact
Metal1 Via
polysilicon
p/n diffusion
GND
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 14
Lienig
1.4 Layout Layers and Design Rules
KLMH
Categories of design rules
Size rules, such as minimum width: The dimensions of any component (shape),
e.g., length of a boundary edge or area of the shape, cannot be smaller than given
minimum values. These values vary across different metal layers.
Separation rules, such as minimum separation: Two shapes, either on the same
layer or on adjacent layers, must be a minimum (rectilinear or Euclidean diagonal)
distance apart.
Overlap rules, such as minimum overlap: Two connected shapes on adjacent layers
must have a certain amount of overlap due to inaccuracy of mask alignment to
previously-made patterns on the wafer.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 15
Lienig
1.4 Layout Layers and Design Rules
KLMH
Categories of design rules
a
c
Minimum Width: a
Minimum Separation: b, c, d
e
Minimum Overlap: e
d
b
Lienig
1.5 Physical Design Optimizations
KLMH
Types of constraints
Technology constraints enable fabrication for a specific technology node and are
derived from technology restrictions. Examples include minimum layout widths and
spacing values between layout shapes.
Electrical constraints ensure the desired electrical behavior of the design. Examples
include meeting maximum timing constraints for signal delay and staying below
maximum coupling capacitances.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 17
Lienig
1.6 Algorithms and Complexity
KLMH
Runtime complexity
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 18
Lienig
1.6 Algorithms and Complexity
KLMH
Runtime complexity
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 19
Lienig
1.6 Algorithms and Complexity
KLMH
Heuristic algorithms
Deterministic: All decisions made by the algorithm are repeatable, i.e., not random.
One example of a deterministic heuristic is Dijkstras shortest path algorithm.
Stochastic: Some decisions made by the algorithm are made randomly, e.g., using a
pseudo-random number generator. Thus, two independent runs of the algorithm will
produce two different solutions with high probability. One example of a stochastic
algorithm is simulated annealing.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 20
Lienig
1.6 Algorithms and Complexity
KLMH
Heuristic algorithms
Problem Instance
Constructive Algorithm
Initial Solution
Iterative Improvement
no
Termination
Criterion Met?
yes
Return Best-Seen Solution
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 21
Lienig
1.7 Graph Theory Terminology
KLMH
Graph Hypergraph Multigraph
b b b
a e
f
a a
c d
e g f
d c c
Lienig
1.7 Graph Theory Terminology
KLMH
Directed graphs with cycles Directed acyclic graph
c f c f
a a
a b
b d g b d g
e e
Lienig
1.7 Graph Theory Terminology
KLMH
Undirected graph with maximum node degree 3 Directed tree
b a
a
f b c d
c
e g e f g h i j k
d
Lienig
1.7 Graph Theory Terminology
KLMH
Rectilinear minimum spanning Rectilinear Steiner minimum
tree (RMST) tree (RSMT)
b (2,6) b (2,6)
Steiner point
c (6,4) c (6,4)
a (2,1) a (2,1)
Lienig
1.8 Common EDA Terminology
KLMH
Netlist
2011 Springer
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 26
Lienig
1.8 Common EDA Terminology
KLMH
Connectivity graph
a x a x
N3 N5
N1 N2 z c z c
N4
y
b b y
Lienig
1.8 Common EDA Terminology
KLMH
Connectivity matrix
a b x y z c
a 0 0 1 1 0 0
a b 0 0 1 1 0 0
x
x 1 1 0 2 1 0
N3 N5
N1 N2 z c y 1 1 2 0 1 0
N4
z 0 0 1 1 0 1
y
b c 0 0 0 0 1 0
Lienig
1.8 Common EDA Terminology
KLMH
Distance metric between two points P1 (x1,y1) and P2 (x2,y2)
n n
n
d = x2 x1 + y2 y1
n = 1: Manhattan distance d M ( P1 , P2 ) = x2 x1 + y 2 y1
P1 (2,4) dM = 7
dE = 5
dM = 7 P2 (6,1)
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 29
Lienig
Summary of Chapter 1
KLMH
IC production experienced huge growth since the 1960s
Exponential decrease in transistor size, cost per transistor, power per transistor, etc
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1: Introduction 30
Lienig