EXPERIMENT 8

CPLD

I. OBJECTIVES

a. To introduce a CPLD (Complex Programmable Logic Device) and the devices.

b. To introduce Altera Max+Plus II
c. Students are able to design a logical circuit using a CPLD, to do the simulation and to
program a CPLD.

II. SCOPE

A. Theory

a. Board FTP-3 Plus

In this experiment, we will use FPT-3 as the development board produced by

Leap Electronic Co.. This FPT-3 is a development board that has a CPLD
(Complex Programmable Logic Device) for the type EPM7064LC-10, and there
are some devices that have connected to the pins of the CPLD:
1. Seven segment (6)
2. LED (8)
3. Loudspeaker atau buzzer (1)
4. Motor driver (1)
5. DIP switch (8 pins)
6. Push button switch (4)
7. External input / output (34 pins)
8. Etc

EPM7064S CPLD Specification

Specification EPM7064S
The number of gades 1.250
The number of macro cels 64
Logic array block 4
Maximum I/O pins 68
tPD (ns) 5
tSU (ns) 2.9
tFSU (ns) 2.5
tCO1 (ns) 3.2
fCONT (MHz) 175.4)

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 Pin configruation of a CPLD EPM7064S-10
Pin Connect Pin Connect
3 15 23 35 VCC 10 22 30 42 GND
4 LED1 16 DIP1
5 LED2 17 DIP2
6 LED3 18 DIP3
8 LED4 19 DIP4
9 LED5 20 DIP5
11 LED6 21 DIP6
12 LED7 24 DIP7
14 LED8 25 DIP8
31 7SEGIO1 27 STEP2
33 7SEGIO2 28 STEP3
34 7SEGIO3 29 STEP4
36 7SEGIO4 40 BZ
37 7SEGIO5 43 CLK
39 7SEGIO6 41 SW1
7 TDI 44 SW2
38 TDO 1 SW3
13 TMS 2 SW4
32 TCK 26 STEP1

Figure 8.1

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 The devices configuration:
1. Power supply

Figure 8.2

2. Clock Pulse or Oscillator

4 MHz X-tal is used

Figure 8.3

3. DIP switch

Figure 8.4

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 4. Push button Switch

Figure 8.5

5. LED

Figure 8.6

6. Stepper motor

Figure 8.7

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 7. Seven segment

Figure 8.8

8. Loudspeaker or buzzer

Figure 8.9

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 9. External Connector

Figure 8.10

b. Software MAX Plus II

To create a program we are using MAX Plus II 10.2. It is used for

programming the CPLD and simulating the program.
Initial Display

Figure 8.11

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 B. Reference

1. Floyd., Digital fundamentals, Pearson International,2006, New Jersy.

2. LEAP ELECTRONIC CO., LTD, FPT-3 Plus Operating Manual_en.pdf
3. Altera Max+Plus II HELP

III. DEVICES

Board FPT-3 Plus

Program Max Plus

IV. INSTRUCTION OF LABORATORY

A. Pocedure

1. Run MAX+plus II 10.2 BASELINE.

2. Click MAX+plus II => Graphic Editor.
3. The the following interface will appear:

Figure 8.12

4. Save with any name. (It is recommended to create a new folder to save the
project)
5. Then click File => Project => Set Project to Current File.
6. Then click Assign => Device. Then choose the Device Family to MAX7000S.
Then in the Devices dialog box type: EPM7064SLC44-10. (This device name
will not be found below the Devices dialog box. To do so the user should type
the devices name then click OK. Then reopen Assign => Device, then the
device name will appears)

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 Figure 8.13

7. Then click Symbol => Enter Symbol. Then the following box will appear:

Figure 8.14

8. Then in Symbol Libraries choose: c:\maxplus2\max2lib\prim. Then the

following box will appear:

Figure 8.15

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 9. Choose and2, or2, xor, not gates. (The number 2 of and and or determines the
number of the inputs)

Figure 8.16

10. Then reclick Symbol => Enter Symbol. After exiting the dialog box, on the
Symbol Name box type: input, then ENTER. INPUT pin should be appear on
the graphic editor.

Figure 8.17

11. Then reinsert the input pins according to the total input pins. Then connect
those pins to the gates.
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 Figure 8.18

12. Then reclick Symbol => Enter Symbol. After exiting the dialog box, on the
Symbol Name box type: output to display the output pin, then press ENTER.
So there should be OUTPUT Pin on the graphic editor then connect every
output to the gates.
13. Then change the name of the every pins by double-clicking the PIN_NAME.
(The name of each pins cannot be same)

Figure 8.19

14. Then right click on the pin, then click Assign => Pin/Location/Chip.

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 Figure 8.20

15. Then a dialog box should appear. On the dialog box, click Pin and choose the
number of the pin connected to the DIP SWITCH (see the picture). Then
choose Pin Type to input. Then reclick Add. Do the similar for the output. For
the output, choose the pins connected to the LED.

Figure 8.21

16. Then compile the program by clicking File => Project => Save & Compile.

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 Figure 8.22

To do the simulation of your program, follow the instructions below.

1. Click MAX+plus II => Waveform Editor.

Figure 8.23

2. Right click on the box Name:. Then choose Enter Nodes from SNF.

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 Figure 8.24

3. Then click List and the nodes you have created will appear on the box Avaible
Nodes & Groups. Then click =>. Klik OK.
4. Then the following display will appear. To change the value, block the
segments then change the value on the left side.

Figure 8.25

5. Then save the waveform editor.

6. Click MAX+plus II => Simulator. Then click start without closing the
Waveform Editor. Then successful message will appear. Click OK and the
simulation can be seen from the Waveform Editor.

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 Figure 8.26

To program the circuit that you have created to the device, do the following
steps.
1. Make sure that the parallel cable on your computer has been connected to the
FTP 3 Plus board.
2. Click MAX+plus II => Programmer.
3. Then the Hardware Setup dialog box will appear. Choose ByteBlaster(MV).
Click OK. (To open the Hardware Setup dialog box click Options =>
Hardware Setup)

Figure 8.27

4. Then on the Programmer dialog box, click Program.

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 Figure 8.28

5. Then a message showing the programming has been successfully done will
appear.

B. Final Reports requirement for minimum grade

The points below should be explained and developed in the digital system final
reports. State at least 5 conclusions in the end of the final reports.
CPLD explanation
The differences between SPLD and CPLD
Steps to design a circuit
Steps to do the simulation
Do the simulation of the following circuits:
o Multiplexer
o Demultiplexer
o Decoder
o Half Adder
o Full Adder
o Full Subtractor

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