Design Tip

Simulating PLL reference spurs

By Steve Williams and Tony Caviglia
Spurious levels on the output of a phase-
locked loop (PLL) that generates a carrier 1
signal are an important specication in many M
RF systems. Spurs may come from a variety VCONTROL dB fOUT
of sources, but one of the most common is PFD CP VCO fOUT
fREF
the PLLs reference clock. This spur is often
referred to as the reference spur, or reference 1
fOUT fREF fOUT + fREF
feedthrough. The existence of this spur is not fREF
surprising because many of the PLLs compo- f
nents including the phase-frequency detector
(PFD) and charge pump (CP) are clocked at
the reference frequency (fref). Spurs from these Figure 1. Typical PLL block diagram and fout spectrum.
sources can be seen in the PLLs output spec-
trum, offset from the PLLs output frequency
Behavioral Behavioral
(fout) by fref as shown in Figure 1. The spurs VCONTROL VCONTROL
are caused by non-idealities in the PLL compo- fREF PFD CP VCO & 1 fREF PFD CP DLL
nents such as mismatched propagation delay in M
the PFD and CP, charge injection and current
mismatches in the CP, and leakage current on
the VCO tuning node (VCONTROL).
Running a transient simulation, waiting
for the loop to settle, and measuring the Figure 2. Two improved simulation approaches using behavioral modeling.
spectrum of fout can simulate a PLLs reference
spurs. Simulation by this method can be time 0.00
consuming and inefcient, especially if the -10.0
feedback ratio (M) of the PLL is large. This -20.0
is because the simulator needs to calculate its -30.0
time step small enough to accurately capture
-40.0
fout. If M is large, the time step will be small -60.05 dBc
compared to the settling time constant of the -50.0
(dB)

PLL, resulting in a long simulation run time to
lock the PLL. In addition, a larger M results in
more fout cycles that are needed to capture the
fout spectrum including the reference spurs.
If the PLL components have sufcient
power supply rejection, we can assume the
reference spurs on fout are dominated by direct
modulation of the VCO input. This allows
us to replace some of the components of
the PLL with behavioral models to decrease
simulation run time. Two improved methods
to evaluating PLL reference spurs caused by
direct modulation of VCONTROL are shown in
Figure 2. Both methods use behavioral models
to eliminate the high-frequency edges of fout.
This requires the simulator to calculate fewer
time steps, resulting in a reduction in transient
simulation run time. Another advantage of
the improved simulation approaches is that
the circuitry reduction makes the PLL easier
to simulate in a periodic steady-state (PSS)
simulator such as SpectreRF. Use of a PSS
simulator further reduces the simulation run
time, and makes accurate determination of the
spectrum trivial.
Using the DLL approach, the fout signal
is not directly available and another method
needs to be used to determine the fout spec-
trum. If we assume that the modulation of
-60.0
-70.0
-80.0
-90.0
-100
-110
1.7G 1.8G 1.9G
Figure 3. Simulation of VCO spectrum to verify spur calculation.
VCONTROL results in only a small phase error
on the VCO output (narrowband FM), we can
use the spectrum of VCONTROL to calculate the
spectrum of fout. KVCOvn
Spur in dBc = 20 . log10 2 fn (1)
where n = peak voltage measured at n in
the spectrum of VCONTROL. This equation
can be tested by simulation of an open loop
behavioral VCO with two 1 mV peak sine
waves with frequencies f1=100.586 MHz and
f2 = 200.195 MHz added to VCONTROL. The VCO
gain is KVCO = 200 MHz/V, and the VCO center
frequency fVCO = 2.0 GHz. Using equation (1)
with vn = 1 mV, and fn = f1 or fn = f2 yields
spur levels that match the simulation results
shown in Figure 3.
In the future, when increased computing
power is available, simulating any architec-
ture PLL to evaluate reference spurs may be
-66.03 dBc
2.0G 2.1G 2.2G 2.3G
Frequency (Hz)
trivial. With present computing limitations,
the improved simulation approaches described
here reduce the number of transient simulator
time steps required to evaluate a PLLs refer-
ence spur levels. This simplication results in
a reduction in simulation run time. A further
reduction in simulation time can be achieved
by using a PSS simulator, and a basic calcula-
tion to evaluate PLL output spectrum based on
the VCO control voltage spectrum.
ABOUT THE AUTHORS
Steve Williams is a principal analog/RF
IC design engineer and Tony Caviglia is
an analog/RF IC architect. Both are with
Cadence Design Systems Cadence Design
Services in Columbia, MD.

98 www.rfdesign.com March 2006