A.

Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16

1. a). Define Compile.

b). Define cross compiler
c). Define preprocessor
d). Define interpreter.
e) define symbol table
f). What is boot strapping?
g). What is the role of lexical analyzer?
i). What is the role of syntax analyzer?
j). What is lexeme, pattern, token?
k). What is left recursion? Eliminate left recursion from the grammar
AAc | Aad | bd |
l). Defferentiate compile and interpreter.
m). What is ambiguous grammar?
n).What is parsing?
o). What is back tracking.
p). What is top down parsing
q). What are the problems with top down parsers?
r). What is left factoring?

2. Explain phases of compiler with example. [6M]

3. Explain input buffering. (6M)

4. Design lexical analyzer for the grammar (6M)

Sif ( C ) S else S | A
AID=E
EE+T | T
TT*F | F
FID | NUM
CID RELOP ID
5. Construct recursive descent parser for following grammar. (6M)
EE+T | T
TT*F | F
FID | NUM | (E)
6. Explain about lex compiler. (6M)
7. Write down the rules for finding FIRST and FOLLOW sets. (6M)
Find first and follow sets for the following grammar
ETE
E+TE |
TFT
T+*FT |
FID | NUM |(E)
 A.Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16

[6 M]

1 a).Design a combinational circuit using a PROM. The circuit should accept 3-bit binary
number and generates its equivalent XS-3 code.

b).Design a combinational circuit using a PLA. The circuit should accept 3-bit binary number
and generates its equivalent XS-3 code.

2. a).What is the function of Multiplexer [4M]

b). Define PLD.
c). How can we implement combinational logic with a decoder
d). what is the function and truth table of Half subtractor
 A.Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16

1. a).Design a combinational circuit for 4-bit binary to gray code Convertor. [6 M]

b).Design a combinational circuit for 4-bit magnitude comparator.

2. a).What are the different types of ROM [4 M]

b). Draw the logic diagram of half subtractor
c). How many dont cares are there in a BCD adder
d). Give the analysis procedure of combinational circuits
 A.Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16

1. a). Design A combinational circuit is defined by the following three functions: [6 M]

F1=xy+xyz

F2=x+y

F3=xy+xy

Design the circuit with decoder and external gates.

b).Construct a block diagram for 532 decoder using four 38 decoders and one 24 decoder.

2. a).Define Combinational circuit [4 M]

b). what is carry look ahead adder
c). what is the function and truth table of Full subtractor
 A.Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16
d). what is the function of De-multiplexer

1. a).Design a combinational circuit for BCD-to-7-segment decoder. [6 M]

b).Design a logic diagram for full subtractor circuit using two half subtractor circuits and
necessary gates.

2 a).What is the function of Encoder [4 M]

b). Give the design procedure of combinational circuits
c). Draw the logic diagram of fullsubtractor
d). what is binary parallel adder
 A.Y: 2016-17
Department of Computer Science and Engineering
Roll No.
BAPATLA ENGINEERING COLLEGE, BAPATLA
(AUTONOMOUS)
First Assignment Examination Marks
Class: III/IV B.Tech.(CSE) Sec - A,B,C1stSem Max.marks:10m.
Subject: CD(14CS602) Time: 50mins.
Date: 29-12-16

1. a).Implement the following Boolean function with multiplexer [6 M]

F(A,B,C,D)=m(0,1,3,4,8,9,15).

b).Design a logic diagram for Look-Ahead carry generator.

2. a).Draw the block diagram of Decoder with enable input [4 M]

b). Give truth table of fullsubtractor
c). Define PLA.
d). Differentiate RAM and ROM