1. Assume you are improving upon an existing computer design.

If your design decreases the clock period and

CPI by (20 + 5*) %, but doubles the number of instructions that are executed, how much faster is your new
design than the original computer?

2. Suppose that we want to enhance the processor used for web serving. The new processor is (5+) times faster
on computation in web serving application than the original processor. Assuming that the original processor
is busy with computation 60% of the time and is waiting for I/O 40% of the time. What is the overall speedup
gained by incorporating the enhancement?

3. Assuming that the opcode for add immediate (addi) is 8d, The instruction code for instruction below
addi $t0, $s5, -(2) (in hexadecimal) is

1. Assume that the 5 stages in the execution cycle have delay as mentioned below:
IF: (+3) ns; ID: (+2) ns; EX: (+1) ns; MEM: (+3) ns; WB: (+2) ns. If a program with 100 instructions
is executed on a pipelined and non-pipelined processor, what is the speed-up for a pipelined processor when
compared to a non-pipelined processor? (Neglect the pipeline register Delays). (Answer should be accurate
up to 2 decimal points)

2. In a program there are 40 R-type instructions, 20 load/store instructions and 40 conditional branch
instructions. This program runs on a 5-stage pipelined processor with always taken predictor, which is
(5*+5) % accurate. Find the total number of clock cycles to execute the above program. (Assume that
branch outcomes are determined at the output of Ex stage and there are no data hazards)

3. Suppose design team has made the following observations for a program
Frequency of all Floating Point (FP) operations = 20%
Average CPI of all Floating Point operations = 5.0
Average CPI of other instructions = 1.5
Frequency of Floating Point Square Root (FPSQR) operations= 5%
CPI of FPSQR = 20
What is speedup achieved if CPI of FPSQR is reduced to (1+). (Answer should be accurate up to 3 decimal
points)

1. What decimal number is represented by the 32-bit IEEE floating point number 0x4A60000?

2. Given 32-bit address, byte addressable memory, word size of 32 bits, direct mapped cache with 2(+6) blocks
and block size as 64-bits; The total size of cache (including the data, tag and valid) is

3. Suppose that in 1000 memory references there are (40+ *10) misses in the first-level (L1) cache and 20 misses in
the second level (L2) cache. Assume the miss penalty from the L2 cache to main memory is 200 clock cycles, the miss
penalty from L1 cache to L2 cache is 10 clock cycles, hit time of L1 is 1 clock cycle, and there are 1.5 memory
references per instruction. (Ignore the impact of writes). Assuming the base CPI of 1.0 without any memory stalls,
Find the total actual CPI.

1. For the code sequence below with initial value of $s1 as 0x00000008, show the scheduling for static two issue
pipelined processor using loop unrolling. In two-issue processor one of the instructions can be ALU or branch and the
other can be load or store. The scheduled code should complete execution in least number of clock cycles. Assume
forwarding is allowed. You can use additional temporary registers if necessary. [4]
Loop: lw $t0, 0($s1)
addu $t0, $t0, $s2
sw $t0, 0($s1)
addi $s1, $s1,4
bne $s1, $zero, Loop
2. A virtual address is specified by 24 bits and physical address is specified by (+16) bits. Assume each page
contains 1K words, word size is 32-bits and main memory is byte addressable. Determine the total number
of pages that the main memory can accommodate. [2]

1. Assuming that the cache has an access time of 2ns and the memory an access time of (10+) ns. What is
the required cache hit rate to attain an average access time of 5ns?

2. 2( +9) bytes of data are organized in a 4-way mapped set associative cache, which has a block size equal to
two words. Assuming that the main memory is byte addressable, word size as 16-bits and address size as
32-bits; the number of sets in this cache is equal to

3. Represent the (.5625) in binary floating point single precision format (IEEE-754). (Represent your
answer in hexadecimal)