FPGA INSIDE

LUT
Switching matrix
CLB
FPGA
FPGA Programing

3td Oct 2016 EEE F348 FPGA Based System Design Laboratory
 Implementation Technologies For Digital Design

Performance comparison
MAX MIN
Full Custom

Standard Cell

Gate Array

CPLD (Complex Programmable Logic Device)

FPGA (Field-Programmable Gate Array)

ASIP

DSP MIN MAX

GPP Speed of operation Power consumed

Time to market Flexibility
3td Oct 2016 EEE F348 CostDesign
FPGA Based System
Laboratory
 FPGA Internal

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
FPGA Internal: LUT

Can you implement the following?

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
FPGA Internal: LUT

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
FPGA Internal: LUT

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: LUT

Implement the circuit with 3 i/p LUTs.

Compare the memory size with 9 i/p LUT

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
FPGA Internal: LUT

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: LUT
Can U implement this 2x4 decoder with two 3 input 2 output LUTs?

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: LUT

How we can have programmable connection?

3td Oct 2016 EEE F348 FPGA Based System Design
Laboratory
 FPGA Internal: LUT

Can I feed a0, a1 selectively from D0, D1, P4 or P5? SWITCH MATRIX
3td Oct 2016 EEE F348 FPGA Based System Design
What should be in the box?
Laboratory
FPGA Internal: SWITCH MATRIX

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: SWITCH MATRIX

To have this decoder how the switch matrix need to be programed?

3td Oct 2016 EEE F348 FPGA Based System Design
Laboratory
FPGA Internal: SWITCH MATRIX

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: SWITCH MATRIX

Can U program the switch matrix?

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
FPGA Internal: SWITCH MATRIX

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: CLB

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: CLB

Implement the
functionality .

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA Internal: CLB

Implement the functionality withoutLaboratory

FF.
3td Oct 2016 EEE F348 FPGA Based System Design
 FPGA

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA: Programing

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA: Programing

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 FPGA: Programing

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 A Bit stream size is fixed.

All slides/figures are taken from slides of CS G553 course prepared by Dr. A. Amlin Prince

You can view the two videos based on which the presentation is prepared from following link:

https://drive.google.com/drive/folders/0B4WM559D3fzyeFRabXg2WjRHWmM?usp=sharing

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
 LAB 11
HARDWARE DEBUGGING USING VIO

3td Oct 2016 EEE F348 FPGA Based System Design

Laboratory
3td Oct 2016 EEE F348 FPGA Based System Design
Laboratory
3td Oct 2016 EEE F348 FPGA Based System Design
Laboratory