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ECEN248 Texas A&M University

Sections: Choi

Introduction to Digital Logic Design

With Verilog Lab

Chapter 1
-Technology, Trends, and Design Flow

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Figure 1.1. A silicon wafer (courtesy of Altera Corp.).

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Table 1.1. A sample of the International Technology Roadmap for Semiconductors.

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Group of 8 logic cells Memory block

Interconnection
wires

Figure 1.2. A field

- programmable gate array chip
(courtesy of Altera Corp.).
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Figure 1.3. The development

process.

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Design concept

Initial design

Simulation Redesign

No
Design correct?

Yes

Successful design

Figure 1.4. The basic design loop.

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Figure 1.5. A digital

hardware system (Part a).

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Figure 1.5. A digital

hardware system (Part b).

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Figure 1.6. A printed circuit board.

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Figure 1.7. Design flow for

logic circuits.

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Implementation

Build prototype

Testing Modify prototype

Yes

No
Correct? Minor errors?

Yes No

Finished PCB Go to A, B, C, or D in Figure 1.7

Figure 1.8. Completion of PCB development.

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ECEN248 Texas A&M University

Sections: Choi

Introduction to Digital Logic Design

With Verilog Lab

Chapter 2
-Logic, Gates, Boolean Expressions, and Hardware Description

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x = 0 x = 1

(a) Two states of a switch

(b) Symbol for a switch

Figure 2.1. A binary switch.

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S
Battery x Light

(a) Simple connection to a battery

S
Power
supply x Light

(b) Using a ground connection as the return path

Figure 2.2. A light controlled by a switch.

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S S
Power
supply x1 x2 Light

(a) The logical AND function (series connection)

x1

Power
supply S Light

x2

(b) The logical OR function (parallel connection)

Figure 2.3. Two basic functions.

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X1
S
Power
supply S X3 Light

X2

Figure 2.4. A series- parallel connection.

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Power
supply x S Light

Figure 2.5. An inverting circuit.

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Figure 2.6. A truth table for the AND and OR operations.

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Figure 2.7. Three- input AND and OR operations.

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x1
x2
x1
x1 x2 x1 x2 xn
x2

xn

(a) AND gates

x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2

xn

(b) OR gates

x x

(c) NOT gate

Figure 2.8. The basic gates.
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x
1
x
2
f = (x + x ) x
x 1 2 3
3

Figure 2.9. The function from Figure 2.4.

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A
1 1 0 1 f
0 0 01 B
0 1 0 1
x2
f = x1 + x1 x2
(a) Network that implements
x 1
x x (
f x x, ) A B 1 0
1 2 1 2

0 0 1 1 0
x 1
0 1 1 1 0 2 0
1 0 0 0 0 1
1 1 1 A
0 1 0

(b) Truth table 1

B
0
1
f
0 Time
(c) Timing diagram

0011 1100
x
1
1 1 0 1
0101 g
x
2

(d) Network that implementsg = x + x

1 2
Figure 2.10. An example of logic networks.
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Figure 2.11. Proof of DeMorgans theorem in 15a.

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x y x y

(a) Constant 1 (b) Constant 0 (e) x y (f) x + y

x y
x x x x x y
z

(c) Variable x (d) x (g) x y (h) xy+z

Figure 2.12. The Venn diagram representation.

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x y x y

z z

(a) x (d) x y

x y x y

z z

(b) y + z (e) x z

x y x y

z z

(c) x ( y + z) (f) x y + x z

Figure 2.13. Verification of the distributive property.

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x y x y

z z x y x y

x y xy z z

yz x y+ x z
x y x y

z z x y

xz xz z

x y + x z+ y z

Figure 2.14. Verification of xy+xz+y z =xy+xz.

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Figure 2.15. A function to be synthesized.

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x1
x2

(a) Canonical sum-of-products

x1
f
x2

(b) Minimal-cost realization

Figure 2.16. Two implementations of a function in Figure 2.15.

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Figure 2.17 Three- variable minterms and maxterms.

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Figure 2.18. A three- variable function.

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x2

f
x3
x1

(a) A minimal sum-of-products realization

x1
x3
f

x2

(b) A minimal product-of-sums realization

Figure 2.19. Two realizations of a function in Figure 2.18.

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x1
x2
x1
x1 x2 x1 x2 xn
x2

xn

(a) NAND gates

x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2

xn

(b) NOR gates

Figure 2.20. NAND and NOR gates.

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x1
x1 x1
x2 x2
x2

(a) x1 x2 = x1 + x2

x1
x1 x1
x2 x2
x2

(b) x1 + x2 = x1 x2

Figure 2.21. DeMorgans theorem in terms of logic gates.

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x1 x1
x2 x2
x3 x3
x4 x4
x5 x5

x1
x2
x3
x4
x5

Figure 2.22. Using NAND gates to implement a sum

- of- products.
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x1 x1
x2 x2

x3 x3
x4 x4
x5 x5

x1
x2

x3
x4
x5

Figure 2.23. Using NOR gates to implement a product- of sums.

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x1

x2 f

x3

(a) POS implementation

x1

x2 f

x3

(b) NOR implementation

Figure 2.24. NOR

- gate realization of the function in Example 2.4.
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x1

f
x2

x3

(a) SOP implementation

x1

f
x2

x3

(b) NAND implementation

Figure 2.25. NAND

- gate realization of the function in Example 2.3.
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Figure 2.26. Truth table for a three- way light control.

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x1
x2
x3

(a) Sum-of-products realization

x3
x2
x1

Figure 2.27. Implementation f

of the function in Figure 2.26.

Fundamentals of Digital Logic Brown-Vranesic (b) Product-of-sums realization

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s x1 x2 f (s, x1, x2)

x1 s

000 0
f x1 0
001 0 f
s x2 1
010 1
x2
011 1
(b) Circuit (c) Graphical symbol
100 0
101 1
110 0 s f (s, x1, x2)
111 1 0 x1

(a)Truth table 1 x2

(d) More compact truth-table representation

Figure 2.28. Implementation of a multiplexer.

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DESIGN ENTRY

Schematic capture Verilog

Synthesis

Figure 2.29. A typical CAD Functional simulation

system.
No
Design correct?

Yes

Physical design

Timing simulation

No
Timing requirements met?

Chip configuration
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x1
x2
f

x3

Figure 2.30. A simple logic function.

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module example1 (x1, x2, x3, f);

input x1, x2, x3;
output f;

and (g, x1, x2);

not (k, x2);
and (h, k, x3);
or (f, g, h);

endmodule

Figure 2.31. Verilog code for the circuit in Figure 2.30.

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module example2 (x1, x2, x3, x4, f, g, h);

input x1, x2, x3, x4;
output f, g, h;

and (z1, x1, x3);

and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);

endmodule

Figure 2.32. Verilog code for a four- input circuit.

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x1
x3

x2
x4

Figure 2.33. Logic circuit for the code in Figure 2.32.

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module example3 (x1, x2, x3, f);

input x1, x2, x3;
output f ;

assign f = (x1 & x2) | (~x2 & x3);

endmodule

Figure 2.34. Using the continuous assignment to specify

the circuit in Figure 2.30.

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module example4 (x1, x2, x3, x4, f, g, h);

input x1, x2, x3, x4;
output f, g, h;

assign g = (x1 & x3) | (x2 & x4);

assign h = (x1 | ~x3) & (~x2 | x4);
assign f = g | h;

endmodule

Figure 2.35. Using the continuous assignment to specify

the circuit in Figure 2.33.

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// Behavioral specification
module example5 (x1, x2, x3, f);
input x1, x2, x3;
output f ;
reg f ;

always @(x1 or x2 or x3)

if (x2 == 1)
f = x1;
else
f = x3;

endmodule

Figure 2.36. Behavioral specification of the circuit

in Figure 2.30.
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// Behavioral specification
module example5 (x1, x2, x3, f);
input x1, x2, x3;
output reg f ;

always @(x1, x2, x3)

if (x2 == 1)
f = x1;
else
f = x3;

endmodule

Figure 2.37. A simpler version of the code in Figure 2.36.

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x1 x2 x1 x2

x3 x3

(a) Function A (b) Function B

x1 x2 x1 x2

x3 x3

(c) Function C (d) Function f

Figure 2.38. The Venn diagrams for Example 2.11.

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x3
x3

x1 x2 x1 x2

x4 x4

(a) (b)

Figure P2.1. Two attempts to draw a four- variable Venn diagram.

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m0 x4

x1 x2 x1 x2

m1
x
m2
x3 3

Figure P2.2. A four- variable Venn diagram.

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x1 1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2.3. A timing diagram representing a logic function.

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1
x1
0

x2 1
0

x3 1
0

f 1
0

Time

Figure P2.4. A timing diagram representing a logic function.

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ECEN248 Texas A&M University

Sections: Choi

Introduction to Digital Logic Design

With Verilog Lab

Chapter 3
-Implementation Technology

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Voltage

V DD

Logic value 1

V 1,min

Undefined

V 0,max

Logic value 0

VSS (Gnd)

Figure 3.1. Logic values as voltage levels.

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x = "low" x = "high"

(a) A simple switch controlled by the input x

Gate

Source Drain
Substrate (Body)

(b) NMOS transistor

VG

VS VD

(c) Simplified symbol for an NMOS transistor

Figure 3.2. NMOS transistor as a switch.

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x = "high" x = "low"

(a) A switch with the opposite behavior of Figure 3.2 a

Gate

Drain Source
VDD
Substrate (Body)

(b) PMOS transistor

VG

VS VD

(c) Simplified symbol for a PMOS transistor

Figure 3.3. PMOS transistor as a switch.

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VD VD = 0 V VD

VG

VS = 0 V
Closed switch Open switch
whenVG = VDD whenVG = 0 V

(a) NMOS transistor

VS = VDD VDD VDD

VG

VD VD VD = VDD
Open switch Closed switch
whenVG = VDD whenVG = 0 V

(b) PMOS transistor

Figure 3.4. NMOS and PMOS transistors in logic circuits.

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VDD

R R
+
5V
- Vf Vf

Vx Vx

(a) Circuit diagram (b) Simplified circuit diagram

x f x f

(c) Graphical symbols

Figure 3.5. A NOT gate built using NMOS technology.

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VDD

Vf

Vx
1

x1 x2 f

0 0 1
Vx
2 0 1 1
1 0 1
1 1 0

(a) Circuit (b) Truth table

x1 x1
f f
x2 x2

(c) Graphical symbols

Figure 3.6. NMOS realization of a NAND gate.

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V DD

x1 x2 f
Vf
0 0 1
Vx Vx 0 1 0
1 2
1 0 0
1 1 0

(a) Circuit (b) Truth table

x1 x1
x2 f x2 f

(c) Graphical symbols

Figure 3.7. NMOS realization of a NOR gate.

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VDD VDD
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Vf

A
Vx1

x1 x2 f

Vx2 0 0 0
0 1 0
1 0 0
1 1 1

(a) Circuit (b) Truth table

x1 x1
f f
x2 x2

(c) Graphical symbols

Figure 3.8. NMOS realization of an AND gate.

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V DD V DD

Vf

x1 x2 f

0 0 0
Vx Vx 0 1 1
1 2

1 0 1
1 1 1

(a) Circuit (b) Truth table

x1 x1
x2 f x2 f

(c) Graphical symbols

Figure 3.9. NMOS realization of an OR gate.

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VDD

Vf

Vx
1
Pull-down network
(PDN)
Vx
n

Figure 3.10. Structure of an NMOS circuit.

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V DD

Pull-up network
(PUN)

Vf

Vx
1
Pull-down network
(PDN)
Vx
n

Figure 3.11. Structure of a CMOS circuit.

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VDD

T1

Vx Vf
x T1 T2 f
T2
0 on off 1
1 off on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.12. CMOS realization of a NOT gate.

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V DD

T1 T2

Vf

Vx
1 T3 x1 x2 T1 T2 T3 T4 f

0 0 on on off off 1
0 1 on off off on 1
Vx
2 T4 1 0 off on on off 1
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.13. CMOS realization of a NAND gate.

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V DD

Vx
1 T1

Vx
2 T2

x1 x2 T1 T2 T3 T4 f
Vf
0 0 on on off off 1
T3 T4 0 1 on off off on 0
1 0 off on on off 0
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

Figure 3.14. CMOS realization of a NOR gate.

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V DD V DD

Vf

Vx
1

Vx
2

Figure 3.15. CMOS realization of an AND gate.

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V DD

Vf

Vx
1

Vx
2

Vx
3

Figure 3.16. The circuit for Example 3.1.

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Vf

Vx
1

Vx
2

Vx
3

Vx
4

Figure 3.17. The circuit for Example 3.2.

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V DD

Vf Vx Vx Vf
1 2

Vx
1
L L H
L H H
H L H
Vx H H L
2

(a) Circuit (b) Voltage levels

Figure 3.18. Voltage levels in the circuit in Figure 3.13.

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x1 x2 f

0 0 1 x1
0 1 1 f
x2
1 0 1
1 1 0

(a) Positive logic truth table and gate symbol

x1 x2 f

1 1 0 x1
1 0 0 f
x2
0 1 0
0 0 1

(b) Negative logic truth table and gate symbol

Figure 3.19. Interpretation of the circuit in Figure 3.18.

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x1 x2 f
Vx Vx Vf
1 2 0 0 0 x1
0 1 0 f
L L L x2
1 0 0
L H L
1 1 1
H L L
H H H
(b) Positive logic
(a) Voltage levels

x1 x2 f

1 1 1 x1
1 0 1 f
x2
0 1 1
0 0 0
(c) Negative logic

Figure 3.20. Interpretation of voltage levels.

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(a) Dual-inline package

VDD

Gnd

(b) Structure of 7404 chip

Figure 3.21. A 7400

- series chip.
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VDD

7404

7408 7432

x1
x2
x3
f

Figure 3.22. An implementation of f = x1x2 + x2x3.

Fundamentals of Digital Logic Brown-Vranesic
Fundamentals of Digital Logic Brown-Vranesic Pin 1
Pin 2 Pin 12
Pin 4 Pin 14
Pin 6 Pin 16
Pin 8 Pin 18
Pin 19
Pin 3 Pin 11
Pin 5 Pin 13
Pin 7 Pin 15

Figure 3.23. The 74244 buffer chip.

Pin 9 Pin 17
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Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Figure 3.24. Programmable logic device as a black box.

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x1 x2 xn

Input buffers
and
inverters

x1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm

Figure 3.25. General structure of a PLA.

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x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
Figure 3.26. Gate-level diagram of a PLA.
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x1 x2 x3

OR plane
P1

P2

P3

P4

AND plane

f1 f2

Figure 3.27. Customary schematic for the PLA in Figure 3.26.

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x1 x2 x3

P1

f1
P2

P3

f2
P4

AND plane

Figure 3.28. An example of a PLA.

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Select
Enable

f1
Flip-flop

D Q

Clock

To AND plane

Figure 3.29. Extra circuitry added to OR

- gate from Figure 3.28.
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Figure 3.30. A PLD programming unit (courtesy of Data IO Corp).

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d
boar
t
ir cui
d c
rinte
P

Figure 3.31. A PLCC package with socket.

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PAL-like PAL-like
block block

I/O block
I/O block

Interconnection wires

PAL-like PAL-like
block block

I/O block
I/O block

Figure 3.32. Structure of a complex programmable logic device (CPLD).

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PAL-like block (details not shown)

PAL-like block

D Q

D Q

D Q

Figure 3.33. A section of the CPLD in Figure 3.32.

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(a) CPLD in a Quad Flat Pack (QFP) package

To computer

Printed
circuit board

(b) JTAG programming

Figure 3.34. CPLD packaging and programming.

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Figure 3.35. A field

-
programmable gate array (FPGA).

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x1

0/1

0/1 x1 x2 f1
f
0/1 0 0 1
0 1 0
0/1
1 0 0
x2 1 1 1

(a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2

x1

0
f1
0

1
x2

(c) Storage cell contents in the LUT

Figure 3.36. A two

- input lookup table (LUT).
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x1
x2

0/1
0/1
0/1
0/1
f
0/1
0/1
0/1
0/1
x3

Figure 3.37. A three- input LUT.

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Select

Out
Flip-flop
In1
In2 LUT D Q
In3
Clock

Figure 3.38. Inclusion of a flip

- flop in an FPGA logic block.

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x3

x1

x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1

Figure 3.39. A section of a programmed FPGA.

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x1 f2

x2
x3
f1

Figure 3.40. A section of two rows in a standard- cell chip.

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Figure 3.41. A sea- of- g

ates gate array.
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f1

x1

x2

x3

Figure 3.42. The logic function f1 = x2x3+x1x3 in the gate array of Figure 3.41.
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V = 0V
G

SiO 2

V = 0V
S
V
D

++++++ ++++ ++++++++++++ +++ ++++++

++++++ ++++++++++++ ++++++
+++++++++++ +++++++++++++++++++++++
+++++++++ Substrate (type p) +++++++++

Source (type n) Drain (type n)

(a) WhenV GS = 0 V, the transistor is off

Figure 3.43a. NMOS transistor when turned off.

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VDD

VG = 5 V

SiO2

VS = 0 V
VD = 0 V

++++++ ++++ +++ ++++++

++++++ ++++++
+++++++++++ +++++++++++++++++
+++++++++ ++ +++++++ ++++++++++

Channel (type n)

(b) When VGS = 5 V, the transistor is on

Figure 3.43b. NMOS transistor when turned on.

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ID

Triode Saturation

0 V GS V T
VDS

Figure 3.44. The current- voltage relationship in the NMOS transistor.

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VDD VDD

Vf I stat V f = V OL

Vx RDS

(a) NMOS NOT gate (b) Vx = 5 V

Figure 3.45. Voltage levels in the NMOS inverter.

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Vf

V OH = V DD Slope = 1

V OL = 0 V
VT V IL V IH ( V DD V T ) V DD
Vx
V DD
2

Figure 3.46. The voltage transfer characteristic for the CMOS inverter.
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N1 N2
A
x f

(a) A NOT gate driving another NOT gate

V DD VDD

VA
Vx
Vf

(b) The capacitive load at node A

Figure 3.47. Parasitic capacitance in integrated circuits.

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VDD

Vx
50% 50%

Gnd

Propagation delay Propagation delay

VDD
90% 90%
VA 50% 50%

Gnd 10% 10%

tr tf

Figure 3.48. Voltage waveforms for logic gates.

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+ W2
W1
+

L
L

(a) Small transistor (b) Larger transistor

Figure 3.49. Transistor sizes.

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VDD

Vx ID
ID

Vf Vf

Vx

(a) Current flow when input Vx (b) Current flow when input Vx
changes from 0 V to 5 V changes from 5 V to 0 V

Figure 3.50. Dynamic current flow in CMOS circuits.

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V DD

V DD

A B

(a) NMOS transistor (b) PMOS transistor

Figure 3.51. NMOS and PMOS transistors used in the opposite way
from Figure 3.4.

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Logic Logic
Vf Voltage
value value
Vx1 x1 x2 Vf f

0 0 1.5 V 0
VDD 0 1 1.5 V 0
Vx2 1.5 V
1 0 0
1 1 3.5 V 1

(a) An AND gate circuit (b) Truth table and voltage levels

Figure 3.52. A Poor implementation of a CMOS AND gate.

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V DD

Vf

Vx
1

Vx
2

Vx
3

Vx
k

Figure 3.53. High fan-in NMOS NAND gate.

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VDD

Vf

Vx1 Vx2 Vxk

Figure 3.54. High fan

- in NMOS NOR gate.

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N1
Vf
f To inputs of To inputs of
x x
n other inverters n other inverters

Cn

(a) Inverter that drives n other inverters (b) Equivalent circuit for timing purposes

V f for n =1
VDD

V f for n = 4

Gnd
0 Time

(c) Propagation times for different values of n

Figure 3.55. The effect of fan

- out on propagation delay.
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V DD

Vx
Vf

(a) Implementation of a buffer

x f

(b) Graphical symbol

Figure 3.56. A noninverting buffer.

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e= 0

e x f

x f
e= 1
x f

(a) A tri-state buffer (b) Equivalent circuit

e x f e
0 0 Z
0 1 Z
x f
1 0 0
1 1 1

(c) Truth table (d) Implementation

Figure 3.57. Tri- state buffer.

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e e

x f x f

(a) (b)

e e

x f x f

(c) (d)

Figure 3.58. Four types of tri- state buffers.

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x1 f

x2

Figure 3.59. An application of tri- state buffers.

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x f s f

0 Z
1 x
s

(a) Circuit (b) Truth table

s= 0

x f=Z s

s= 1 x f
x f=x s

(c) Equivalent circuit (d) Graphical symbol

Figure 3.60. A transmission gate.

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x1 x2 f = x 1 x2

0 0 0
0 1 1
x1
1 0 1 f = x1 x 2
x2
1 1 0

(a) Truth table (b) Graphical symbol

x1
x2

f = x1 x2

(c) Sum-of-products implementation

Figure 3.61a. Exclusive- ORgate.

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x1
x2

f = x1 x 2

(d) CMOS implementation

Figure 3.61b. CMOS Exclusive- ORgate.

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x1

x2 f

Figure 3.62. A 2
- to
- 1multiplexer built using transmission gates.

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x1 x2 x3

NOR plane

VDD VDD VDD

S1

VDD

S2

VDD

S3

NOR plane f1 f2

Figure 3.63. An example of a NOR

- NOR PLA.
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x1 x2 xn

VDD

=
Ve
S1
VDD

(b) A programmable switch

S2

VDD Ve

Sk ++++
+++++
++++ + ++++++ ++++ +

(c) EEPROM transistor

(a) Programmable NOR-plane

Figure 3.64. Using EEPROM transistors to create a

programmable NOR plane.
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x1 x2 x3 x4
NOR plane

V DD

V DD

S1

S2

S3

S4

S5

S6

NOR plane

f1 f2
Figure 3.65. Programmable version of a NOR-NOR PLA.
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x1 x2 x3 x4
NOR plane
V DD

V DD

P1

P2

P3

P4

P5

P6

NOR plane

Figure 3.66. A NOR-NOR PLA used for sum-of-

f1 f2
products.
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x1 x2 x3 x4

VDD

P1

P2
f1
P3

P4

P5
f2

P6

NOR plane

Figure 3.67. PAL programmed to implement two functions in Figure 3.66.

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x1 0 Vf
0 1
f1
0
x2
1
VA

1 0 0
SRAM SRAM SRAM

(to other wires)

Figure 3.68. Pass- transistor switches in FPGAs.

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V DD

SRAM
1
VB
VA To logic block

Figure 3.69. Restoring a high voltage level.

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Figure 3.70. The AOI cell for Example 3.9.

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Figure 3.71. Circuit for Example 3.9.

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Figure 3.72. The pseudo

- NMOS inverter.

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x1
x2

x3

Figure P3.1. A sum

- of- products CMOS circuit.

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x1
x2

x3
g

Figure P3.2. A CMOS circuit built with multiplexers.

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x1 A
x2 h
x3

Figure P3.3. Circuit for problem 3.3.

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V DD

Vf

Vx
1

Vx
2

Vx
3

Figure P3.4. A three- input CMOS circuit.

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V DD

Vx
1

Vx
2

Vx
3

Vx
4

Vf

Figure P3.5. A four- input CMOS circuit.

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Vf
Vx1

Vx2

Vx3

Figure P3.6. The PDN in a CMOS circuit.

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V DD

Vx
1

Vx
2

Vf
Vx
3
Vx
4

Figure P3.7. The PUN in a CMOS circuit.

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Figure P3.8. The pseudo

- PMOS inverter.
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in 1 in2 in 3

out

in4 in5 in 6 in 7

Figure P3.9. A gate- array logic cell.

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Vx
1

Vx
2

Vf

Figure P3.10. Circuit for problem 3.54.

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Vx1

Vx2
Vf

Figure P3.11. Circuit for problem 3.55.

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