2942 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO.

12, DECEMBER 2007

An Electronic Dispersion Compensator (EDC)

With an Analog Eye-Opening Monitor (EOM)
for 1.25-Gb/s Gigabit Passive Optical
Network (GPON) Upstream Links
Hyoungsoo Kim, Student Member, IEEE, Jean de Ginestous, Franklin Bien, Member, IEEE,
Kil-Hoon Lee, Student Member, IEEE, Soumya Chandramouli, Student Member, IEEE,
Youngsik Hur, Member, IEEE, Chris Scholz, Member, IEEE,
Edward Gebara, Member, IEEE, and Joy Laskar, Fellow, IEEE

AbstractToday, network systems require higher bandwidth for

applications such as fiber-to-the-home communications. Gigabit
passive optical network (GPON) links using a FabryPerot laser
are attractive solutions for this high-speed network. However,
due to the mode partition noise and fiber dispersion, GPON
systems suffer from inter-symbol interference (ISI). In this paper,
we present an electronic dispersion compensator (EDC) that
will improve a 1.25-Gb/s experimental GPON link. The experi-
mental GPON link is simulated and measured with impairment
assessment. An analog eye-opening monitor, which captures the
quality of the EDC output signal using the tunable delay and the
integrator is proposed. The proposed EDC successfully compen-
sates ISI for a given link with a 1.25-Gb/s signal. All circuits are
fabricated using a 0.18- m CMOS process.
Index TermsDigitalanalog converter (DAC), electronic
dispersion compensator (EDC), eye-opening monitor (EOM), Fig. 1. Block diagram of the GPON link [12].
FabryPerot (FP) laser, fiber dispersion, finite impulse response
(FIR), gigabit passive optical network (GPON), mode partition
noise (MPN), single-mode fiber (SMF), 0.18- m CMOS.
A promising low-cost approach using this medium is the gi-
gabit passive optical network (GPON)-based fiber-to-the-home
I. INTRODUCTION (FTTH) [1][4].
A GPON system is a bi-directional point-to-multipoint net-
work architecture deploying optical access lines between a car-
HE increasing demand for higher bandwidth in network riers central office and customer sites. An optical line termina-
T infrastructures has escalated in recent years. Many appli-
cations with rich media such as multimedia applications and
tion (OLT) is placed at a central office and optical network units
(ONUs) are at the customers premise. The GPON system, as
Internet protocol television (IPTV) are successfully employed. shown in Fig. 1, uses passive optical splitters to distribute the
This demand for high-speed communication fuels new hardware content to multiple premises. The upstream and downstream
network system developments. One of the emerging transmis- paths utilize different wavelengths and different transmission
sion mediums that can fulfill such demands is the optical fiber. speeds. This feature enables two-way traffic on a single optical
fiber and makes the GPON a cost-effective system [6], [10].
One of the critical parts of GPON links is the laser. The
Manuscript received May 10, 2007; revised August 27, 2007. distributed feed back (DFB) laser and electro-absorption mod-
H. Kim, J. de Ginestous, K.-H. Lee, S. Chandramouli, C. Scholz, E. ulated laser (EML) are stable solutions; however, they are
Gebara, and J. Laskar are with the Georgia Electronic Design Center, School
of Electrical and Computer Engineering, Georgia Institute of Technology,
expensive. For a more cost-effective system, the FabryPerot
Atlanta, GA 30308 USA (e-mail: hskim@ece.gatech.edu; jeanatl@gmail.com; (FP) laser is a good candidate because it is manufactured by a
klee@gatech.edu; Soumya@ece.gatech.edu; chris.scholz@ece.gatech.edu; higher yield process, which does not require equipment-inten-
gebara@ece.gatech.edu; joy.laskar@ece.gatech.edu).
F. Bien is with Staccato Communications, San Diego, CA 92121 USA
sive grating and overgrowth steps.
(e-mail: franklin@staccatocommunications.com). The FP lasers, however, exhibit multiple spectral modes, as
Y. Hur is with the Samsung RFIC Design Center, Georgia Institute of Tech- shown in Fig. 2, whereas GPON systems use single-mode fiber
nology, Atlanta, GA 30308 USA (e-mail: young.hur@samsung.com). (SMF) with a single spacial mode characteristic. As a result, the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. relative power throughout various spectral modes can fluctuate
Digital Object Identifier 10.1109/TMTT.2007.909887 significantly even though the total optical output power of the
0018-9480/$25.00 2007 IEEE
KIM et al.: EDC WITH ANALOG EOM FOR 1.25-Gb/s GPON UPSTREAM LINKS
Fig. 2. Measured and modeled laser output spectrum.
FP laser is fairly constant. This phenomenon is known as mode
partition noise (MPN) [11], [14]. This MPN in conjunction with
chromatic dispersion (CD) results in inter-symbol interference
(ISI) at the receiver side, significantly degrading the system per-
formance. This study suggests using an FP laser in the upstream
link and correct for the ISI resulting from the FP laser in order
to have a cost-effective system. This study does not address the
downstream path, which uses a DFB laser and, therefore, does
not suffer from ISI-related problems.
Previous approaches to compensate ISI mostly use optical
components, which are bulky and expensive [8], [13]. This study
suggests using the electronic dispersion compensator (EDC) to
address the problem in the electrical domain [12], [18]. For fur-
ther understanding of the GPON link and its impairment, the
model is simulated and compared to an actual characterized link.
An analog eye-opening monitor (EOM) method using a tunable
delay line is also proposed.
This paper is organized as follows. Section II presents the
detailed GPON link system model with impairment analysis.
Section III describes the detailed EDC design and other circuits
such as digitalanalog converters (DACs) and the analog EOM.
Experimental results are presented in Section IV. A conclusion
is finally drawn in Section V.
II. GPON LINKS WITH FP LASER ANALYSIS
A preliminary analysis of the GPON links from ONU to OLT
was necessary to better understand the link to be equalized. The
downstream path, which uses a DFB laser with a good signal
quality due to the absence of MPN, has good transmission char-
acteristics. However, the upstream path (utilizing the FP laser)
has limiting characteristics that need to be discussed. Here, we
developed an analytical model taking into account the main im-
pairments that impact the link performance: thermal and shot
noise in the receiver, CD in the fiber, and MPN from the laser.
The bit error ratio (BER) data extracted from this analytical
model is compared with the actual measured BER data to verify
the accuracy of the model.
2943
A. GPON Upstream Signal Path
The GPON upstream signal path is composed of an FP laser
included in a triplexer on the ONU side, 020 km of SMF,
and a receiver on the OLT side. A triplexer is a bi-directional
transceiver, which converts an electrical signal into an optical
signal. It contains an FP laser diode with a monitor photodiode,
a high-bandwidth avalanche photodiode, and trans-impedance
amplifier (TIA) for a digital receiver, an analog photodiode for a
video channel with low noise and high linearity, and a matching
network built directly on the chip. This upstream path transmits
signal through the FP laser.
B. Upstream Link Model
The laser output spectrum is typically modeled by a Gaussian
distribution around a center wavelength and with a standard de-
viation [10]. Fig. 2 shows the measured spectrum (blue in online
version) and the associated Gaussian fit (red in online version).
The spectral width of the laser can be derived from the standard
deviation of the Gaussian distribution using the full width at
half maximum (FWHM) method
(1)
In order to test the system in different situations, the laser is
temperature tuned to change the center wavelength, and thus the
dispersion-induced penalties on the system. At room tempera-
ture, the laser properties are measured to have a center wave-
length of 1324.5 nm and a spectral width of 3.0 nm. As the tem-
perature is increased, the spectral width remains constant, but
the spectrum shifts to higher wavelength. The tuned tempera-
ture (TT) is defined as the temperature where the center wave-
length of the FP laser is 1328.5 nm, the longest experimental
wavelength value.
In this thermal noise, limited upstream link, the BER for a
back-to-back configuration can be derived as a function of the
average input optical power using
(2)
where is the responsivity, is the average avalanche multi-
plication gain of the APD receiver, and is the receiver noise.
The noise in the receiver can be derived from the thermal noise
defined as
(3)
where is the temperature, is the noise figure of the fol-
lowing low noise amplifier, and is the electrical bandwidth
of the receiver. The receiver noise is also derived from the shot
noise of the photodiode defined as
(4)
In (4), is the elementary charge and is the excess noise
factor of the APD.
The receiver can be practically characterized by the BER
back-to-back curve. With an electrical bandwidth of 640 MHz,
2944 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007
Fig. 3. Comparison between simulated and measured BER.
a value that is slightly higher than half the bit rate, the com-
puted back-to-back BER is displayed on Fig. 3 as a solid black
curve, and the experimental data points are denoted as black
crosses. The back-to-back simulated results correlate with the
actual measurements.
Based on this receiver characterization, the two critical power
penalties of the system (MPN and CD) are analyzed and in-
cluded into the model in order to simulate the 20-km BER per-
formances (Fig. 3) and evaluate the weight of each effect. A
detailed explanation of these impairments will be covered in
Section II-C.
C. CD and MPN
Group velocity dispersion in SMF leads to a broadening of
the optical pulse [12]. If a significant part of the pulse energy
spreads beyond the allocated bit slot, it will affect the previous
and/or next bit, resulting in so-called ISI after electrical conver-
sion. Moreover, the pulse energy within the bit slot is reduced
when the optical pulse broadens. Thus, more average energy is
needed to maintain the system performance, resulting in a power
penalty due to dispersion. The optical pulse can be modeled as a
Gaussian pulse and an analysis of its broadening properties [12]
leads to the expression of the dispersion induced power penalty
(5)
Since dispersion theoretically is a linear process, this power
penalty can be compensated by an EDC.
Another impairment, i.e., MPN, is typically found in FP lasers
where the output optical spectrum has different longitudinal
modes. It can be assumed that the total power is constant even if
the amplitude of the peak is constantly varying. When the signal
propagates through the fiber and is affected by group velocity
dispersion, each mode is delayed by different amounts.
The varying amount of power in each mode submitted to
CD leads to an additional, noise which was theoretically in-
TABLE I
POWER PENALTY (Pp) COMPARISON AND ANALYSIS FOR
DIFFERENT WAVELENGTHS
vestigated by Ogawa and Vodhanel [14]. In their model, the
noise-to-signal ratio after the transmission is expressed by
(6)
where
(7)
(8)
and the propagation constant is derived with respect to
at .
The power penalty due to MPN is then given by
(9)
where we have introduced a coefficient . This coefficient
was used by Ogawa and Vodhanel [14] to take into account that
the amplitude of each spectral modes do not vary from very
small to maximum peak, but only fluctuates by , or
70% in our model, of total optical power [20]. MPN results in a
nondeterministic component of ISI [7], [8].
The accuracy of the model was evaluated by comparing the
computed BER to the measured BER of the link in different con-
figurations. Three significant configurations are tested. Fig. 3
is the summary of the simulated BER compared to the experi-
mental data for each of the three configurations. The black graph
is the back-to-back BER data. The blue curve (in the online ver-
sion) displays the BER data with 20-km SMF at the center wave-
length of 1324.5 nm. Finally, the red plot (in the online version)
shows the 20-km fiber data at the 1328.5-nm wavelength.
The simulated curves on Fig. 3 are consistent with the ex-
perimental data measured from the upstream link and allow us
to evaluate the amount of power penalty due to CD and MPN.
Power penalties (Pp) for the BER of 10 for the two link con-
figurations are summarized in Table I.
III. CIRCUIT DESIGN DETAIL
EDC building blocks for the GPON links and corresponding
functional blocks are described here with their design specifica-
tions. The EDC is composed of variable gain amplifiers (VGAs),
active delay lines, and a buffer stage. Other peripheral blocks
are a single-to-differential conversion circuit, an analog EOM,
and DAC circuits. All components are implemented via TSMC
0.18- m CMOS technology.
KIM et al.: EDC WITH ANALOG EOM FOR 1.25-Gb/s GPON UPSTREAM LINKS
Fig. 4. Functional block diagram of the EDC.
Fig. 5. Measured impulse response with concept of the EDC [12].
GPON links have various channel characteristics that are de-
pendent on the fiber length and zero dispersion wavelengths.
EDCs could either be placed at the ONU side or the OLT side.
Placing an EDC at ONU side has the advantage that the link
could be compensated for a specific fiber dispersion value since
fiber dispersion changes very little with temperature. However,
this structure would require 32 or more transmitter-side EDCs
in the ONU and would increase the cost of customer side equip-
ments. When placing an EDC in the OLT, the cost of the EDC
is shared by 32 users, thus resulting in a more cost-effective so-
lution.
The feed-forward equalizer (FFE) structure comprised of
four taps with spacing is selected for the EDC, as shown
in Fig. 4. System simulations show that four taps with tap
spacing are sufficient to meet the system requirement criteria.
Increasing the number of taps provides marginal improvement
in ISI cancellation at the cost of power consumption and size
[16]. For converting a single-ended signal to a differential
signal, a single-to-differential converter is placed at the EDC
input. DACs are connected to VGAs for controlling the four-tap
gain cells. Finally, an analog EOM is placed at the output of
the EDC.
The operating principle of the EDC can be explained by re-
ferring to Fig. 5, which shows the normalized impulse response
2945
Fig. 6. Schematic of the VGA [12].
measured through the channel. This impulse response is de-
graded due to ISI and shows the broadening of pulse energy.
With the use of VGAs, the EDC will add positive and negative
gains accordingly to remove the effects of pre- and post-cursor
ISI. The spacing between the tap gains is implemented with
delay cells. In this application with a 1.25-Gb/s data rate, the
spacing between the taps is approximately 267 ps.
A. EDC Components
The EDC is comprised of four VGAs, active delay lines, and
an output buffer stage. A Gilbert-multiplier type amplifier was
chosen as the architecture for the VGAs, which has positive and
negative gain [7]. To improve voltage headroom, a gain control
circuit is folded with the current steering block. Summation
is done in current domain at the passive node. The schematic
of the VGA is shown in Fig. 6. In addition, both linearity and
voltage headroom are enhanced by applying an active degen-
eration scheme between divided common source pairs. The
transistor pairs represent such active degeneration with
and being the divided current sources. The
gain control block also includes a degeneration circuit ( )
for linear gain control. The 3-dB bandwidth is 7.2 GHz, and the
input dynamic range is 300 mVpp.
The delay line can be implemented in two methods using LC
(passive) components or active components. An active delay
cell is implemented with an nMOS differential pair because it is
more space efficient compared to a passive approach. The prop-
agation delay of the active devices is generated by RC transient
characteristic, i.e., resistance of the load and intrinsic capaci-
tance of the differential amplifier pair cells.
The overall voltage gain of the differential pair in unit delay
cell is
(10)
where the corresponding and values can be calculated
as follows:
(11)
2946 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007

and

(12)

The two poles are at

(13)
and the zero is at

(14)

By varying the ( is the turn-on resistance of the load tran-
sistor), the zero location can be controlled.
Another benefit of active delay is that it does not introduce
dc voltage drop across each stage and is immune to the process
variations, while the passive approach lacks these features.
The passive delay approach is an attractive solution for power
saving, but achieving 267-ps delay with LC passive compo-
nents occupying a large space [9]. The active delay cell is a
subcircuit of the tunable delay line, which is later discussed in
Section III-D.
The buffer stage consists of two cascaded differential pairs
matched to 50 . Instead of using an identical gain cell for two
stages, each stage is designed differently with the first stage
designed for gain and the second stage designed for matching.
The output stage also increases the slew rate by flowing a
large-signal current swing. The input voltage swing to the
buffer is large enough compared to the offset input voltage,
no offset compensation is needed. The 3-dB bandwidth of the
output buffer is approximately 7 GHz, which does not degrade
the signal integrity at the output of the EDC.
B. Single-to-Differential Converter
Optical systems are usually single ended, whereas integrated
analog circuits used in high-frequency applications are fully dif-
ferential due to the ability to reject common-mode noise and
achieve high voltage swings [17]. Therefore, a stage that con-
verts a single-ended signal into a differential signal needs to be
added.
The single-to-differential conversion circuit composed of a
differential pair with one of its inputs grounded is shown in
Fig. 7. The unused input of the differential pair is the gate of
whose dc-bias voltage is supplied through a low-pass filter com-
prised of and . The input signal propagates to the
node through a path where operates as a common-source
stage, generating an inverting signal, and to the node
through a path where and operate as a cascade of a
source follower and common-gate stage, generating a nonin-
verting signal. The gain of this circuit is set by the ratio of
the transconductance of and that can be adjusted by
varying their aspect ratio.
C. DAC
A 6-bit DAC is implemented to control the tap gain of VGAs
digitally. The schematic of the DAC is shown in Fig. 8. A 6-bit
Fig. 7. Schematic of the single-to-differential converter.
Fig. 8. Schematic of the DAC.
DAC is integrated with each tap to provide control voltages. The
R-2R ladder network architecture is used. The design is modi-
fied to consist of bit modules, as illustrated in Fig. 8. This ap-
proach provides flexibility to the DAC resolution such that the
desired number of bits can be designed by simply adding or
deleting the standardized bit modules. It is inherently accurate
and easy to manufacture because an R-2R-based modular DAC
uses ratios of single value standardized poly resistors, where
these ratios can be highly tolerant over process variation, es-
pecially with inter-digitated layout and added dummy resistors.
To reduce error, which is critical for the EDC, large aspect ratio
devices are used for nMOS switch transistors. This feature min-
, imizes errors due to voltage drop between the source and drain.
Process corner, supply voltage, and temperature variations
simulations are performed and showed 10% of error offset at
the least significant bit. Simulation result for the DAC is shown
in Fig. 9. Effective control range for the VGA is from 0.5 to
1.2 V and corresponding gain is from 1 to 1.
D. Analog EOM and Tunable Delay Cell
The output of the EDC is monitored by the analog EOM
to evaluate the overall signal quality. Instead of using clocked
components, which can increase the complexity [15], the analog
EOM employs two tunable delay cells and an integrator, as
shown in Fig. 10. The output signal from the EDC is divided
into two different delayed paths, where the delay amount of the
KIM et al.: EDC WITH ANALOG EOM FOR 1.25-Gb/s GPON UPSTREAM LINKS
Fig. 9. Simulation result of the DAC [20].
Fig. 10. Functional block diagram of an analog EOM.
first cell is set to capture the rise time and that of the second
cell is adjusted to capture the fall time according to the date
rate of the application. This tunable delay feature has an advan-
tage of enabling the analog EOM to operate with applications
with various data rates. The two delayed signals are then sub-
tracted from each other, and the difference is subsequently in-
tegrated over time to generate a dc voltage. The eye-opening
size of the EDC output signal will be directly proportional to
the amplitude of the difference signal. Consequently, when this
difference signal is integrated, the resultant dc value will also
be proportional to the eye-opening size. For example, a signal
with a wide eye opening as in Fig. 11(a) will have a larger in-
tegrated dc value than a signal with a narrow eye opening as in
Fig. 11(b). The signal quality of the EDC, therefore, can be pre-
dicted without measuring the actual eye diagram.
A tunable delay cell, as illustrated in Fig. 12, consists of three
active delay stages with a signal path that is connected to both
the first and third delay cells. The amount of signal distribu-
tion between these two delay paths is determined by the control
voltage applied to and . These two delay paths
form the slow path and fast path. The fast path is designed to pro-
vide minimum gate delay that can be achieved from the given
process technology. On the other hand, the slow path is designed
to provide the longest desirable delay. The fastest path achieves
15-ps delay, while the slowest path can go up to 95-ps delay.
2947
Fig. 11. Eye diagrams with a: (a) wide eye opening and (b) narrow eye opening.
Fig. 12. Schematic of the tunable delay cell.
Fig. 13. Chip micrograph of the EDC [12].
IV. RESULTS
To measure the EDC performance, the GPON experimental
link is set up. The FP laser in the ONU generates a 1.25-Gb/s op-
tical signal. This optical signal is transmitted through 020-km
SMF and is converted to an electrical signal using a photodiode.
The electrical signal is fed into the EDC and the output of the
EDC is monitored with an oscilloscope. The zero dispersion
wavelength of SMF used in the experiments is 1310 nm. The
EDC die photograph is shown in Fig. 13. A 1.25-Gb/s pseu-
dorandom bit signal (PRBS) with word length of 2 1 was
transmitted. Fig. 14 shows the bit patterns before and after com-
pensation. The bit pattern before compensation shows uneven
zero and one signal levels, which is an indicator of ISI. After
applying to the EDC, with appropriate compensation the signal
levels are improved at the output of the EDC. The performance
of the EDC is also evaluated in terms of error ratio. The EDC
was tested with a PRBS signal for experimental purposes. The
EDC will work even in a burst mode for the GPON application
because it is transparent to modulation. The concept of a trans-
parent EDC is introduced and is used as the reference for the
2948 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007
Fig. 14. Bit pattern before and after compensation [12].
Fig. 15. Comparison of BER between the transparent and the optimized EDC.
GPON link performance, which is affected by the EDC mea-
surement setup. In this configuration, the first tap of the EDC
is set to a constant coefficient, gain of one, and the three others
are set to zero. Fig. 15 compares the BER performance of the
EDC in the transparent configuration and in the optimized con-
figuration where the tap coefficients were tuned to compensate
for dispersion.
For the laser at both 1324 and 1328 nm, compensation leads
to a shift of the BER curve to a lower received power, com-
pensating for the power penalty due to dispersion. The disper-
sion compensation provided by the EDC enables the system to
overcome ISI penalties and get an access to lower BER needed
for communication purposes. The EDC is implemented with a
0.18- m CMOS technology and consumes 54-mW power dis-
sipation from a 1.8-V supply voltage.
The DAC and tunable delay line are fabricated on a single
chip, and the die photograph is shown in Fig. 16. The con-
trol voltage of the tunable delay line is connected to the DAC.
Fig. 17 shows measurement results of the tunable delay line. It
illustrates linear control of the tunable delay for up to 82 ps,
which closely matches the simulation results. A wide tuning
range is achieved from 15 ps (fast delay path) up to 97 ps (slow
delay path). This corresponds to the control voltage from 0.5 to
Fig. 16. Chip micrograph of the tunable delay and the DAC [20].
Fig. 17. Measurement results of the digitally controlled active tunable delay
with 3-ps effective tuning resolution.
TABLE II
ANALOG EOM RESULTS
1.2 V, which is within the control range of the designed modular
6-bit DAC. These components are also fabricated in a CMOS
0.18- m process.
Finally, results of the analog EOM are summarized in
Table II. Three different eye diagrams with different eye open-
ings and their corresponding dc voltages show that the bigger
eye openings result in larger dc values from the analog EOM,
as expected.
V. CONCLUSION
The EDC for GPON links using an FP laser has been pre-
sented. To compensate for ISI caused by MPN of the FP laser
and CD, the EDC using the FFE structure with a 267-ps tap
delay line has been designed. The proposed EDC successfully
compensates ISI from these impairments, which is measured
from the experimental GPON link. GPON link system simu-
lations and measurements are also investigated and compared.
A DAC is designed for effective management of tap gains. An
analog EOM scheme has been presented to monitor the output
of the EDC without directly measuring eye diagrams. All of cir-
cuits have been implemented in 0.18- m CMOS technology.
KIM et al.: EDC WITH ANALOG EOM FOR 1.25-Gb/s GPON UPSTREAM LINKS
ACKNOWLEDGMENT
The authors would like to thank A. Romano, Pirelli Labora-
tories, Milan, Itay, and Dr. A. Righetti, Corecom, Milan, Italy,
for their technical support. The authors also would like to thank
S. Vasavada, Atlanta, GA, for helping with measurement and
GPON link setup.
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2949
Hyoungsoo Kim (S04) received the B.S. degree in
electrical engineering from Yonsei University, Seoul,
Korea. in 2000, the M.S. degree in electrical engi-
neering from the Georgia Institute of Technology, At-
lanta, in 2004, and is currently working toward the
Ph.D. degree at the Georgia Institute of Technology.
His research interests include equalization systems
and circuits for backplane and optical applications
and high-speed mixed-signal circuit design.
Jean de Ginestous was born in Paris, France. He
attended Lycee Stanislas, Paris, France, where for
two years he focused on advanced mathematics and
physics. He received the B.S. degree in electrical
engineering and computer science from the Ecole
Superieure dElectricite, Paris, France, in 2006, and
is currently working toward the M.S. degree at the
Georgia Institute of Technology, Atlanta.
His research is focused on integration analog/
mixed signal integrated circuits (ICs) in optical fiber
communication systems.
Franklin Bien (S04M07) received the B.S. degree
from Yonsei University, Seoul, Korea, in 1997, and
the M.S. and Ph.D. degrees in electrical and com-
puter engineering from the Georgia Institute of Tech-
nology, Atlanta, in 2000 and 2006, respectively.
From 2000 to 2002, he was an Analog IC Design
Engineer with Agilent Technologies, where he devel-
oped transceiver ICs for enterprise segments. From
2003 to 2004, he was a Senior Design Engineer with
Quellan Inc., where he developed ICs that improve
the speed and reach of communication channels in
consumer, broadcast, enterprise, and computing markets. He is currently a Se-
nior IC Design Engineer with Staccato Communications, San Diego, CA, where
he is involved with analog/mixed-signal ICs for ultra-wideband (UWB) prod-
ucts. During his doctoral studies, his research interests included signal integrity
improvement with alternate modulation schemes, crosstalk noise cancellation,
+
and equalization techniques for 10 Gb/s broadband communication applica-
tions.
Kil-Hoon Lee (S07) received the B.S. and M.S.
degrees in electrical and computer engineering from
the Georgia Institute of Technology, Atlanta, in 2005
and 2006, respectively, and is currently working
toward the Ph.D. degree in electrical and computer
engineering at the Georgia Institute of Technology.
His research interests include mixed-signal IC
design for equalization and electrostatic discharge
(ESD) protection design for high-frequency applica-
tions.
Soumya Chandramouli (S00) was born in Banga-
lore, India. She received the B.S. degree in electrical
and computer engineering from Lafayette College,
Easton, PA, in 2002, the M.S. degree in electrical
and computer engineering from the Georgia Institute
of Technology, Atlanta, in 2004, and is currently
working toward the Ph.D. degree at the Georgia
Institute of Technology.
From May to December 2005, she was an Analog
Circuit Design Intern with National Semiconductor,
Norcross, GA. Her research interest is in the area of
multigigabit/second equalizer circuits in CMOS.
2950 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007
Youngsik Hur (S04M06) received the B.S. and
M.S. degrees in electrical engineering from Hanyang
University, Seoul, Korea, in 1993 and 1995, respec-
tively, and the Ph.D. degree in electrical engineering
from the Georgia Institute of Technology, Atlanta, in
2005.
During his doctoral studies, he was involved with
mixed-signal circuit implementation of equalization
and noise-cancellation techniques for broadband
wired and wireless communication applications.
Prior to joining the Samsung RFIC Design Center,
Georgia Institute of Technology, Atlanta, in 2006, he was with the Samsung
Institute of Advanced Technology, Kiheung, Korea, and subsequently with
Samsung Electronics, Suwon, Korea, from 1995 to 2001. During this period,
he was involved with the development of an orthogonal frequency division
multiplexing (OFDM) wireless communication system and a channel charac-
terization of the 60-GHz indoor wireless channel. He subsequently lead the
system development efforts of the Fiber-Optic Security Sensor System Project.
His current research interests include developments of system and IC solutions
enabling the convergence of digital broadcasting and broadband wireless data
access. He is specifically focused on realizing cognitive radio (CR) technology
as a promising coexistence solution of the unlicensed spectrum applications.
Chris Scholz (M97) received the B.S. degree from
Ruhr University Bochum, Bochum, Germany, in
1986, the M.S. degree in mechanical engineering
from the Technical University Carolo Wilhelmina,
Braunschweig, Germany, in 1988, and the M.S.
degree in aerospace engineering and Ph.D. degree in
electrical engineering from the Georgia Institute of
Technology, Atlanta, in 1992 and 1999, respectively.
He has held research faculty position with the
University of California at Santa Barbara and the
Center for High Technology Materials, University
of New Mexico, Albuquerque. While with IntelCapital, Santa Clara, CA, he
conducted due diligence on 50 national and international startups in optical
components and communication space. While with the Intel Corporation,
San Jose, CA, he managed a product development team that manufactured
innovative silicon-based integrated electrooptic components. He is currently
a member of the research faculty with the Georgia Electronic Design Center
(GEDC), Atlanta, CA. His research interests include nanophotonic devices,
nonlinear optical signal processing, electrooptic co-design and millimeter-wave
(MMW) sensors for prognosis, and health monitoring of airframe structures.
Edward Gebara (M05) received the B.S. (with
highest honors), M.S., and Ph.D. degrees in electrical
and computer engineering from the Georgia Institute
of Technology, Atlanta, in 1996, 1999, and 2003,
respectively.
He is currently a Member of Technical Staff with
Quellan Inc., Atlanta, GA, which develops high-per-
formance analog semiconductors that improve the
speed and reach of communication channels in
consumer, broadcast, enterprise, computing, and
wireless markets. He is also a research faculty
member with the Georgia Institute of Technology, where he leads the Mixed
Signal Teams research efforts. The teams research interest is to develop the
foundation for alternate modulation schemes (quadrature amplitude modulation
(QAM), optical subcarrier multiplexing (OSCM), etc.), equalization techniques,
and Xtalk cancellation techniques on pure CMOS applied to next-generation
wired and wireless communication. He has authored or coauthored over 50
publications
Joy Laskar (S84M85SM02F05) received
the B.S. degree in computer engineering with
math/physics minors (with highest honors) from
Clemson University, Clemson, SC, in 1985, and the
M.S. and Ph.D. degrees in electrical engineering
from the University of Illinois at Urbana-Cham-
paign, in 1989 and 1991, respectively.
Prior to joining the Georgia Institute of Tech-
nology in 1995, he held faculty positions with the
University of Illinois at Urbana-Champaign and the
University of Hawaii. With the Georgia Institute of
Technology, he holds the Joseph M. Pettit Professorship of Electronics and
is currently the Chair for the Electronic Design and Applications Technical
Interest Group. He is also the Director of the Electronic Design Center
(GEDC), Georgia Institute of Technology, and the System Research Leader for
the National Science Foundation (NSF) Packaging Research Center. He heads
a research group of 25 members with a focus on integration of high-frequency
mixed-signal electronics for next-generation wireless and wired systems. He
has authored or coauthored over 200 papers, several book chapters (including
three textbooks in development), and numerous invited talks. He has over
20 patents pending. Most recently, his research has resulted in the formation
of two companies. In 1998, he cofounded the advanced wireless local area
network (WLAN) IC company RF Solutions, which is now part of Anadigics
(Nasdaq: Anad). In 2001, he cofounded the next-generation analog CMOS IC
company Quellan, which develops collaborative signal-processing solutions
for the enterprise, video, storage, and wireless markets.
Prof. Laskar was an IEEE Distinguished Microwave Lecturer for the
20042006 term for his Recent Advances in High Performance Communica-
tion Modules and Circuits seminar. He was the recipient of the 1995 Army
Research Office Young Investigator Award, the recipient of the 1996 National
Science Foundation (NSF) CAREER Award, the NSF Packaging Research
Center Faculty of the Year 1997, the corecipient of the 1999 IEEE Rappaport
Award (Best IEEE Electron Devices Society journal Paper), the faculty advisor
for the 2000 IEEE MTT-S IMS Best Student Paper Award, the 2001 Georgia
Institute of Technology Faculty Graduate Student Mentor of the year, the
recipient of the 2002 IBM Faculty Award, the recipient of the 2003 Clemson
University College of Engineering Outstanding Young Alumni Award, and the
recipient of the 2003 Outstanding Young Engineer of the IEEE MTT-S.