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1. Product profile
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
n Typical CW performance at frequency of 225 MHz, a supply voltage of 50 V and an IDq
of 1000 mA:
u Average output power = 500 W
u Power gain = 26.5 dB
u Efficiency = 70 %
n Easy power control
n Integrated ESD protection
n Excellent ruggedness
n High efficiency
n Excellent thermal stability
n Designed for broadband operation (10 MHz to 500 MHz)
n Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
n Industrial, scientific and medical applications
n Broadcast transmitter applications
NXP Semiconductors BLF574
HF / VHF power LDMOS transistor
2. Pinning information
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
1 drain1
1 2 1
2 drain2
5
3 gate1
3
4 gate2 3 4 5
4
5 source [1]
2
sym117
3. Ordering information
Table 3. Ordering information
Type number Package
Name Description Version
BLF574 - flanged balanced LDMOST ceramic package; SOT539A
2 mounting holes; 4 leads
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 110 V
VGS gate-source voltage 0.5 +11 V
ID drain current - 56 A
Tstg storage temperature 65 +150 C
Tj junction temperature - 225 C
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resistance from Tcase = 80 C; PL = 400 W 0.23 K/W
junction to case
6. Characteristics
Table 6. DC characteristics
Tj = 25 C; per section unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown voltage VGS = 0 V; ID = 2.5 mA 110 - - V
VGS(th) gate-source threshold voltage VDS = 10 V; ID = 250 mA 1.25 1.7 2.25 V
VGSq gate-source quiescent voltage VDS = 50 V; ID = 500 mA 1.35 1.85 2.35 V
IDSS drain leakage current VGS = 0 V; VDS = 50 V - - 2.8 A
IDSX drain cut-off current VGS = VGS(th) + 3.75 V; 29 37.5 - A
VDS = 10 V
IGSS gate leakage current VGS = 11 V; VDS = 0 V - - 280 nA
gfs forward transconductance VDS = 10 V; ID = 12.5 A - 17 - S
RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V; - 0.14 -
ID = 8.33 A
Crs feedback capacitance VGS = 0 V; VDS = 50 V; - 1.5 - pF
f = 1 MHz
Ciss input capacitance VGS = 0 V; VDS = 50 V; - 204 - pF
f = 1 MHz
Coss output capacitance VGS = 0 V; VDS = 50 V; - 72 - pF
f = 1 MHz
Table 7. RF characteristics
Mode of operation: CW; f = 225 MHz; RF performance at VDS = 50 V; IDq = 1000 mA for total device;
Tcase = 25 C; unless otherwise specified; in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gp power gain PL = 400 W 25 26.5 28 dB
RLin input return loss PL = 400 W 13 20 - dB
D drain efficiency PL = 400 W 66 70 - %
001aaj126
500
Coss
(pF)
400
300
200
100
0
0 10 20 30 40 50
VDS (V)
VGS = 0 V; f = 1 MHz.
Fig 1. Output capacitance as a function of drain-source voltage; typical values per
section
7. Application information
7.1 RF performance
RF performance in a 500 W application circuit at 225 MHz.
7.1.1 1-Tone CW
001aaj127 001aaj128
30 80 30
Gp D Gp
(dB) (%) (dB)
D
(7)
28 60 28 (6)
(5)
Gp
26 40 26
(4)
(3)
(2)
(1)
24 20 24
22 0 22
0 200 400 600 0 100 200 300 400 500
PL(PEP) (W) PL (W)
001aaj129
60
PL
(dBm)
58 Ideal PL (1)
PL
56
54
52
50
24 26 28 30 32 34
Ps (dBm)
7.1.2 2-Tone CW
001aaj130 001aaj131
30 80 0
Gp D IMD3
(dB) D (%) (dBc)
(1)
(2)
28 60 20
(3)
Gp
26 40 40
(4)
(5)
24 20 60
22 0 80
0 200 400 600 800 0 200 400 600 800
PL(PEP) (W) PL(PEP) (W)
VDS = 50 V; IDq = 1000 mA; f1 = 224.95 MHz; VDS = 50 V; f1 = 224.95 MHz; f2 = 225.05 MHz.
f2 = 225.05 MHz. (1) IDq = 600 mA
(2) IDq = 800 mA
(3) IDq = 1000 mA
(4) IDq = 1200 mA
(5) IDq = 1400 mA
Fig 5. Power gain and drain efficiency as functions of Fig 6. Third order intermodulation distortion as a
peak envelope load power; typical values function of peak envelope load power; typical
values
C23, C24
C3 multilayer ceramic chip capacitor 24 pF [1]
C10, C11
C12, C16 electrolytic capacitor 220 F; 63 V
C13, C15 multilayer ceramic chip capacitor 62 pF [1]
L1
R3
C10 +
T1 C6 T3
C7
R1 C12
L2 C17
C13
C20 C23
C1 C3 C4 C5 L6 L8 L9 L11
C14 C18 C21
C24
C2 L5 L7 L10 L12
C15 C22
C19
L3
R2 C16
C8
T2 C9 C11 + T4
R4
L4
001aaj132
7.2 Reliability
001aaj133
105
Years
(1) (2) (3) (4) (5) (6)
104
103
102
1
0 4 8 12 16 20
Idc (A)
8. Test information
drain
ZL
gate
ZS
001aaf059
8.2 RF performance
The following figures are measured in a class-AB production test circuit.
8.2.1 1-Tone CW
001aaj134 001aaj135
30 80 30
Gp D Gp
(dB) D (%) (dB)
28 60 28 (7)
(6)
(5)
Gp
26 40 26
(4)
(3)
(2)
(1)
24 20 24
22 0 22
0 100 200 300 400 500 0 100 200 300 400 500
PL (W) PL (W)
001aaj136
60
PL
(dBm)
58 ideal PL
(1)
56
PL
54
52
50
24 26 28 30 32 34
Ps (dBm)
8.2.2 2-Tone CW
001aaj137 001aaj138
30 80 0
Gp D IMD3
(dB) (%) (dBc) (1)
(2)
28 D 60 20 (3)
Gp
26 40 40
(4)
(5)
24 20 60
22 0 80
0 100 200 300 400 500 600 0 100 200 300 400 500 600
PL(PEP) (W) PL(PEP) (W)
VDS = 50 V; IDq = 1000 mA; f1 = 224.95 MHz; VDS = 50 V; f1 = 224.95 MHz; f2 = 225.05 MHz.
f2 = 225.05 MHz. (1) IDq = 600 mA
(2) IDq = 800 mA
(3) IDq = 1000 mA
(4) IDq = 1200 mA
(5) IDq = 1400 mA
Fig 13. Power gain and drain efficiency as functions of Fig 14. Third order intermodulation distortion as a
peak envelope load power; typical values function of peak envelope load power; typical
values
C20, C21
C3 multilayer ceramic chip capacitor 24 pF [1]
C10, C11
C8, C9 multilayer ceramic chip capacitor 4.7 F [1] TDK4532X7R1E475Mt020U
C12, C13 electrolytic capacitor 220 F; 63 V
C14, C15 multilayer ceramic chip capacitor 47 pf [1]
VDD
C12
VGG
R3 L3
C8
C7 C11
R2 L1
C14
T1 C23 C18
C1 C20 output
C3 C4 C5 C22 C16 C17 T3 50
input
50 T2 L6 L8 L9 L11
C2 C21
L5 L7 L10 L12 T4
C24 C19
C15
R1 L2
C6 C10
C9
L4 L4
VGG
C13
001aaj139
VDD
L3
R3
T1 C8 T3
C11
C7
C12
R2
L1 C14
C23
C18
C1 C3 C4 C5 C20
C22 C16 C17
11 mm 37 mm 11 mm 5 mm
C2 C24 3 mm C19 C21
L2 C15
R1
C6
C10
T2 C9 T4
R4 C13
L4
001aaj140
9. Package outline
A
F
D1
U1 B
q C
H1 w2 M C M
c
1 2
H U2 p E1 E
5 w1 M A M B M
L
A
3 4
b w3 M Q
e
0 5 10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT A b c D D1 e E E1 F H H1 L p Q q U1 U2 w1 w2 w3
5.33 11.81 0.15 31.55 31.52 9.50 9.53 1.75 17.12 25.53 3.73 3.30 2.31 41.28 10.29
mm 13.72 35.56 0.25 0.51 0.25
3.96 11.56 0.08 30.94 30.96 9.30 9.27 1.50 16.10 25.27 2.72 3.05 2.01 41.02 10.03
0.210 0.465 0.006 1.242 1.241 0.374 0.375 0.069 0.674 1.005 0.147 0.130 0.091 1.625 0.405
inches 0.540 1.400 0.010 0.020 0.010
0.156 0.455 0.003 1.218 1.219 0.366 0.365 0.059 0.634 0.995 0.107 0.120 0.079 1.615 0.395
SOT539A 99-12-28
00-03-03
10. Abbreviations
Table 11. Abbreviations
Acronym Description
CW Continuous Wave
EDGE Enhanced Data rates for GSM Evolution
GSM Global System for Mobile communications
HF High Frequency
LDMOS Laterally Diffused Metal-Oxide Semiconductor
LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor
RF Radio Frequency
TTF Time To Failure
VHF Very High Frequency
VSWR Voltage Standing-Wave Ratio
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term short data sheet is explained in section Definitions.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customers own risk.
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in Applications Applications that are described herein for any of these
modifications or additions. NXP Semiconductors does not give any products are for illustrative purposes only. NXP Semiconductors makes no
representations or warranties as to the accuracy or completeness of representation or warranty that such applications will be suitable for the
information included herein and shall have no liability for the consequences of specified use without further testing or modification.
use of such information. Limiting values Stress above one or more limiting values (as defined in
Short data sheet A short data sheet is an extract from a full data sheet the Absolute Maximum Ratings System of IEC 60134) may cause permanent
with the same product type number(s) and title. A short data sheet is intended damage to the device. Limiting values are stress ratings only and operation of
for quick reference only and should not be relied upon to contain detailed and the device at these or any other conditions above those given in the
full information. For detailed and full information see the relevant full data Characteristics sections of this document is not implied. Exposure to limiting
sheet, which is available on request via the local NXP Semiconductors sales values for extended periods may affect device reliability.
office. In case of any inconsistency or conflict with the short data sheet, the Terms and conditions of sale NXP Semiconductors products are sold
full data sheet shall prevail. subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
12.3 Disclaimers explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
General Information in this document is believed to be accurate and terms and conditions, the latter will prevail.
reliable. However, NXP Semiconductors does not give any representations or
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warranties, expressed or implied, as to the accuracy or completeness of such
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information and shall have no liability for the consequences of use of such
grant, conveyance or implication of any license under any copyrights, patents
information.
or other industrial or intellectual property rights.
Right to make changes NXP Semiconductors reserves the right to make
Quick reference data The Quick reference data is an extract of the
changes to information published in this document, including without
product data given in the Limiting values and Characteristics sections of this
limitation specifications and product descriptions, at any time and without
document, and as such is not complete, exhaustive or legally binding.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 2
6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Ruggedness in class-AB operation. . . . . . . . . . 4
7 Application information. . . . . . . . . . . . . . . . . . . 5
7.1 RF performance . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.1 1-Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.2 2-Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.3 Application circuit . . . . . . . . . . . . . . . . . . . . . . . 7
7.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
8.1 Impedance information . . . . . . . . . . . . . . . . . . 10
8.2 RF performance . . . . . . . . . . . . . . . . . . . . . . . 11
8.2.1 1-Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.2.2 2-Tone CW . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.2.3 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
12.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
13 Contact information. . . . . . . . . . . . . . . . . . . . . 17
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.