Presented at the 15the Nordic Semiconductor

Meeting, 8 -11 June, Hämeenlinna, Finland, 1992

SIMULATION OF AN ELECTRONIC LAMP

BALLAST CIRCUIT
M. Andersson, H. Pohjonen
Technical Research Centre of Finland, Semiconductor Laboratory
Olarinluoma 9, 02200 Espoo, Finland

ABSTRACT

As new power semiconductor devices are developed and reach maturity, it becomes
possible to improve the performance of existing power circuits by replacing their bipolar
power transistors with more advanced devices, for example DMOS power transistors. A
problem often encountered in these efforts is the lack of accurate models for power
semiconductor devices in commercial circuit simulators.
In this paper, the simulation environment for electronic lamp ballasts including
macromodeling capabilities is presented. The simulated performance of an electronic
lamp ballast circuit realized with DMOS transistors is compared to the measured and
simulated performance of the conventional bipolar version. A new macromodel including
the quasi-saturation effect for DMOS power transistors [1] is used for the simulations. The
simulations and measurements are in good agreement.

INTRODUCTION

In power applications changes in component performance affect not only to the particular
part where the component is located, but also to the performance - driving strategy, power
consumption and losses - of the whole system. The rapid development of discrete silicon
power devices offers possibilities to improve the products and speed up the development
cycle. However, this requires flexibility in device modeling and circuit simulation.
In switching power applications like electronic lamp ballasts, DMOS and/or IGBT
devices compete with conventional power bipolar transistors. The models required for
simulating these systems include DC and AC models accurate enough both in the linear
and saturation regions. This is extremely important in applications with varying loads like
fluorescent lamps, which show as a purely capacitive load during the startup phase and
have a more resistive nature in continuous operation.

THE ELECTRONIC BALLAST CIRCUIT

Fig. 1. shows a schematic picture of the electronic lamp ballast circuit. The mains rectifier,
the filter part and the lamp condition monitor parts are excluded. The control transformer
L1 - L3, the coil L4, the capacitances Ch, Cl and Ci, and the fluorescent lamp itself form a
resonance circuit with a frequency of 20 - 50 kHz. Voltages with opposite phase angels
are induced into the secondary coils L1 and L3 of the control transformer, so that the
bipolar npn power transistors Q1 and Q2 conduct alternately.
 VDC
~300 V
Q1 Ch

LAMP
L1
L2 L4
Ci
L3
Q2

Cl

GND
Figure 1. Electronic lamp ballast circuit realized with power bipolar transistors.

The fluorescent lamp is difficult to model because of its highly nonlinear behaviour.
During continouos operation, however, it can be modeled as a nonlinear, current-
dependent resistor which exhibits negative resistance at high currents. The lamp
characteristics have been found to influence the behaviour of the ballast circuit greatly,
and therefore the accuracy of the lamp model is very important.

Basically, the lamp ballast circuit based on the bipolar transistors is a resonator circuit
with sinusoidal driving base currents of transistors Q1 and Q2. Replacing these transistors
with DMOS type devices also requires changes in the driving waveforms from the
sinusoidal to the pulsed driving scheme, which is controlled externally, Fig. 2.
VDC
~300 V
M1 Ch
CONTROL

VG1 LAMP
L4
Ci
M2

VG2 Cl

GND

Figure 2. Simplified electronic lamp ballast circuit realized with power DMOS
transistors. The driving frequency is now generated by the control block.
THE DMOS MACROMODEL

During the startup phase, the fluorescent lamp as a capacitive load draws only few
milliamperes of current compared to the continuous operation with about 300 mA peak
lamp current. The bipolar transistor models implemented in circuit simulators are accurate
enough for describing linear and saturation areas in DC IV-characteristics both in low and
high power conditions below the breakdown region, Fig. 3a. For DMOS transistors
models available from discrete device manufacturers may have some weaknesses
especially in applications, where the loading conditions are not constant, Fig. 3 b. The
macromodel used in simulating the electronic lamp ballasts with DMOS type driving
transistors includes the SPICE level 3 model (MOS 3) and the quasisaturation effect
guaranteeing an average error between measured and simulated DC characteristics
smaller than 17% both for linear and saturation regions, Fig. 3c.

a)

b) c)
Figure 3. Measured () and simulated (----) I-V characteristics of a) power bipolar
transistor BUV46, b) power DMOS transistor IRF740 with macromodel from
the manufacturer, c) the same device as in b) but with developed macromodel.
For modeling AC characteristics it is necessary to extract capacitances CGD and CDS vs.
voltage by using the same approach as when extracting the basic DMOS macromodel DC
parameters: The open simulator environment APLAC [2], which also was used for the
system level simulations of the lamp ballast circuits. This method guarantees that the
device models used on the system level are exactly the same as used for the device level
parameter extraction.

SIMULATIONS OF THE ELECTRONIC LAMP BALLAST

The typical measured and simulated waveforms for the base and collector current of Q1
are shown in Fig. 4. Most of the circuit’s power consumption is due to the lamp and to the
bipolar transistors, which shows the need for more efficient power devices. The simulated
total power consumption is within 10% of the measured value, ~32 W.
 Figure 4. Measured () 0.3 0.8
and simulated (----) base IB1 [A] IC1 [A]
and collector currents of Q1. 0.1 0.6
The simulated waveforms
-0.1 0.4
are in good agreement with
the measured waveforms. -0.3 0.0

-0.5 -0.4
0.0 5.0 10.0 15.0 20.0
Time [µs]
Using DMOS type drivers, the gate voltage waveforms can be controlled more precisely,
Fig. 5. This strategy yields at least a 15% decrease in power consumption, depending on
the height and width of the gate voltage pulses, which can be optimized using APLAC.
Figure 5. Simulated drain 5.0 0.8
current of M1 driven using a VG1 [V] ID1 [A]
pulsed gate voltage. The 2.5 0.6
same waveform, in opposite
0.0 0.4
phase, is used for M2.
-2.5 0.0

-5.0 -0.4
0.0 30.0 60.0 90.0 120.0
Time [µs]

CONCLUSIONS

In demanding power applications, like electronic lamp ballasts, a flexible modeling and
simulation environment is needed for selecting critical components, optimizing the
system level performance and testing different driving strategies. This type of modeling
and design environment is also a necessity for effective, future monolithic integration of
the lamp ballast electronics.

ACKNOWLEDGEMENTS
This work was supported by Technology Development Centre (TEKES) and Helvar Oy.
Special thanks are due to Prof. Martti Valtonen and Mr. Jarmo Virtanen at the Circuit
Theory Laboratory, Helsinki University of Technology, for APLAC support and for
developing the model of the fluorescent lamp.

REFERENCES

1. M. Andersson, P. Kuivalainen: SPICE Macromodel for Power DMOS

Transistors. These Proceedings.
2. Helsinki University of Technology, Circuit Theory Laboratory & Nokia Research
Center, Hardware Design Technology: APLAC, An Object-Oriented Analog
Circuit Simulator and Design Tool, 6.0 User’s Manual & 6.0 Reference Manual,
October 1991.