module router_top (input [7:0] data_in, input

clock,resetn,read_enb_0,read_enb_1,read_enb_2,pkt_valid,
output [7:0] data_out_0,data_out_1,data_out_2,
output vld_out_0,vld_out_1,vld_out_2,err,busy);

wire [2:0]write_enb;
wire [7:0]dout;

router_fifo F1
(clock,resetn,soft_reset_0,write_enb[0],read_enb_0,lfd_state,dout,full
_0,fifo_empty_0,data_out_0);
router_fifo F2
(clock,resetn,soft_reset_1,write_enb[1],read_enb_1,lfd_state,dout,full
_1,fifo_empty_1,data_out_1);
router_fifo F3
(clock,resetn,soft_reset_2,write_enb[2],read_enb_2,lfd_state,dout,full
_2,fifo_empty_2,data_out_2);

router_sync SYNCH1
(clock,resetn,detect_add,full_0,full_1,full_2,fifo_empty_0,fifo_empty_
1,fifo_empty_2,write_enb_reg,read_enb_0,read_enb_1,
read_enb_2,data_in[1:0],
write_enb,fifo_full,vld_out_0,vld_out_1, vld_out_2,soft_reset_0,
soft_reset_1, soft_reset_2);

router_fsm FSM (clock, resetn,

pkt_valid,data_in[1:0],fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_
2,soft_reset_0,soft_reset_1,
soft_reset_2 ,parity_done,
low_pkt_valid,write_enb_reg,detect_add,ld_state,laf_state,lfd_state,fu
ll_state,rst_int_reg,busy);

router_reg REG (clock, resetn, pkt_valid,data_in,fifo_full,

detect_add, ld_state, laf_state, full_state, lfd_state, rst_int_reg,
err, parity_done, low_pkt_valid,dout);

endmodule
//////////////////////////////
module router_sync (input
clock,resetn,detect_add,full_0,full_1,full_2,
empty_0,empty_1,empty_2,write_enb_reg,read_enb_0,
read_enb_1, read_enb_2,input [1:0]data_in,
output reg [2:0]write_enb,output reg
fifo_full, output vld_out_0,
vld_out_1, vld_out_2,output reg
soft_reset_0, soft_reset_1, soft_reset_2);
reg [1:0]temp;
reg [4:0]count0;
reg [4:0]count1;
reg [4:0]count2;
always@(posedge clock)
begin
if(~resetn)
begin
temp<=2'b00;
end
else
begin
if(detect_add)
begin
temp<=data_in;
end
end
end
always@(*)
begin
case(temp)
2'b00: fifo_full=full_0;
2'b01: fifo_full=full_1;
2'b10: fifo_full=full_2;
default: fifo_full=0;
endcase
end

assign vld_out_0= ~empty_0;

assign vld_out_1= ~empty_1;
assign vld_out_2= ~empty_2;

always@(*)
begin
if(write_enb_reg)
begin
case(temp)
2'b00:write_enb=3'b001;
2'b01:write_enb=3'b010;
2'b10:write_enb=3'b100;
default : write_enb = 3'b000;
endcase
end
else
write_enb = 3'b000;
end

always@(posedge clock)
begin
if(~resetn)
begin
count0 <= 5'b0;
soft_reset_0 <=0;
end
else if (read_enb_0)
 begin
count0 <= 5'b0;
soft_reset_0 <= 0;
end
else if(vld_out_0 && ~read_enb_0 && count0 <29)
begin
count0 <= count0 +1'b1;
soft_reset_0 <=0;
end
else if(vld_out_0 && ~read_enb_0 && count0==29)
begin
soft_reset_0 <=1'b1;
count0 <= 5'b0;
end

end

always@(posedge clock)
begin
if(~resetn)
begin
count1 <= 5'b0;
soft_reset_1 <=0;
end
else if (read_enb_1)
begin
count1 <= 5'b0;
soft_reset_1 <= 0;
end
else if(vld_out_1 && ~read_enb_1 && count1<29)
begin
count1 <= count1+1;
soft_reset_1 <=0;
end
else if(vld_out_1 && ~read_enb_1 && count1==29)
begin
soft_reset_1 <=1'b1;
count1 <= 5'b0;
end

end
always@(posedge clock)
begin
if(~resetn)
begin
count2 <=5'b0;
soft_reset_2 <=0;
end
else if (read_enb_2)
begin
 count2 <= 5'b0;
soft_reset_2 <= 0;
end
else if(vld_out_2 && ~read_enb_2 && count2<29)
begin
count2<= count2+1;
soft_reset_2 <=0;
end
else if(vld_out_2 && ~read_enb_2 && count2==29)
begin
soft_reset_2 <=1'b1;
count2 <= 5'b0;
end

end

endmodule
/////////////////////////////////
module router_reg (input clock, resetn, pkt_valid,
input [7:0]data_in,
input fifo_full, detect_add, ld_state, laf_state,
full_state, lfd_state, rst_int_reg,
output reg err, parity_done, low_pkt_valid, output reg
[7:0]dout);

reg [7:0]header;
reg [7:0]fifo_full_state;
reg [7:0]internal_parity;
reg [7:0]packet_parity;

always@(posedge clock)
begin
if(~resetn)
begin
parity_done <= 0;
end

else if(detect_add)
begin
parity_done<=0;
end

else if( ld_state && ~fifo_full && ~pkt_valid)

parity_done <= 1'b1;

else if(laf_state && low_pkt_valid && ~parity_done)

parity_done <= 1'b1;

 end

always@(posedge clock)
begin
if(~resetn)
begin
low_pkt_valid <= 0;
end

else if(rst_int_reg)
begin
low_pkt_valid <= 0;
end
else if ( ld_state && ~pkt_valid)
begin
low_pkt_valid <= 1'b1;
end
end

always@(posedge clock)
begin
if(~resetn)
begin
dout <= 0;
//header <=0;
//fifo_full_state <= 0;
end
else if (lfd_state)
begin
dout <= header;
end
else if ( ld_state && ~fifo_full)
begin
dout <= data_in;
end
else if (laf_state)
begin
dout <= fifo_full_state;
end
end
always@(posedge clock)
begin
if(~resetn)
fifo_full_state <=8'b0;
else if ( ld_state && fifo_full)
begin
fifo_full_state <= data_in;
end
end
always@(posedge clock)
begin
if (detect_add && pkt_valid)
begin
header <= data_in;
end
end
always@(posedge clock)
begin
if(~resetn)
begin
packet_parity <= 0;
end

else if (detect_add)
begin
packet_parity <= 8'b0;
end

else if (( ld_state && ~pkt_valid ))

begin
packet_parity <= data_in;
end
end

always@(posedge clock)
begin
if(~resetn)
begin
internal_parity <= 0;
end
else if (lfd_state)
begin
internal_parity <= internal_parity ^ header;
end
else if ( ld_state && ~full_state && pkt_valid)
begin
internal_parity <= internal_parity ^ data_in;
end
end

always@(posedge clock)
begin
if(~resetn)
err <= 1'b0;
else
begin
if(parity_done)
begin
if ( packet_parity != internal_parity)
err <= 1'b1;
else
 err <= 1'b0;
end
else
err <= 0;

end
end
endmodule
/////////////////////////////////
module router_fsm (input clock, resetn, pkt_valid, input[1:0]data_in,
input fifo_full,

fifo_empty_0,fifo_empty_1,fifo_empty_2,soft_reset_0,soft_reset_1,
soft_reset_2 ,parity_done, low_pkt_valid, output
write_enb_reg,

detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,bu
sy);

parameter DECODE_ADDRESS = 8'b00000001;

parameter LOAD_FIRST_DATA = 8'b00000010;
parameter LOAD_DATA = 8'b00000100;
parameter LOAD_PARITY = 8'b00001000;
parameter FIFO_FULL_STATE = 8'b00010000;
parameter LOAD_AFTER_FULL = 8'b00100000;
parameter WAIT_TILL_EMPTY = 8'b01000000;
parameter CHECK_PARITY_ERROR = 8'b10000000;

reg[7:0]state,next_state;

always@(posedge clock)
begin
if(~resetn)
begin
state<=DECODE_ADDRESS;
end
else if (soft_reset_0 || soft_reset_1 || soft_reset_2)
state <= DECODE_ADDRESS;
else
begin
state<= next_state;
end
end
always@(*)
begin
next_state = DECODE_ADDRESS;
case(state)
DECODE_ADDRESS: begin
if((pkt_valid && (data_in[1:0]==0) &&
fifo_empty_0)||(pkt_valid &&(data_in[1:0]==1) && fifo_empty_1)||
(pkt_valid && (data_in[1:0]==2) &&
fifo_empty_2))
 begin
next_state=LOAD_FIRST_DATA;
end
if((pkt_valid && (data_in[1:0]==0) &&
~fifo_empty_0)||(pkt_valid && (data_in[1:0]==1) && ~fifo_empty_1)||
(pkt_valid && (data_in[1:0]==2) &&
~fifo_empty_2))
begin
next_state=WAIT_TILL_EMPTY;
end
end
LOAD_FIRST_DATA: next_state = LOAD_DATA;
LOAD_DATA: begin
if(fifo_full)
next_state=FIFO_FULL_STATE;
else if(~fifo_full && ~pkt_valid)
next_state=LOAD_PARITY;
else next_state = LOAD_DATA;
end
FIFO_FULL_STATE:begin
if(~fifo_full)
next_state=LOAD_AFTER_FULL;
else next_state= FIFO_FULL_STATE;
end
LOAD_AFTER_FULL:begin
if(~parity_done && ~low_pkt_valid)
next_state=LOAD_DATA;
if(~parity_done && low_pkt_valid)
next_state=LOAD_PARITY;
if(parity_done)
next_state=DECODE_ADDRESS;
end
LOAD_PARITY: begin
next_state=CHECK_PARITY_ERROR;
end
CHECK_PARITY_ERROR:begin
if(~fifo_full)
next_state=DECODE_ADDRESS;
if(fifo_full)
next_state=FIFO_FULL_STATE;
end
WAIT_TILL_EMPTY:begin

if(fifo_empty_0||fifo_empty_1||fifo_empty_2)
next_state=LOAD_FIRST_DATA;
if(~fifo_empty_0|| ~fifo_empty_1
||~fifo_empty_2)
next_state=WAIT_TILL_EMPTY;
end
endcase
end
assign write_enb_reg =(state==LOAD_DATA)||
(state==LOAD_PARITY)||(state==LOAD_AFTER_FULL) ? 1'b1 : 1'b0 ;
assign detect_add = (state==DECODE_ADDRESS)? 1'b1 : 1'b0;
assign ld_state =(state==LOAD_DATA) ? 1'b1 : 1'b0 ;
assign laf_state = (state==LOAD_AFTER_FULL) ? 1'b1 : 1'b0;
assign lfd_state = (state==LOAD_FIRST_DATA)? 1'b1 : 1'b0;
assign full_state = (state==FIFO_FULL_STATE)? 1'b1 : 1'b0;
assign rst_int_reg = (state==CHECK_PARITY_ERROR) ? 1'b1 : 1'b0;
assign busy = (state==DECODE_ADDRESS)||(state==LOAD_DATA) ? 1'b0 :
1'b1;

endmodule
////////////////////////////////

module router_fifo #(parameter WIDTH =9,DEPTH=16,ADDR=5)

(input
clock,resetn,soft_reset,write_enb,read_enb,lfd_state,
input [WIDTH-2:0]data_in,
output full,empty,
output reg [WIDTH-2:0]data_out);
reg [WIDTH-1:0]ram[DEPTH-1:0];
reg [ADDR-1:0]rd_ptr,wr_ptr;
integer i;
reg [5:0]count;
reg lfd_temp;

always@(posedge clock)
begin
lfd_temp <= lfd_state;
end

always@(posedge clock)
begin:B1
if(~resetn)
begin
for(i=0;i<DEPTH;i=i+1)
ram[i]<=8'd0;
end

else if(soft_reset)
begin
for(i=0;i<DEPTH;i=i+1)
ram[i]<=8'd0;
end
else if(write_enb && ~full)
begin

{ram[wr_ptr[3:0]][8],ram[wr_ptr[3:0]][7:0]}<={lfd_temp,data_in};
end

end
 always@(posedge clock)
begin
if(~resetn)

data_out <= 8'b0;

else if(soft_reset)
data_out <=8'dz;

else if(read_enb && ~empty)

{data_out}<=ram[rd_ptr[3:0]][7:0];
else if (count ==0)
data_out <= 8'dz;
end

always@(posedge clock)
begin
if(~resetn)

count <= 8'b0;

else if(soft_reset)
count <=8'dz;

else if (read_enb && ~empty)

begin
if (ram[rd_ptr[3:0]][8])
count<=(ram[rd_ptr[3:0]][7:2]+1'b1);

else if(count>0)
count<=count-1'b1;

else
begin
count<=0;
// data_out<=8'dz;
end

end
end
always@(posedge clock)
begin
if(~resetn)
begin
rd_ptr<=8'd0;wr_ptr<=8'd0;
end
else
begin
if(write_enb && ~full)

wr_ptr<=wr_ptr+1'b1;
 if (read_enb && ~empty)

rd_ptr<=rd_ptr+1'b1;
end
end

assign full = ((wr_ptr[4]==!rd_ptr[4]) && (wr_ptr[3:0]==rd_ptr[3:0]))

? 1'b1: 1'b0 ;
assign empty = (wr_ptr==rd_ptr)? 1:0;

endmodule