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www.ti.com PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011
www.ti.com PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

www.ti.com

www.ti.com PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

Voltage Output Programmable Sensor Conditioner

Check for Samples: PGA309

1 FEATURES

DESCRIPTION

2

– Span, Offset, and Temperature Drifts (pressure, strain, etc.). The calibration is done via a

– Uses External EEPROM (SOT23-5) The all-analog signal path contains a 2x2 input

Small TSSOP-16 Package The core of the PGA309 is the precision, low-drift, no 1/f noise Front-End PGA (Programmable Gain

Amplifier). The overall gain of the Front-End PGA + Output Amplifier can be adjusted from 2.7V/V to 1152V/V. The polarity of the inputs can be switched through the input mux to accommodate sensors with unknown polarity output. The Fault Monitor circuit

Automotive Sensors detects and signals sensor burnout, overload, and system fault conditions.

• Bridge Sensors

APPLICATIONS

Complete Bridge Sensor Conditioner The PGA309 is a programmable analog signal

Voltage Output: Ratiometric or Absolute conditioner designed for bridge sensors. The analog

Digital Cal: No Potentiometers/Sensor Trims

Sensor Error Compensation

Low Error, Time-Stable

Sensor Linearization Circuitry

signal path amplifies the sensor signal and provides digital calibration for zero, span, zero drift, span drift, and sensor linearization errors with applied stress

One-Wire digital serial interface or through a Two-Wire industry-standard connection. The calibration parameters are stored in external

Temperature Sense: Internal or External nonvolatile memory (typically SOT23-5) to eliminate

Calibration Lookup Table Logic

Over/Under-Scale Limiting

Sensor Fault Detection

manual trimming and achieve long-term stability.

multiplexer (mux), auto-zero programmable-gain instrumentation amplifier, linearization circuit, voltage reference, internal oscillator, control logic, and an

+2.7V TO +5.5V Operation output amplifier. Programmable level shifting

–40°C to +125°C Operation

compensates for sensor dc offsets.

• Remote 4-20mA Transmitters

• Strain, Load, and Weigh Scales

EVALUATION TOOLS

• Hardware Designer’s Kit (PGA309EVM)

– Temperature Eval of PGA309 + Sensor

– Full Programming of PGA309

– Sensor Compensation Analysis Tool

For detailed application information, see the PGA309 User's Guide (SBOU024) available for download at www.ti.com.

V S Nonlinear Linearization Ref VEXC Circuit Bridge PGA309 Transducer Lin DAC P Analog Sensor
V
S
Nonlinear
Linearization
Ref
VEXC
Circuit
Bridge
PGA309
Transducer
Lin DAC
P
Analog Sensor Linearization
psi
0
50
Fault
Auto- Zero
Over/Under
Linear
Monitor
V
PGA
Scale Limiter
OUT
Analog Signal Conditioning
+125 C
Digital
Digital Cal
Int Temp
T
Temperature
Compensation
Temp
Control Register
EEPROM
40 C
Ext Temp
ADC
Interface Circuitry
(SOT23-5)
Ext Temp

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.C Ext Temp ADC Interface Circuitry (SOT23-5) Ext Temp 2 All trademarks are the property of

2All

trademarks

are the property of their respective

owners.

date.

Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication

Copyright © 2003–2011, Texas Instruments Incorporated

SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

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PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011 www.ti.com

www.ti.com

– DECEMBER 2003 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION (1)

   

PACKAGE

PACKAGE

PRODUCT

PACKAGE-LEAD

DESIGNATOR

MARKING

PGA309

TSSOP-16

PW

PGA309

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.

 

PARAMETER

PGA309

UNIT

Supply Voltage, V SD , V SD

+7.0

V

Input Voltage, V IN1 , V IN2 (2)

–0.3 to V SA +0.3

V

Input Current, V FB , V OUT

±150

mA

Input Current

±10

mA

Output Current Limit

50

mA

Storage Temperature Range

–60 to +150

°C

Operating Temperature Range

–55 to +150

°C

Junction Temperature

+150

°C

ESD Ratings

Human Body Model (HBM)

4

kV

(1)

(2)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less.

2

Copyright © 2003–2011, Texas Instruments Incorporated

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SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, T A = –40°C to +125°C. At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL ; V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

     

PGA309

   

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Front-End PGA + Output Amplifier

         

V OUT /V IN Differential Signal Gain Range (1)

Fine gain adjust = 1

8

to 1152

V/V

Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128

Output Amplifier gains: 2, 2.4, 3, 3.6, 4.5, 6, 9

Input Voltage Noise Density

f

= 1kHz

210

nV/Hz

V OUT Slew Rate

 

0.5

V/ms

V OUT Settling Time (0.01%)

V OUT /V IN Differential gain = 8, R L = 5kΩ || 200pF

 

6

ms

V OUT Settling Time (0.01%)

V OUT /V IN Differential gain = 191, R L = 5kΩ || 200pF

4.1

ms

V OUT Nonlinearity

0.002

%FSR

External Sensor Output Sensitivity

V SA = V SD = V EXC = +5V

1 to 245

mV/V

Front-End PGA

         

Auto-Zero Internal Frequency

 

7

kHz

Offset Voltage (RTI) (2)

Coarse offset adjust disabled

±3

±50

mV

vs Temperature

±0.2

mV/°C

vs Supply Voltage, V SA

 

±2

mV/V

vs Common-Mode Voltage

G F = Front-End PGA gain

1500/G F

6000/G F

mV/V

Linear Input Voltage Range (3)

0.2

V SA 1.5

V

Input Bias Current

0.1

 

1.5

nA

Input Impedance: Differential

30

|| 6

 

GΩ || pF

Input Impedance: Common-Mode

50

|| 20

GΩ || pF

Input Voltage Noise

0.1Hz to 10Hz, G F = 128

4

mV

PP

PGA Gain

   

Gain Range Steps

4, 8, 16, 23.27, 32, 42.67, 64, 128

4

to 128

V/V

Initial Gain Error

G F = 4 to 42

0.2

 

±1

%

 

G F = 64

0.25

±1.2

%

G

F = 128

0.3

±1.6

%

vs Temperature

   

10

ppm/°C

Output Voltage Range

0.05 to V SA 0.1

V

Bandwidth

 

Gain = 4

400

kHz

Gain = 128

 

60

kHz

Coarse Offset Adjust (RTI of Front-End PGA)

         

Range

±(14)(V REF )(0.00085)

±56

±59.5

±64

mV

vs Temperature

0.004

%/°C

Drift

±14 steps, 4-bit + sign

 

4

mV

Fine Offset Adjust (Zero DAC) (RTO of the Front-End PGA) (2)

         

Programming Range

0

V

REF

V

Output Voltage Range

0.1

V SA – 0.1

V

Resolution

65,536 steps, 16-bit DAC

 

73

mV

Integral Nonlinearity

20

LSB

Differential Nonlinearity

0.5

LSB

Gain Error

0.1

%

Gain Error Drift

 

10

ppm/°C

Offset

5

mV

Offset Drift

10

mV/°C

(1)

PGA309 total differential gain from input (V IN1 – V IN2 ) to output (V OUT ). V OUT / (V IN1 – V IN2 ) = (Front-end PGA gain) × (Output Amplifier

(2)

gain) × (Gain DAC). RTI = Referred-to-input. RTO = referred to output.

(3)

Linear input range is the allowed min/max voltage on the V IN1 and V IN2 pins for the input PGA to continue to operate in a linear region. The allowed common-mode and differential voltage depends on gain and offset settings. Refer to the Gain Scaling section for more information.

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T A = –40°C to +125°C. At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL ; V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

     

PGA309

 

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Output Fine Gain Adjust (Gain DAC) Range Resolution Integral Nonlinearity Differential Nonlinearity

   

0.33 to 1

 

V/V

65,536 steps, 16-bit DAC

10

mV/V

20

LSB

0.5

LSB

Output Amplifier Offset Voltage (RTI of Output Amplifier) (4) vs Temperature vs Supply Voltage, V SA Common-Mode Input Range Input Bias Current Amplifier Internal Gain Gain Range Steps Initial Gain Error

   

3

 

mV

5

mV/°C

30

mV/V

0

V S – 1.5

V

100

pA

2, 2.4, 3, 3.6, 4.5, 6, 9 2, 2.4, 3.6

2 to 9

V/V

0.25

±1

%

 

4.5

0.3

±1.2

%

6

0.4

±1.5

%

9

0.6

±2.0

%

vs Temperature

2, 2.4, 3.6

5

ppm/°C

4.5

5

ppm/°C

6

15

ppm/°C

9

30

ppm/°C

Output Voltage Range (5) Open-Loop Gain Gain-Bandwidth Product Phase Margin Output Resistance

R L = 10kΩ

0.1

4.9

V

115

dB

2

MHz

Gain = 2, C L = 200pF AC Small-signal, open-loop, f = 1MHz, I O = 0

45

deg

675

Over- and Under-Scale Limits Over-Scale Thresholds

V REF = 4.096 Ratio of V REF , Register 5—bits D5, D4, D3 = ‘000’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘001’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘010’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘011’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘100’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘101’ Ratio of V REF , Register 5—bits D5, D4, D3 = ‘110’

 

0.9708

   

0.9610

0.9394

0.9160

0.9102

0.7324

0.5528

Over-Scale Comparator Offset Over-Scale Comparator Offset Drift Under-Scale Thresholds

 

+6

+60

+114

mV

+0.37

mV/°C

Ratio of V REF , Register 5—bits D2, D1, D0 = ‘111’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘110’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘101’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘100’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘011’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘010 Ratio of V REF , Register 5—bits D2, D1, D0 = ‘001’ Ratio of V REF , Register 5—bits D2, D1, D0 = ‘000’

0.0605

 

0.0547

0.0507

0.0449

0.0391

0.0352

0.0293

0.0254

Unde-rScale Comparator Offset Under-Scale Comparator Offset Drift

 

7

50

+93

mV

0.15

mV/°C

(4)

(5)

RTI = Referred-to-input. RTO = referred to output. Unless limited by the over/under-scale setting.

4

Copyright © 2003–2011, Texas Instruments Incorporated

Product Folder Link(s): PGA309

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SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T A = –40°C to +125°C. At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL ; V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

     

PGA309

 
 

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Fault Monitor Circuit

           

INP_HI, INN_HI Comparator Threshold

See (6)

V SA 1.2 or V EXC 0.1

V

INP_LO, INN_LO Comparator Threshold

40

100

 

mV

A1SAT_HI, A2SAT_HI Comparator Threshold

V SA 0.12

V

A1SAT_LO, A2SAT_LO Comparator Threshold

V SA 0.12

V

A3_VCM Comparator Threshold

 

V SA 1.2

V

Comparator Hysteresis

20

mV

Internal Voltage Reference

           

V

REF1

Register 3, bit D9 = 1

2.46

2.5

2.53

V

V REF1 Drift vs Temperature

 

+10

ppm/°C

V

REF2

I PU

Register 3, bit D9 = 0

4.0

4.096

4.14

V

V REF2 Drift vs Temperature

+10

±7

ppm/°C

Input Current REF IN /REF OUT

Internal V REF disabled

100

mA

Output Current REF IN /REF OUT

V SA > 2.7V for V REF = 2.5V

1

mA

 

V SA > 4.3V for V REF = 4.096V

1

mA

Temperature Sense Circuitry (ADC)

           

Internal Temperature Measurement

Register 6, bit D9 = 1

xx

Accuracy

±2

°C

xx

Resolution

12-Bit + sign, twos complement data format

±0.0625

°C

xx

Temperature Measurement Range

55

+150

°C

xx

Conversion Rate

R 1 , R 0 = ‘11’, 12-bit + sign resolution

24

ms

Temperature ADC

           

External Temperature Mode

Temp PGA + Temp ADC

1 to 8

V/V

xx

Gain Range Steps

G PGA = 1, 2, 4, 8

GND 0.2

V SA +0.2

V

xx

Analog Input Voltage Range

Temperature ADC Internal REF (2.048V)

Register 6, bit D8 = 1

xx

Full-Scale Input Voltage

(+Input) (Input)

±2.048/G PGA

V

xx

Differential Input Impedance

2.8/G PGA

MΩ

xx

Common-Mode Input Impedance

G PGA = 1

3.5

MΩ

 

G PGA = 2

3.5

MΩ

G PGA = 4

1.8

MΩ

G PGA = 8

0.9

MΩ

xx

Resolution

R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 8ms

11

Bits + Sign

 

R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 32ms

13

Bits + Sign

R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 64ms

14

Bits + Sign

R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 128ms

15

Bits + Sign

xx

Integral Nonlinearity

0.004

%

xx

Offset Error

G PGA = 1

1.2

mV

 

G PGA = 2

0.7

mV

G PGA = 4

0.5

mV

G PGA = 8

0.4

mV

xx

Offset Drift

G PGA = 1

1.2

mV/°C

 

G PGA = 2

0.6

mV/°C

G PGA = 4

0.3

mV/°C

G PGA = 8

0.3

mV/°C

(6)

When V EXC is enabled, a minimum reference selector circuit becomes the reference for the comparator threshold. This minimum reference selector circuit uses V EXC 100mV and V SA 1.2V and compares the V INX pin to the lower of the two references. This configuration ensures accurate fault monitoring in conditions where V EXC might be higher or lower than the input CMR of the PGA input amplifier relative to V SA .

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T A = –40°C to +125°C. At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL ; V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

     

PGA309

 
 

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Temperature ADC. continued

           

xx

Offset vs V SA

G PGA = 1

800

mV/V

 

G PGA = 2

400

mV/V

G PGA = 4

200

mV/V

G PGA = 8

150

mV/V

xx

Gain Error

0.05

0.50

%

xx

Gain Error Drift

5

50

ppm/°C

xx

Noise

All gains

< 1

LSB

xx

Gain vs V SA

80

ppm/V

xx

Common-Mode Rejection

At dc and G PGA = 8

105

dB

 

At dc and G PGA = 1

100

dB

Temp ADC Ext. REF (V REFT = V REF , V EXC , or V SA )

Register 6, bit D8 = 0

xx

Full-Scale Input Voltage

(+Input) (Input)

±V REFT /G PGA

V

xx

Differential Input Impedance

2.4/G PGA

MΩ

xx

Common-Mode Input Impedance

G PGA = 1

8

MΩ

 

G PGA = 2

8

MΩ

G PGA = 4

8

MΩ

G PGA = 8

8

MΩ

xx

Resolution

R1, R0 = ‘00’, ADC2X = ‘0’, conversion time = 6ms

11

Bits + Sign

 

R1, R0 = ‘01’, ADC2X = ‘0’, conversion time = 24ms

13

Bits + Sign

R1, R0 = ‘10’, ADC2X = ‘0’, conversion time = 50ms

14

Bits + Sign

R1, R0 = ‘11’, ADC2X = ‘0’, conversion time = 100ms

15

Bits + Sign

xx

Integral Nonlinearity

0.01

%

xx

Offset Error

G PGA = 1

2.5

mV

 

G PGA = 2

1.25

mV

G PGA = 4

0.7

mV

G PGA = 8

0.3

mV

xx

Offset Drift

G PGA = 1

1.5

mV/°C

 

G PGA = 2

1.0

mV/°C

G PGA = 4

0.7

mV/°C

G PGA = 8

0.6

mV/°C

xx

Gain Error

0.2

%

xx

Gain Error Drift

2

ppm/°C

xx

Gain vs V SA

80

ppm/V

xx

Common-Mode Rejection

At dc and G PGA = 8

100

dB

 

At dc and G PGA = 1

85

dB

External Temperature Current Excitation

I TEMP

Register 6, bit D11 = 1

xx

Current Excitation

5.8

7

8

mA

xx

Temperature Drift

5

nA/°C

xx

Voltage Compliance

V SA 1.2

V

Copyright © 2003–2011, Texas Instruments Incorporated

Product Folder Link(s): PGA309

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SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T A = –40°C to +125°C. At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL ; V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

     

PGA309

 
 

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Linearization Adjust and Excitation Voltage (V EXC ) Range 0

         

Register 3, bit D11 = 0 With respect to V FB ±127 steps, 7-bit + sign With respect to V REF

xx

Linearization DAC Range

0.166 to +0.166

V/V

xx

Linearization DAC Resolution

1.307

 

mV/V

xx

V EXC Gain

0.83

V/V

xx

Gain Error Drift

 

25

ppm/°C

Range 1

Register 3, bit D11 = 1 With respect to V FB ±127 steps, 7-bit + sign With respect to V REF

xx

Linearization DAC Range

0.124 to +0.124

V/V

xx

Linearization DAC Resolution

0.9764

 

mV/V

xx

V EXC Gain

0.52

V/V

xx

Gain Error Drift

 

25

ppm/°C

V EXC Range Upper Limit

I EXC = 5mA Short-circuit V EXC output current

V SA 0.5

V

I EXC SHORT

50

mA

Digital Interface Two-Wire Compatible One-Wire Maximum Lookup Table Size (7) Two-Wire Data Rate

Bus speed Serial speed baud rate

1

 

400

kHz

4.8K

38.4K

Bits/s

 

17 x 3 x 16

Bits

PGA309 to EEPROM (SCL frequency)

65

kHz

Logic Levels Input Levels (SDA, SCL, PRG, TEST) Input Levels (SDA, SCL, PRG, TEST) Input Levels (SDA, SCL) Pull-Up Current Source (SDA, SCL) Pull-Down Current Source (TEST) Output LOW Level (SDA, SCL, PRG)

Low

   

0.2 • V SD

V

High

0.7 • V SD

V

Hysteresis

0.1 • V SD

V

55

85

125

mA

15

25

40

mA

Open drain, I SINK = 5mA

0.4

V

Power Supply

         

V SA, V SD

2.7

5.5

V

I SA + I SD , Quiescent Current

V SA = V SD = +5V, without bridge load

1.2

1.6

mA

Power-On Reset (POR) Power-Up Threshold Power-Down Threshold

V S rising V S falling

 

2.2

2.7

V

1.7

V

Temperature Range Specified Performance Range Operational-Degraded Performance Range

 

–40

 

+125

°C

–55

+150

°C

(7)

Lookup table allows multislope compensation over temperature. Lookup table has access to 17 calibration points consisting of three adjustment values (Tx, Temperature, ZMx, Zero DAC, GMx, Gain DAC) that are stored in 16-bit data format (17x3x16 = Lookup table size).

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PIN CONFIGURATION

PW PACKAGE

TSSOP-16

(TOP VIEW) 1 16 REF /REF V EXC IN OUT GND A 2 15 TEMP
(TOP VIEW)
1 16
REF
/REF
V EXC
IN
OUT
GND A
2 15
TEMP IN
V
3 14
SDA
SA
V
4 13
SCL
IN1
5 12
PRG
V IN2
6 11
GND D
V FB
7 10
V OUT
V SD
8 9
TEST
V SJ
PIN DESCRIPTIONS

PIN NO.

NAME

DESCRIPTION

1

V

EXC

Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation is to be used.

2

GND A

Analog ground. Connect to analog ground return path for V SA . Should be same as GND D .

3

V

SA

Analog voltage supply. Connect to analog voltage supply. To be within 200mV of V SD .

4

V

IN1

Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA.

5

V

IN2

Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change connection internally to Front-End PGA.

   

V OUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain set resistors for the output amplifier are used, this is also the voltage feedback sense point for the

6

V

FB

output amplifier. V FB in combination with V SJ allows for ease of external filter and protection circuits without degrading the PGA309 V OUT accuracy. V FB must always be connected to either V OUT or the point of feedback for V OUT , if external protection is used.

7

V

OUT

Analog output voltage of conditioned sensor.

8

V

SJ

Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive loads (> 100pF) and/or for using external gain setting resistors for the output amplifier.

9

TEST

Test/External controller mode pin. Pull to GND D in normal mode.

10

V

SD

Digital voltage supply. Connect to digital voltage supply. To be within 200mV of V SA .

11

GND D

Digital ground. Connect to digital ground return path for V SD . Should be same as GND A .

   

Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a

12

PRG

single wire. Can be connected to V OUT for a three-lead (V S , GND, V OUT ) digitally-programmable sensor assembly.

   

Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital

13

SCL

calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface.

   

Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital

14

SDA

calibration and configuration from external EEPROM. Can also communicate directly to the registers in the PGA309 through the Two-Wire, industry-standard compatible interface.

   

External temperature signal input. PGA309 can be configured to read a bridge current sense resistor as an indicator of bridge temperature, or an external temperature sensing device such as diode

15

TEMP IN

junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input can be read differentially with respect to V GNDA , V EXC , or the internal/external V REF . There is also an internal, register-selectable, 7mA current source (I TEMP ) that can be connected to TEMP IN as an RTD, thermistor, or diode excitation source.

   

Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is

16

REF IN /REF OUT

available for system use on this pin. As an input, the internal reference may be disabled and an external reference can then be applied as the reference for the PGA309.

Copyright © 2003–2011, Texas Instruments Incorporated

Product Folder Link(s): PGA309

www.ti.com PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011
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SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

REF (V)

I B (nA)

V

CMRR (dB)

I TEMP ( A)

PSRR (dB)

Gain (dB)

TYPICAL CHARACTERISTICS

At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL , V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

4.090

4.085

4.080

4.075

4.070

4.065

4.060

V REF vs TEMPERATURE

Average
Average
Average
Average
Average
Average
Average
Average

Average

Average
Average
Average
Average
Average
Average

55

35

15

5

25

45

65

85

Temperature ( C)

Figure 1.

105

125

145

I TEMP CURRENT vs TEMPERATURE

9

8

7

6

5

4

3

2

1

0

Average
Average
Average
Average
Average
Average
Average
Average
Average
Average
Average
Average
Average

Average

Average
Average
Average
Average

55

35

15

5

25

45

65

85

Temperature ( C)

Figure 3.

105

125

145

POWER-SUPPLY REJECTION RATIO vs FREQUENCY

90

80

70

60

50

40

30

20

10

0

10

V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V

V

V

REF

REF

=

and

PSRR at

V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V EXT V OUT Enabled
V EXT V OUT Enabled
V EXT V OUT Enabled

V EXT

V OUT

V EXT V OUT Enabled

Enabled

V EXT V OUT Enabled
V EXT V OUT Enabled
Small-Signal 2.5V
Small-Signal
2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V
V V REF REF = and PSRR at V EXT V OUT Enabled Small-Signal 2.5V

10

100

10k

Frequency (Hz)

1k

Figure 5.

100k

1M

I B CURRENT vs TEMPERATURE

1.0

0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA

Average,

nA

Average, nA
Average, nA
Average, nA
Average, nA
Average, nA
Average, nA

55

35

15

5

25

45

65

85

Temperature ( C)

Figure 2.

105

125

145

COMMON-MODE REJECTION RATIO vs FREQUENCY

70

60

50

40

30

20

10

0

10

20

30

RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA

RTO

of Front- End

PGA

RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA
RTO of Front- End PGA

10

100

10k

Frequency (Hz)

1k

Figure 4.

100k

1M

CLOSEDLOOP GAIN vs FREQUENCY

80

60

40

20

0

G OUTAMP

G OUTAMP G G

G

G

= Output

Amplifier Gain

G

G

OUTAMP

FRONT

= 9V/V

= 128V/V

Amplifier Gain G G OUTAMP FRONT = 9V/V = 128V/V G OUTAMP = 9V/V G FRONT

G

OUTAMP

= 9V/V

G

FRONT

= 32V/V

= 2V/V

= 8V/V

G

G

OUTAMP

FRONT

= 2V/V

= 32V/V

OUTAMP FRONT
OUTAMP
FRONT

10

100

10k

Frequency (Hz)

1k

Figure 6.

100k

1M

Copyright © 2003–2011, Texas Instruments Incorporated

Product Folder Link(s): PGA309

9

SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011 www.ti.com
PGA309 SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011 www.ti.com

www.ti.com

Temp ADC Error ( C)

Total Error (% of FS)

TYPICAL CHARACTERISTICS (continued)

At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL , V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

V

V

V

V

V

S

S

S

S

S

V S

0.1

0.2

0.3

0.4

0.5

0.5

0.4

0.3

0.2

0.1

0

V OUT SWING TO RAIL vs I LOAD

V = 2.7V V = 5V S S V = 5V S V S =
V
= 2.7V
V
= 5V
S
S
V
= 5V
S
V S = 2.7V
0
5
10
15
20
25
I
(mA)
LOAD
I Q (mA)

Figure 7.

TEMPERATURE ADC ERROR (INTERNAL MODE)

0.4

0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15
ADC ERROR (INTERNAL MODE) 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 55 35 15

55

35

15

5

25

45

65

85

105

125

145

Actual Die Temperature ( C)

Figure 9.

V REF NOISE (0.1Hz TO 10Hz)

V = 4.096V REF Measured After Bandpass Filter 0.1Hz Second-Order High-Pass 10Hz Fourth-Order Low-Pass 50
V
= 4.096V
REF
Measured After Bandpass Filter
0.1Hz Second-Order High-Pass
10Hz Fourth-Order
Low-Pass
50
V/div

1s/div

Figure 11.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

I Q vs TEMPERATURE

All Blocks Enabled Ref, Exc, and ADC Disabled
All

All

All
All
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled

Blocks Enabled

Ref, Exc,

and ADC Disabled

All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled
All Blocks Enabled Ref, Exc, and ADC Disabled

55

35

15

5

25

45

65

85

Temperature ( C)

Figure 8.

105

125

145

TEMPERATURE ADC ERROR (EXTERNAL MODES)

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4

Reg 6 = 0503h Reg 6 = 0433h V = 2.048V Internal V = 2.5V
Reg 6 = 0503h
Reg 6 = 0433h
V
= 2.048V Internal
V
= 2.5V Internal
REF
REF
(Temp ADC Internal)
15-Bit
+ Sign
15-Bit
+ Sign
Reg 6 =
0430h
V
REF
= 2.5V Internal
11-Bit + Sign
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6
+ Sign Reg 6 = 0430h V REF = 2.5V Internal 11-Bit + Sign Reg 6

Reg 6 =

0403h

V REF

= 5V Internal

15-Bit + Sign

100

80

60

40

Input Signal (% FS of V

20

0

20

40

REF

)

60

80

100

Figure 10.

V OUT NOISE (0.1Hz TO 10Hz PEAK-TO-PEAK NOISE)

V = +61mV G = 1152 IN CLK_CFG = 00 (default) Coarse Offset = 59mV
V
= +61mV
G = 1152
IN
CLK_CFG = 00
(default)
Coarse
Offset = 59mV
Measured After Bandpass
Filter
0.1Hz Second-Order High-Pass
10Hz Fourth-Order Low-Pass
1mV/div

1s/div

Figure 12.

Copyright © 2003–2011, Texas Instruments Incorporated

Product Folder Link(s): PGA309

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www.ti.com

SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011

e ND ( V/ Hz ), RTI

e ND ( V/ Hz ), RTI

TYPICAL CHARACTERISTICS (continued)

At T A = +25°C, V SA = V SD = +5V (V SA = V SUPPLY ANALOG , V SD = V SUPPLY DIGITAL , V SA must equal V SD ), GND D = GND A = 0, and V REF = REF IN /REF OUT = +5V, unless otherwise noted.

INPUT VOLTAGE NOISE DENSITY

10

1

0.1

0.01

Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)

Coarse Offset Adjust

V IN

= +61mV

= 59mV

CLK_CFG = 00 (default)

Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)
Coarse Offset Adjust V IN = +61mV = 59mV CLK_CFG = 00 (default)