3.

Transceiver Design

3.1 Introduction
The drive for lower cost and hence system-on-chip (SoC) design has inevitably brought
up CMOS technology as a serious contender. The cost of low complexity subcircuits such as
amplifiers and mixers is determined by primarily packaging and testing, rather than chip area. On
the other hand, with single-chip transceivers and the prospect of integrating the digital baseband
processor along with the RF and analog functions, the cost equation is heavily weighted by the
chip area and therefore the integrated circuit (IC) technology.

3.2 Technology Trends in RFIC’s

This section attempts to provide some insights into the current trends and research in the
area of low cost RF front ends. Currently, a great amount of research is underway to improve the
power efficiency and lower the cost of the circuits used in the present generation of wireless
products. The general approach taken towards this goal is to move towards higher levels of
integration in cheap silicon based technologies, such as BiCMOS (combination of bipolar and
CMOS transistors on the same substrate) and CMOS.
There are several factors that contribute to the significantly lower cost of circuits
manufactured on Silicon substrates compared with other semi-conductor materials, such as GaAs
and SiGe. First, processes for CMOS and BiCMOS circuits provide higher yields (fewer defects
per wafer). Secondly, the high volume of orders enjoyed by CMOS fabrication facilities helps
reduce the cost of such circuits through economies of scale.
Finally, analog circuits implemented in CMOS can be easily integrated on the same substrate
with the digital baseband processing circuits for a truly optimal single chip implementation of the
system.
 The traditional approach towards the design of wireless transceivers has been to use
GaAs or SiGe based circuits for the realization of the RF components such as power amplifiers,
low noise amplifiers, and switches. Silicon based analog circuits are then used for the IF to
baseband sections and possibly the RF mixers. In these approaches, band selection at RF and IF
are typically performed using discrete off chip components. This eliminates the difficulties
associated with the realization of high-Q filters on chip. Most conventional approaches also
utilize external tuned LC resonators to provide the tuning element of the VCO. The high Qs
realized by the external elements are critical in ensuring good VCO phase-noise.
The above mentioned trend is still evident in the latest series of “integrated” transceivers
for wireless data applications [1] [2] [3]. The reason for this partitioning will become clearer in
the ensuing section, however, at this point it is worth noting that in general GaAs is fast, provides
high gain, high selectivity (high Qs), and has lower noise than silicon based circuits, on the other
hand Si based circuits are cheaper and can be used in mixed-mode circuits where digital and
analog functionality is realized on the same substrate.
In an attempt to eliminate the need for the GaAs components and enjoy the cost savings
associated with Silicon based circuits, researchers within industry and universities are looking
for ways of realizing the same functionality now provided by GaAs based circuits on a Silicon
substrate, at the expense of some degradation in the overall performance of the block. This was
first initiated with Silicon bipolar circuits due to the traditionally higher bandwidths of these
devices. However, in recent years advances in the development of CMOS processes and circuits
have brought bandwidths, fT, of these transistors to levels comparable with Silicon bipolar
transistors. Consequently, researchers have also started to consider the use CMOS at RF.
In addition to implementing RF sub-blocks of a traditional super-heterodyne
architectures, researchers are also investigating a host of alternative transceiver architectures
which will help eliminate the need for high-Q, lossy, off-chip filters [4] [5].
Overall, these activities will help take us one step closer to the ultimate goal of a single chip
radio which integrates, RF, IF, analog-baseband, D/A and all the required baseband signal
processing on the same substrate. Over the past several years, a number of entities have
successfully demonstrated CMOS building blocks such as mixers oscillators and amplifiers
[6][7][8][9] for operation in the cellular and the 900 MHz ISM bands. With the continuing trend
towards the availability of smaller transistor dimensions, this trend is moving towards the PCS
bands and beyond.

3.3 Oscillators in Transceivers

Oscillators play a critical role in communication systems, providing the periodic signals
needed for the timing of digital circuits and for frequency translation. While “oscillator” can
mean anything that exhibits periodically time-varying characteristics, we are concerned with the
type that provides an electrical signal (voltage or current) at a specific frequency when supplied
only with DC power. When used for frequency translation, we often refer to an oscillator as the
local oscillator (LO), as opposed to oscillators used as clocks for timing digital circuits.[10]
While LOs and clocks can be derived from the same basic oscillator, we will focus on the
function, performance, and design of oscillators used as LOs for frequency translation in radio
transceivers.

3.4 Receiver & Transmitter Architectures

3.4.1 Receiver Architecture
Following are the different types of receiver architectures
a) Heterodyne Receiver
b) Homodyne Receiver(also called zero- IF or direct-conversion architecture)
c) Digital-IF Receivers
Out of these, Heterodyne Receiver is the most widely used one.
However, a major advantage of the heterodyne receiver structure is its adaptability to many
different receiver requirements. That is why it has been the dominant choice in RF systems for
many decades. However, the complexity of the structure and the need for a large number of
external components (e.g., the IF filter) make problems if a high level of integration is necessary.
This is also the major drawback if costs are concerned. Furthermore, amplification at some high
IF can cause high power consumption
3.4.2 Transmitter architecture
Following are the two main types of receiver architectures
a) Direct Conversion Transmitter
b) Heterodyne Transmitter
Here we are not emphasizing more on receiver and transmitter, information about them is
commonly available in many literatures and assumed that is known to reader.

3.5 Performance Issues

The most critical specification for any oscillator is its spectral purity, usually
characterized by phase noise. Since many wireless transceivers such as mobile phones are
battery-powered, we also strive to minimize power consumption. There is a trade-off between
phase noise and power consumption up to a point, beyond which increased power consumption
cannot be tolerated by practical devices.

3.5.1 Phase Noise

Ideally, the spectrum of an oscillator is an impulse located at a single frequency.
However, in any practical oscillator, the spectrum has power distributed around the desired
oscillation frequency ω 0 , in addition to power located at harmonic frequencies, as shown in Fig.
3.1. This undesirable power distribution around the desired oscillation frequency is known as
phase noise. The origins of phase noise will be discussed in Chapter6..

Fig.3.1 Practical oscillator spectrum.

3.5.2 Power Consumption

Phase noise is inversely proportional to the power dissipated in the resistive part of
the resonant LC tank. [10] This seems to suggest that an arbitrarily small phase noise can be
achieved by simply increasing the bias current, but there are practical limitations as to how
small phase noise can be made.
As bias current is increased, so is the VCOs output voltage amplitude. However, any
CMOS transistor has a maximum voltage that cannot be exceeded without permanent damage.
 Also, in the usual situation where the n-well in a PMOS device is tied to the power supply, the
drain cannot exceed the power supply voltage by more than about 0.6 volts before the drain-
well diode is turned on, resulting in clipping of the output voltage.
As a result, bias current is usually limited by the process. Moreover, since the VCO is
likely to be incorporated in a battery-powered transceiver, we would like to minimize current
consumption to maximize battery life.

3.6 Summary
Over the past few years, the RF design paradigm has followed four important trends:
• Due to the integration capabilities of CMOS technology, RF transceiver architectures
have markedly departed from the conventional heterodyne approach, including far greater
on-chip complexity in favor of minimizing the number of external components.
• High-resolution low-power analog-to-digital converters employing new methods of
improving the dynamic range have emerged as an integral part of transceivers.
• Numerous low-voltage low-noise RF and baseband circuit techniques have been invented
that circumvent the limitations of MOS transistors.
• Extensive research on passive monolithic devices such as inductors and varactors has led
to accurate models and hence ease of use in circuit design. In this section, we present
design techniques that exemplify the above trends.

3.7 References
[1] K. Irie, H. Matsui, T. Endo, et. al., “A 2.7V GSM RF Transceiver IC,” in IEEE ISSCC
`97 Digest, Feb. 1997, pp. 302-303.
[2] S. Heinen, K. Hadjizada, U. Matter, et. al. “A 2.7V 2.5 GHz Bipolar Chipset for Digital
Wireless Communication,” in IEEE ISSCC `97 Digest, pp. 306-307.
[3] R. G. Meyer, W. D. Mack, J. Hageraats, “A 2.5 GHz BiCMOS Transceiver for Wireless
LAN,” in IEEE ISSCC `97 Digest, Feb. 1997, pp. 310-311.
[4] B. Razavi, “Challenges in Portable RF Transceiver Design,” IEEE Circuits and Devices
Magazine, Sept. 1996, pp. 12-25.
[5] A. Abidi, “Low-Power Radio Frequency IC's for Portable Communications,”
Proceedings of the IEEE, Vol. 83, No. 4, April 1995, pp. 544-569.
[6] S. Wong, H. Bhimnathwala, S. Luo, B. Halai, S. Navid, “A 1 W 830 MHz monolithic
BiCMOS Power Amplifier,” IEEE ISSCC `96 Digest, pp. 52-53.
[7] M. Rofougaran, et. al., “A 900 MHz CMOS RF power amplifier with programmable
output,” 1994 Symposium on VLSI Circuits Digest of Technical papers, pp. 133-134.
[8] N. Karanicolas, “A 2.7V 900 MHz CMOS LNA and Mixer,” in IEEE ISSCC `96 Digest,
vol. 39, pp. 50-51, Feb. 1996.
[9] J. Craninckx, M.S.J. Steyaert, “A 1.8-GHz CMOS Low-Phase Noise Voltage-Controlled
Oscillator with Prescaler,” IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp.
1474-1482, Dec. 1995.
[10] N. Sneed, “A 2-GHz CMOS LC-Tuned VCO using Switched-Capacitors to Compensate
for Bond Wire Inductance Variation” University of California Berkeley, 2000