Introduction to

CMOS VLSI
Design

Delay Calculations
Transient Response

DC analysis tells us Vout if Vin is constant

Transient analysis tells us Vout(t) if Vin(t) changes

Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

MOS equations CMOS VLSI Design

Simulated Inverter Delay

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically

Uses more accurate I-V models too!

But simulations take time to write
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)

MOS equations CMOS VLSI Design

Delay Definitions

tpdr: rising propagation delay

From input to rising output crossing VDD/2

tpdf: falling propagation delay

From input to falling output crossing VDD/2

tpd: average propagation delay

tpd = (tpdr + tpdf)/2

tr: rise time

From output crossing 0.2 VDD to 0.8 VDD

tf: fall time

From output crossing 0.8 VDD to 0.2 VDD

MOS equations CMOS VLSI Design

Delay Definitions

tcdr: rising contamination delay

From input to rising output crossing VDD/2

tcdf: falling contamination delay

From input to falling output crossing VDD/2

tcd: average contamination delay

tpd = (tcdr + tcdf)/2

MOS equations CMOS VLSI Design

Delay Estimation

We would like to be able to easily estimate delay

Not as accurate as simulation

But easier to ask What if?

The step response usually looks like a 1st order RC response
with a decaying exponential.

Use RC delay models to estimate delay

C = total capacitance on output node

Use effective resistance R

So that tpd = RC

Characterize transistors by finding their effective R

Depends on average current as gate switches

MOS equations CMOS VLSI Design

 RC Delay Models

Use equivalent circuits for MOS transistors

Ideal switch + capacitance and ON resistance

Unit nMOS has resistance R, capacitance C

Unit pMOS has resistance 2R, capacitance C

Capacitance proportional to width

Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

MOS equations CMOS VLSI Design

 Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2 Y 2
A
1 1

MOS devices CMOS VLSI Design

 Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2C

2C
2C
2 Y 2
A Y
1 1
C
R C

MOS devices CMOS VLSI Design

 Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

MOS devices CMOS VLSI Design

 Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

MOS devices CMOS VLSI Design

Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

MOS equations CMOS VLSI Design

Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

MOS equations CMOS VLSI Design

Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2 2 2

3
3
3

MOS equations CMOS VLSI Design

3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2 2 2

MOS equations CMOS VLSI Design

3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C

3C
3
3C
3C
3
3C
3C
3
3C
3C

MOS equations CMOS VLSI Design

3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2 2 2

3 9C
5C
3 3C
5C
3 3C
5C

MOS equations CMOS VLSI Design

 Elmore Delay

ON transistors look like resistors

Pullup or pulldown network modeled as RC ladder

Elmore delay of RC ladder
t pd
nodes i
Ri to sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

R1 R2 R3 RN

C1 C2 C3 CN

MOS equations CMOS VLSI Design

Example: 2-input NAND

Estimate worst-case rising and falling delay of 2-input NAND
driving h identical gates.

2 2 Y
h copies
A 2
B 2x

MOS equations CMOS VLSI Design

Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

MOS equations CMOS VLSI Design

Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

R
Y
(6+4h)C
t pdr =

MOS equations CMOS VLSI Design

Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

R
Y t pdr = ( 6 + 4h ) RC
(6+4h)C

MOS equations CMOS VLSI Design

Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

MOS equations CMOS VLSI Design

 Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

R/2
R/2
x
2C
Y
(6+4h)C t pdf =

MOS equations CMOS VLSI Design

 Example: 2-input NAND

Estimate rising and falling propagation delays of a 2-input
NAND driving h identical gates.

2 2 Y
A 2 6C 4hC h copies

B 2x 2C

x R/2
t pdf = ( 2C ) ( R2 ) + ( 6 + 4h ) C ( R2 + R2 )
Y

= ( 7 + 4h ) RC
R/2 2C (6+4h)C

MOS equations CMOS VLSI Design

Delay Components

Delay has two parts

Parasitic delay

6 or 7 RC

Independent of load

Effort delay

4h RC

Proportional to load capacitance

MOS equations CMOS VLSI Design

Contamination Delay

Best-case (contamination) delay can be substantially less than
propagation delay.

Ex: If both inputs fall simultaneously

2 2 Y
A 2 6C 4hC

B 2x 2C

R R
Y tcdr = ( 3 + 2h ) RC
(6+4h)C

MOS equations CMOS VLSI Design