Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]

Technology Dept. of Electrical and Electronic Engineering (EEE)

Contents

No Experiment Name
1 Verification of Gates
2 Half Adder and Full Adder using Logic gates
3 Half Subtractor and Full Subtractor Logic gates
4 Parallel Adder and Subtractor
4 Excess 3 to BCD and Vce Versa
5 Binary Grey & Grey Binary Converter
6 MUX and DEMUX
7 MUX and DEMUX using NAND Gates
8 Comparators
9 Encoder and Decoder
10 Flip Flops
11 Counters
12 Shift Registers
13 Johnson and Ring Counters
14 Multivibrators
 Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)

Experiment No: 01

Experiment Name: Verification of Gates

Objective: To Study and verify the truth table of logic gates.

Aparatus :

1. AND gate (7408 LS)

2. NOT Gate (7404 LS)
3. OR Gate (7432 LS)
4. NAND Gate (7400 LS)
5. XOR Gate (7486 LS)
6. XNOR Gate ()

Procedure:

1. Place the IC on IC Trainer Kit

2. Connect Vcc and ground to respective pins of IC
3. Connect the inputs to the inputs swictches provided in the IC trainer Kit
4. Connects the outputs of the IC to the switches of O/P LEDs
5. Apply various combinations of inuts according to the truth table and observe the outputs
in LEDs
6. Disconnect the outputs from the LEDs and note down the corrosponding multimeter
voltage reading for various combinations of inputs.
Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)
Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)

2 Input NOR
 Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)

Experiment No: 02

Experiment Name: Half Adder and Full Adder using Basic Gates

Objective:

1. Realize Half Adder using XOR and Basic Gates

2. Realize Full Adder using XOR and Basic Gates
3. Realize Half Adder using NAND Gates
4. Realize Full Adder using NAND Gates

Procedure:

1. Verify the Combinational Circuits

2. Make the connection as per the circuit diagram
3. Switch on Vcc and apply various combinations of inputs according to the truth table
4. Note down the ourput reading for various combinations of inputs
Shahjalal University of Science and [DEGITAL ELECTRONICS LAB MANUAL]
Technology Dept. of Electrical and Electronic Engineering (EEE)