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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Double Logarithmic Arithmetic Technique for
Low-Power 3-D Graphics Applications
Dina M. Ellaithy, Magdy A. El-Moursy, Ghada H. Ibrahim, Amal Zaki, and Abdelhalim Zekry
Abstract An energy efficient double logarithmic arith-
metic (DLA) technique is proposed for 3-D graphics applications.
DLA manipulates the logarithmic arithmetic and improves the
architecture for the realization of the transcendental functions
and the advanced lighting model using energy efficient tech-
niques. The DLA features complete elimination of multipliers in
logarithmic domain by using successive logarithmic converters.
DLA demonstrates up to 56% reduction in power consumption
as compared to the existing techniques. The main advantage of
this approach is the ability to perform the complex functions
using power-efficient, area-efficient, as well as high frequency
design. The proposed technique performs transcendental func-
tions using multiplier free hardware architecture. Moreover,
based on nonuniform subdivisions and piecewise linear approxi-
mation, novel logarithmic and antilogarithmic converters are also
proposed. These converters achieve optimal power consumption
as compared to several recent approaches. The proposed convert-
ers provide low relative error with less nonuniform subdivisions.
Up to 19%, 12%, and 20% reduction in relative error, area, and
power consumption are achieved, respectively.
Index Terms Antilogarithmic converter, double logarith-
mic arithmetic (DLA) unit, graphical processing unit (GPU),
logarithmic arithmetic unit, logarithmic converter, low power.
I. I NTRODUCTION
T HE conventional implementation of an arithmetic unit
focuses primarily on maximizing the speed of realizing
computationally intensive real-time functions, such as gaming,
graphics, GPS navigation, and video compression. However,
the emerging need to perform the computation with low-
power consumption is barely taken into account. The fast
growth of the mobile electronics market and the transition from
text-based applications to versatile multimedia applications
resulted in increasing the popularity of mobile communi-
cation devices. Real-time 3-D graphics are becoming one
of the most interesting applications in mobile workstations
due to their benefits for gaming, advertising, marketing, and
avatars. Also, for bandwidth-constrained wireless applications
such as complex 3-D scenes, 3-D graphics are very helpful.
Manuscript received September 22, 2016; revised December 1, 2016 and
January 17, 2017; accepted January 26, 2017.
D. M. Ellaithy G. H. Ibrahim A. Zaki are with the Microelectronics
Department, Electronics Research Institute, Cairo, Egypt (e-mail: dina_
elessy@eri.sci.eg; ghadahamdy@yahoo.com; amalzaki@gmail.com).
M. A. El-Moursy is with the Design Creation Division, Mentor Graphics,
Cairo, Egypt and also with Microelectronics Department, Electronics Research
Institute, 12622, Cairo, Egypt (e-mail: magdy_el-moursy@mentor.com).
A. Zekry is with Electronics and Communications Department, Ain Shams
University, Cairo, Egypt (e-mail: aaazekry@hotmail.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2017.2667714
1063-8210 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
Complex 3-D scenes can be represented using lists of vertices,
texture images, and equivalent camera movements, producing
high data-compression ratios [1]. General purpose proces-
sors are commonly used in graphics applications. In con-
trast to general processors, typical 3-D graphical processing
units (GPUs) handle complex arithmetic calculations, such
as division, reciprocating, squaring, square-rooting, and expo-
nentiation operations. These functions use most of the clock
cycles in real-time 3-D graphics systems. As a result of that,
they consume most of the computing power [2]. Handheld
3-D graphics processors adopt programmable functionality.
Those processors are mainly composed of vertex and pixel
shaders to support various advanced graphics effects. These
shaders perform complex vector, elementary, and transcen-
dental functions, such as vector multiply-and-add, division,
exponentiation, logarithm to any base, and trigonometric
functions (TRG) [3]. It can be claimed that, low-power
consumption is one of the most important bottlenecks for
wireless applications because of the limited battery lifetime
and complex cooling techniques. Cooling has become a real
bottleneck with the increased sophistication of mobile devices.
Digital electronic circuits tend to become much less reliable at
high operating temperatures. Accordingly, reducing the power
consumption of the arithmetic unit inside the programmable
shaders is the main target for the optimization effort. Since
logarithmic number system (LNS) affects the signal activity
and the strength of the operators, using logarithmic numbers
can lead to large savings in power consumption [4]. In certain
cases, the mean bit assertion probability is reduced by above
50% if LNS is employed, which leads to significant power dis-
sipation reduction [5]. Therefore, using logarithmic arithmetic
unit for GPU reduces the power dissipation and simplifies
the arithmetic calculations [2][12]. The overall architecture
of logarithmic arithmetic units still includes programmable
multipliers, which are usually implemented using booth mul-
tipliers. Booth multipliers are still needed to perform complex
functions [6][10].
Double logarithmic arithmetic (DLA) with reduced hard-
ware complexity for energy efficient GPU arithmetic is pro-
posed. The architecture of the vertex shader with DLA is
shown in Fig. 1. Logarithmic and antilogarithmic converters
are the main blocks of DLA. Computation error and power
consumption are ongoing challenges for researchers involved
in 3-D graphics applications. For this sake, a new set of con-
verters are proposed. Compared to several recent approaches,
the proposed converters have lower relative error with simpler
hardware implementation which reduce the overall area and
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 1. Architecture of the vertex shader with DLA.
power consumption. The proposed DLA hardware occupies
smaller area and consumes less power and is suited for mobile
applications. The rest of this paper is arranged as follows. The
previous research in this area is presented in Section II. DLA
scheme is explained in Section III. In Section IV, the proposed
logarithmic and antilogarithmic converters are presented. Error
analysis and comparison with other techniques are demon-
strated in Section V. Hardware implementation and synthesis
results of the proposed technique along with the comparison
with the previous research are presented in Section VI. Finally,
Section VII contains some conclusions.
II. BACKGROUND
The 3-D graphics rendering is the main workload of GPU.
GPU rendering is responsible for projecting 3-D scene onto
2-D screen. Basically, the 3-D graphics rendering pipeline is
composed of vertex shader and pixel shader. Transformation
and lighting functions of geometric vertices are handled by
the vertex shader. Pixel shader takes the generated prepixel
data, and uses linear equation and linear interpolation to
determine the actual color of the pixels. Thereafter, skinning
and mapping are carried out [12]. Realization of these various
kinds of complex operations with limited power resources is
a challenge. Power and area overheads for the programmable
3-D graphics pipeline can be reduced in logarithmic arith-
metic scheme. In logarithmic arithmetic unit, multiplication,
Fig. 2. Original architecture of the logarithmic arithmetic unit.
division, squaring, and square rooting can be obtained by
simple addition, subtraction, and shift operations. Previously,
complicated functions such as exponentiation, logarithm to
any base, and TRG are converted into multiplication, which
is usually implemented using booth multiplier, as reported
in [4][12]. At the first stage, the operands of the inputs are
converted into the logarithmic number format. Then, linear
addition, subtraction, shift and multiplication are performed.
At the end, the results which are computed in logarithmic
domain are transformed to fixed point by the antilogarithmic
converter, as shown in Fig. 2. Especially for large operands,
multiplication has always been area, time, and power con-
suming mathematical process [4]. In Section III, the proposed
approach to reduce power consumption by completely elimi-
nating multiplication is presented.
On the other hand, logarithmic and antilogarithmic convert-
ers are the core of the logarithmic arithmetic. The logarith-
mic converter is responsible for converting the input binary
number to logarithmic number. A straight-line approximation
is defined by Mitchell to determine the binary logarithm
for power-of-two segments [13]. The converter by Mitchell
has a simple architecture which results in a small hard-
ware implementation with large conversion error. A simple
piecewise linear approximation by Abed and Siferd [14] is
used for logarithmic conversion. Abed and Siferd [14] use
combinational logic in the implementation to achieve low
power and high speed while reducing the maximum percentage
error of the conversion. Several approaches were adopted to
optimize logarithmic converters accuracy, power consumption,
and area.
Antilogarithmic converters are responsible for transforming
the computing results in the logarithmic domain to the final
fixed point domain. Several researches have been done on
antilogarithmic converters based on the straight-line and piece-
wise linear approximation representations. Based on linear
approximations, Mitchell [13] presented an efficient conver-
sion method. However, the provided scheme does not have
sufficient accuracy. Many converter algorithms are proposed
to increase the conversion accuracy on the price of complexity
and hardware implementation difficulty. For low power,
Abed et al. [15] have developed and implemented
antilogarithm correction algorithm which slightly decreases
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ELLAITHY et al.: DLA TECHNIQUE
Fig. 3. Fixed-point format Qm.n of the x number.
the accuracy. The proposed DLA in this paper might be
useless without improving the logarithmic and antilogarithmic
converters accuracy. A wide range of studies in this area have
been done so far [14][24]. Digital recurrence, ROM or lookup
table, and piecewise approximation are among the primary
used techniques for logarithmic and antilogarithmic converters
approximations. Piecewise linear approximation techniques
give good tradeoff between the computation error and the
complexity of hardware and the power consumption. They are
widely used in many applications [15], [18], [20], [21], [23].
A new piecewise linear approximation technique is proposed
in order to achieve low conversion error using simple
hardware for logarithmic and antilogarithmic converters in
Section IV. The proposed converters make tradeoff between
accuracy and hardware complexity by using nonuniform
segmentation and less conversion terms in each segment
compared to prior research [2], [3], [18], [20][23]. For being
accurate and efficient in power, the conversion coefficients
can be realized by few shift and add operations as shown in
this paper.
III. P ROPOSED DLA A PPROACH
A second logarithm stage is added in DLA to eliminate
the need for any multiplier in logarithmic domain. The
second stage replaces multiplications by additions in a second
logarithmic domain. Thus, large amount of power reduc-
tion is achieved. The 3-D graphics programmable shaders
require complex transcendental, and lighting model functions
to provide various graphics effects [7]. The implementation
of these functions in the proposed technique is presented in
Sections III-AIII-C.
A. DLA Architecture
In DLA, the input operands are transformed into the loga-
rithmic domain. Some operands go through single logarithmic
stage and others go through double logarithmic stages. Then,
linear addition, subtraction, and shift are performed in the
logarithmic domain. The results in the logarithmic domain
are converted into fixed point domain by the antilogarithmic
converter.
The transformation between the fixed-point and logarithmic
numbers has conversion error. It is shown in this paper that
the error could be manipulated to make DLA efficient with
low power and limited error. Fixed-point DLA system can
be effective for handheld 3-D graphics systems that have a
small screen accuracy. This makes DLA efficient in trading-
off accuracy with power. As shown in Fig. 3, a fixed-point
number x has the configuration of Qm.n, where m and n
correspond to the integer and fraction number of bits. The
five most significant bits represent the integer part and the
remaining twenty-seven bits represent the fraction part.
3
Fig. 4. Architecture of the DLA for exponentiation operation.
The DLA for exponentiation function is shown in Fig. 4.
The two inputs, x and y are converted into the LNS/format,
which requires one logarithmic converter for the input y to get
log2 y. A pair of cascaded logarithmic converters for the input
x are used to get log2 log2 x. Linear additions are carried out by
adding log2 y and log2 log2 x. Finally, the result of the addition
in LNS/format is converted to fixed point number through two
successive stages of antilogarithmic converters. DLA adopts
unifying the implementation of transcendental functions to a
definite arithmetic unit using a simple hardware to maintain the
small size and to achieve low-power design as in the following
section.
B. Transcendental Functions
The transcendental functions such as, exponentiation of
arbitrary exponent, logarithm to any base, trigonometric,
inverse trigonometric, hyperbolic, or inverse hyperbolic func-
tions can be converted into addition in LNS as follows.
1) The exponentiation function can be computed using
addition in LNS according to
[(log2 y)+(log2 log2 x)]
x y = 22 (1)
where x and y are the input operands. The results of the
addition are transformed into fixed-point domain by two
stages of antilogarithm converters.
2) The logarithm to base b, can be converted into addition,
according to
logb x = 2[(log2 K )+(log2 log2 x)] (2)
1
k = . (3)
log2 b
3) The TRG can be described by definite Taylor series
expansions. Concerning the initial five terms of the
Taylor series calculation, a general process of the TRG
is defined as
TRG = c0 x k0 c1 x k1 c2 x k2 c3 x k3 c4 x k4 (4)
where {+, } ci is real, ki are integer constants,
and i {0:4}. Using this generic equation represen-
tation (for example, Taylor series approximations as
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
si n x = x x3/3! + x5/5! x7/7! + x9/9!, and
cos x = 1 x2/2! + x4/4! x6/6! +
x8/8!, the calculation of the exponentiations
which is required for this process can be
transformed to addition in LNS by convert-
ing (4) to (5)
TRG = 2log2 c0 +A0 2log2 c1 +A1 2log2 c2 +A2
2log2 c3 +A3 2log2 c4 +A4
[(log2 K i )+(log2 log2 x)]
Ai = 2 . (6)
Each term in (5) requires only addition in LNS with
constant log2 ci , avoiding using multipliers.
C. Lighting Model Equations
Inside 3-D graphics, lighting process determines the final
pixel color from the direction of the light source, 3-D object,
and camera [11]. In most of the rendering, illuminations
in vertex shader inject intensive effort-load [12], [25], [26].
The Phong illumination pattern is used in general to achieve
prevertex lights [12]. For Phong pattern, color C of a vertex
is resolved by
C = Camb + {(N L)Cdiff } + {(N H)Cpow Cspec
where Camb is the ambient light, N is normal vector of vertex,
L is direction vector of light, Cdiff is the diffuse light, and
H is half vector between direction vector of eye and normal
vector of vertex. Cpow is shinny factor, which is determined by
texture. The last term Cspec is computed for specular lighting
by complex power operation.
The lighting equation involves a very large amount of
calculations and very complicated arithmetic processes. They
consist of multiplication and exponentiation that consume
large amount of power [11]. In the presented approach,
the multiplication and the exponentiation are converted into
addition by transforming (7) into
[(log2 A1 )+(log2 C diff )] [(log2 A3 )+(log2 C spec )]
C = Camb + 2 +2
[(log2 N)+(log2 L)]
A1 = 2
A2 = 2[(log2 N)+(log2 H )]
2[(log2 Cpow )+(log2 log2 A2 )]
A3 = 2 . (11)
In Section IV, the proposed logarithmic and antilogarithmic
converters are presented.
IV. L OGARITHMIC AND A NTILOGARITHMIC C ONVERTERS
DLA increases the error in the processed data. The
primary building blocks of the DLA are the logarith-
mic and antilogarithmic converters. Since logarithmic and
antilogarithmic curves are nonlinear, large uniform segments
are needed to provide good precision. To overcome the
straight-line limitations on accuracy, nonuniform segments are
required [12], [21]. The selection of the conversion coeffi-
cients has a great impact on the hardware complexity. The
nonuniform segments and the conversion coefficients for each
segment are selected by using a linear programming to make
a compromise between accuracy and hardware complexity.
(5)
Fig. 5. Proposed algorithm for logarithmic/antilogarithmic converters.
For the logarithmic conversion, the error increases as the
input value is close to 1 so a fine segments are needed
close to 1. Starting approximately at the middle of the
antilogarithmic conversion, coarser steps make it faster to find
the best tradeoff between accuracy and hardware complexity.
The segments and the conversion coefficients of each seg-
ment are obtained using MATLAB software by matching the
approximation coefficients to the actual values. The obtained
segments and coefficients simplify the hardware implemen-
tation with best accuracy and minimum segments. In Fig. 5,
the proposed algorithm that is used to obtain the sub-segments
(7)
and the conversion coefficients is shown. In the next subsec-
tions, the proposed logarithmic/antilogarithmic converters are
presented.
A. Proposed Logarithmic Converters
A novel set of nonuniform piecewise linear approximation
logarithmic converters are presented in this section. The input
x can be presented by (12) and its logarithm by (13)
x = 2k (1 + f ) (12)
log2 x = k + log2 (1 + f ) (13)
where k is the characteristic or integer portion which repre-
sents the place of the most significant bit of x and f is the
(8)
fraction portion. Based on piecewise linear approximation
(9)
(10) log2 (1 + f ) f + f + (14)
where and are the conversion coefficients which are
distinct for each segment. In this paper, two lower error
logarithmic converters are proposed having either nine or six
regions. The nonuniform regions and the coefficient values
for each region are listed in Tables I and II for nine and six
regions, respectively. Column 1 in Tables I and II contains the
nonuniform regions which are used to obtain the approximate
value of log2 . The proposed conversion coefficient values
and for each region are listed in columns 2 and 3, respec-
tively. The proposed antilogarithmic converters are presented
in Section IV-B.
B. Proposed Antilogarithmic Converters
A novel set of nonuniform piecewise linear approximation
antilogarithmic converters are presented in this section. The
logarithmic number x can be presented by (15) and its
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ELLAITHY et al.: DLA TECHNIQUE
TABLE I
P ROPOSED N INE N ONUNIFORM R EGIONS L OGARITHMIC
C ONVERTER W ITH I TS C ONVERSION C OEFFICIENT
TABLE II
P ROPOSED S IX N ONUNIFORM R EGIONS L OGARITHMIC
C ONVERTER W ITH I TS C ONVERSION C OEFFICIENT
antilogarithm by (16)
x =k+ f
2 = 2 .2
x k f
where k is the integer portion and f is the fraction portion.
Based on piecewise linear approximation
2f f +
where and are the conversion coefficients which are
distinct for each segment. In this paper, two low error antilog-
arithmic converters are proposed with either eight or four
regions. The nonuniform regions and the coefficient values for
each region are listed in Tables III and IV. The nonuniform
regions which are used to obtain the approximate value of 2 x
are listed in column 1 of Tables III and IV. Columns 2 and 3
contain the proposed conversion coefficient values and
for each region. In the next section, error analysis and com-
parisons with the recent techniques are presented.
V. E RROR A NALYSIS AND C OMPARISONS
For high precision, several previous converters were pro-
posed [2], [3], [14], [15], [18], [20][23]. MATLAB software
is used to obtain the error for the previous work and the
proposed one using different conversion coefficients. In Fig. 6,
the error graphs for [2], [3], [18], [21], and [22], and the
5
TABLE III
P ROPOSED E IGHT N ONUNIFORM R EGIONS A NTILOGARITHMIC
C ONVERTER W ITH I TS C ONVERSION C OEFFICIENT
TABLE IV
P ROPOSED F OUR N ONUNIFORM R EGIONS A NTILOGARITHMIC
C ONVERTER W ITH I TS C ONVERSION C OEFFICIENT
(15)
(16)
(17) Fig. 6. Error of logarithmic converters with proposed nine-region.
proposed nine-region logarithmic converter are shown. The
error graphs for [14], [18], and [21], and the proposed six-
region logarithmic converter are shown in Fig. 7. The error
graphs of previous work for antilogarithmic converters and
the proposed one are shown in Figs. 8 and 9. The work
in [2], [3], [15], [20], [22], and [23], and the proposed eight
and four regions antilogarithmic converters are compared.
It is shown in the error graphs for logarithmic converters
that most of previous techniques suffer from large percent
error in the first region (in Fig. 6 the first region was not
taken into consideration). Selina [23] uses a lot of terms for
the conversion coefficients to achieve higher precision which
leads to more power consumption, larger area and hardware
complexity. From the next Figs. 69, it is shown that the
proposed logarithmic and antilogarithmic converters achieve
higher accuracy as compared to prior work. The error is
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 7. Error of logarithmic converters with proposed six-region.
Fig. 8. Error of antilogarithmic converters with proposed eight-region.
Fig. 9. Error of antilogarithmic converters with proposed four-region.
defined by
 
(approximated value - exact value)
error% =
exact value
The results are summarized in Tables V and VI. The first
column contains the used technique. The number of segments
is listed in the second column. The maximum positive error
and the minimum negative error are listed in third and fourth
columns, respectively. The last column contains the difference
between the values of third and fourth columns which is
defined as the error range.
As compared to many previous techniques, the proposed
converters achieve higher precision. The accuracy is increased
by up to 19% for both the proposed nine-region and six-region
logarithmic converters, and by up to 11% for both the proposed
TABLE V
E RROR C OMPARISON B ETWEEN THE P ROPOSED L OGARITHMIC
C ONVERTERS AND P REVIOUS W ORK
TABLE VI
E RROR C OMPARISON B ETWEEN THE P ROPOSED A NTILOGARITHMIC
C ONVERTERS AND P REVIOUS W ORK
100. eight-region and four-region antilogarithmic converters. Since
the conversion coefficients values are combination of power
(18)
of two, logarithmic/antilogarithmic converters can be imple-
mented using shift-and-add approach. Hardware structure of
the proposed logarithmic converters is shown in Fig. 10(a).
The logarithmic converter scheme is based on leading one
detector that determines the characteristic value k. The bits
following the leading one are then shifted and added by the
shifter/adder block to obtain the required approximation loga-
rithmic value. The adder is implemented using carry save adder
3:2 or 4:2 and carry propagating adder (CPA). In Fig. 10(b),
the hardware structure of the proposed antilogarithmic con-
verters is shown. Similarly, the structure of the antiloga-
rithmic converters is based on the sum of shifts approach.
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ELLAITHY et al.: DLA TECHNIQUE 7

TABLE VIII
C OMPARISON B ETWEEN THE P ROPOSED A NTILOGARITHMIC
C ONVERTERS AND P REVIOUS W ORK IN T ERMS OF
P OWER , A REA , AND D ELAY

Fig. 10. (a) Architecture of the proposed logarithmic converters.

(b) Architecture of the proposed antilogarithmic converters.
TABLE VII
C OMPARISON B ETWEEN THE P ROPOSED L OGARITHMIC C ONVERTERS AND
P REVIOUS W ORK IN T ERMS OF P OWER , A REA , AND D ELAY

TABLE IX
C OMPARISON B ETWEEN THE DLA AND P REVIOUS W ORK IN
T ERMS OF P OWER , A REA , D ELAY, AND AVERAGE E RROR

The integer part contains the value of the characteristic k

which is used for the final right shifter to obtain the approxi-
mation antilogarithmic result.

VI. H ARDWARE I MPLEMENTATION AND

S YNTHESIS R ESULTS
The proposed converters and all previous work are imple-
mented at a structural level Very High Speed Integrated
Circuit Hardware Description Language. Different logarithmic
and antilogarithmic techniques are synthesized using 90 nm
CMOS technology, standard cell library with the Synopsys
Design Compiler. The power consumption, area, and delay
for the proposed techniques are compared with prior work
and are summarized in Tables VIIIX. It can be noted that
for logarithmic converters in Table VII, the proposed nine-
region logarithmic converter achieves saving of at least 20% in
power consumption as compared to Lastras and Parhami [22]
technique with 51% higher precision. As compared with
Nam et al. [3] technique, at least 54%, 43%, and 29%
saving in power, area, and delay, are achieved respectively,
with 19% higher precision. The proposed six-region loga-
rithmic converter achieves more than 3% reduction in power
consumption as compared with De Caro et al. [18] technique
with 19% higher precision.
For antilogarithmic converters in Table VIII, the proposed
eight-region achieves more than 35% and 26% saving in power
and area, respectively as compared to Selina [23] technique
with 9% lower precision. As compared to Kim et al. [2]
technique, more than 23%, 8%, and 18% reduction in
area, delay, and precision are achieved, respectively, with
approximately the same power consumption. The proposed
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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
four-region antilogarithmic converter achieves more than 12%
reduction in power consumption and area as compared
to Kuo and Parhami [20] technique with 11% higher
precision. As compared to Selina [23] technique, more
than 42% and 43% saving in power and area are achieved
with 23% lower precision. On average, the proposed nine-
region logarithmic converter achieves saving up to 35%, 9%,
and 8% in power, area, and delay, respectively. On average,
saving of the proposed eight-region antilogarithmic converter
is up to 8%, and 17% in power and area. For the proposed
four-region antilogarithmic converter, the average saving is up
to 43%, and 27% in power and area.
32-bit fixed-point DLA unit is also implemented at a struc-
tural level by VHDL. It is also synthesized by the Synopsys
Design Compiler. A CPA is used for the addition that is
shown in Fig. 4 to obtain the final results in the logarithm
domain in DLA. A booth multiplier is used for comparison
with the previous work that is shown in Fig. 2. The proposed
technique is implemented using 90 nm CMOS technology,
1 V supply voltage standard cell library, and is running
at 100 MHz. The proposed technique reduces both power
dissipation and area. A comparison between DLA and prior
designs for exponentiation operation, using same technology
is summarized in Table IX. The first column contains the
technique name. Columns 2 to 5 contain power consumption,
area, delay, and average error, respectively. In the first com-
parison, rows 2 and 3, the proposed six-region logarithmic
converter is used with the proposed four-region antilogarithmic
converter due to the simplicity of hardware implementation.
In the second comparison, row 5, the proposed nine-region
logarithmic converter and the proposed eight-region antiloga-
rithmic converter are used which gives a good tradeoff between
conversion error and hardware complexity.
Using DLA, the average error is increased by less than 0.6%
with a reduction in power of up to 51%, and a reduction
in area, and delay larger than 40% and 48%, respectively.
The DLA technique provides saving in power, area, and delay
by at least 43%, 7%, and 45%, respectively, as compared to
conventional techniques.
VII. C ONCLUSIONS
DLA is proposed to perform complex functions and light-
ing model equations without the need for multiplications in
GPUs. The proposed technique can perform the transcen-
dental operations using simple hardware architecture. Loga-
rithmic and antilogarithmic converters based on nonuniform
segments and piecewise linear approximations are enhanced
in this paper. The proposed converters achieve lower error
ranges as compared to prior recent proposed techniques.
Up to 19% and 11%, reduction in error is achieved with the
proposed logarithmic converter, and antilogarithmic converter,
respectively. The proposed logarithmic converters provide sav-
ing of at least 20% in power. At least 13% and 12% saving in
power and area are achieved, respectively, for the proposed
antilogarithmic converters. DLA is implemented using the
90-nm CMOS technology. Avoiding the multiplication in
logarithmic domain leads to reduction in power, area and delay
by up to 56%, 40%, and 48%, respectively as compared to
previous best results with less than 0.6% increase in error.
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Dina M. Ellaithy received the B.S. degree in
electronics and communications engineering and the
M.S. degree in electrical and electronics engineering
from Ain Shams University, Cairo, Egypt, in 2005
and 2013, respectively, where she is currently pur-
suing the Ph.D. degree in electrical and electronics
engineering.
From 2007 to 2013, she was a Teaching Assistant
with the Electronics and Communications Depart-
ment, Modern Academy for Engineering and Tech-
nology, Cairo. Since 2014, she has been a Research
Assistant with the Electronics Research Institute, Cairo. Her current research
interests include low-power circuit design, low-power arithmetic, low-power
design and implementation of 3-D graphics processors, analog integrated
circuit design, and phase-locked loop design.
Magdy A. El-Moursy was born in Cairo, Egypt,
in 1974. He received the B.S. degree (Hons.) in
electronics and communications engineering and the
masters degree in computer networks from Cairo
University, Cairo, in 1996 and 2000, respectively,
and the masters and Ph.D. degrees in electrical engi-
neering in the area of high-performance VLSI/IC
design from the University of Rochester, Rochester,
NY, USA, in 2002 and 2004, respectively.
In 2003, he joined STMicroelectronics, Advanced
System Technology, San-Diego, CA, USA. From
2004 to 2006, he was a Senior Design Engineer with Portland Technology
Development, Intel Corporation, Hillsboro, OR, USA. From 2006 to 2008, he
was an Assistant Professor with the Information Engineering and Technology
Department, German University in Cairo, Cairo. From 2008 to 2010, he was
a Technical Lead with the Mentor Hardware Emulation Division, Mentor
Graphics Corporation, Cairo, where he is currently a Staff Engineer with the
Design Creation and Synthesis Division. He is an Associate Professor with the
Microelectronics Department, Electronics Research Institute, Cairo. He has
authored over 70 papers, five book chapters, and three books in the fields
of high-speed and low-power CMOS design techniques and network-on-chip
(NoC)/system-on-chip (SoC). His current research interests include NoC/SoC,
interconnect design and related circuit level issues in high-performance
VLSI circuits, clock distribution network design, digital ASIC circuit design,
VLSI/SoC/NoC design and validation/verification, circuit verification and
testing, embedded systems, and low-power design.
Dr. El-Moursy is an Associate Editor of the Editorial Board of the
Microelectronics Journal (Elsevier), the International Journal of Circuits and
Architecture Design, and the Journal of Circuits, Systems, and Computers,
and the Technical Program Committee of many IEEE Conferences, such as
ISCAS, ICAINA, PacRim CCCSP, ISESD, SIECPC, and IDT.
9
Ghada H. Ibrahim received the B.Sc., M.Sc., and
Ph.D. degrees from the Electronics and Communi-
cations Department, Faculty of Engineering, Cairo
University, Cairo, Egypt, in 2000, 2005, and 2013,
respectively.
She was with the Bahgat Group for MPEG
Decoder Chip Design, Research and Development
Department, and then was with the Microelectronics
Department, Electronics Research Institute, Cairo,
El-Tahrir Str., -Dokki, Giza, -Egypt, where her
research interests focused on RF circuit design for
wireless sensor networks applications. She was with MIMOS BHD, Malaysia,
from 2006 to 2008, where she contributed in the establishment of an RF
Team for the design of a WIMAX RF transceiver chip. She has authored or
co-authored over 11 published papers and one pending patent. Her current
research interests include low-power digital circuits, RFIC design, printed
electronics and Micro-Electro-Mechanical Systems design, and microfabrica-
tion.
Amal Zaki is a Full Professor at Electronics
Research Institute ERI, Cairo, Egypt, Chair VLSI
Department, Electronics Research Institute, since
2011. She was the head of OBC and data handling
subsystem of satellite division at Egyptian Space
Program in National Authority for Remote Sensing
and Space Sciences. Her research interests include
digital circuit design, computer architecture, mixed
signal VLSI, and MEMS.
Abdelhalim Zekry was a Staff Member on sev-
eral rewarded universities. He also supervised over
70 master thesis and 25 doctorate. He is currently
a Professor of Electronics with the Faculty of Engi-
neering, Ain Shams University, Cairo, Egypt. He has
authored over 200 papers. His current research inter-
ests include the field of microelectronics and elec-
tronic applications, including communications and
photovoltaics.
Dr. Zekry was a recipient of several prizes for his
outstanding research and teaching performance.