TS Tutorial

Full-Scan Tutorial
Product Tutorial
The purpose of this tutorial is to familiarize you with the steps required to process a
Full-Scan design using SynTest products. You will learn how to:
Synthesize a scan chain into a non-scan design
Extract scan information from a design
Generate test vectors
To complete the full-scan run, you will perform the following steps and procedures:
Create new directories for file organization
Compile a cell library and netlist
Do testability analysis
Do full-scan selection
Do full-scan synthesis and debug
Do scan extraction
Do scan verification
Generate and translate test vectors
Fault test the design
Logic test the design
This knowledge forms the foundation for the concepts and skills you will need to integrate
the SynTest tools into your work environment.
SynTest Tutorials 1-1

Full-Scan Tutorial
Assumptions
It is assumed that:
Syntest software has been installed. Further installation and user setup information
can be found in the Quick Installation Procedure in the SynTest Users Guide,
chapter 1.
You have a basic understanding of Unix Workstation and variables.
Tutorials Directory and File Structure
The directories and files needed for the tutorials are shown in . You will be using the same
design, s27, for all three tutorials, and you will also run a full-scan test on the design with
memory.
syntest
tutorials
syntest.def
Full Partial
Scan Scan
fscan pscan
libsrc libsrc
netsrc netsrc Boundary
s27lib.v s27lib.v
Full Scan
s27.v Scan s27.v
s27.map s27.map
s27.dft ripple_rom s27.dft bscan
frun s27.psi
libsrc netsrc
netsrc prun
s27lib.v libsrc
ripple_rom.tdl s27.v
example.v
init_rom.v
ripple_rom.map example.pin brun
s27.dft
s27rom.rom example.lib
ripple_rom.pso s27.map
run_rom example.bsc
Figure 1-1 Tutorial Directory and Files Structure
1-2 SynTest Tutorials

Full-Scan Tutorial
Table 1-1 Tutorial Files and Directories
Files/Directories Function
netsrc Directory containing design.v files (Verilog structural file)
libsrc Directory containing lib.v files (Verilog source file for libraries)
*.dft File containing information that sets condition for testability analysis.
*.map Files describes relationship between generic memory cell and scannable memory cell.
*.pso File contains a list of cells to be converted to scan, and .psi file information.
*.psi File contains a list of cells to be converted to scan required for partial scan.
*.pin Pin list file used by boundary-scan.
*.lib Cell library file used by boundary-scan.
*.bsc File containing information that sets condition used by boundary-scan.
frun Script file to run a full-scan synthesis.
prun Script file to run a partial-scan synthesis.
brun Script file to run a boundary-scan synthesis.

run_rom Script file to run a full-scan synthesis for the Ripple Rom design.

Full-Scan Tutorial
The s27 Design
The schematic representation of the s27.v design is shown in Figure 1-2. Its Verilog
structural netlist and cell library are shown in Figure 1-3 and Figure 1-4 respectively.
I10
I14 I5
G10 G5
G14 D Q
G0
FD1
I11 I17
I8
CP
I6 G11 G17
G8 G17
G6
D Q
FD1
CP
I15
I9
G15
G9
I12
G1 G12
I13 I7
G13 G7
D Q
FD1
CLK CP
G2
I16
G16
G3
Figure 1-2 The s27.v Design Schematic

Full-Scan Tutorial
// File : s27.v
// Created: Fri May 24 11:43:39 1996
module s27 (G17, CLK, G0, G1, G2, G3);

output G17;
input CLK, G0, G1, G2,
G3;
wire G5, G10, G6, G11, G7;
wire G13, G14, G8, G15, G12;
wire G16, G9;
FD1 I5 (.Q(G5), .D(G10), .CP(CLK));
FD1 I6 (.Q(G6), .D(G11), .CP(CLK));
FD1 I7 (.Q(G7), .D(G13), .CP(CLK));
IV I14 (.Z(G14), .A(G0));
IV I17 (.Z(G17), .A(G11));
AN2 I8 (.Z(G8), .A(G14), .B(G6));
OR2 I15 (.Z(G15), .A(G12), .B(G8));
OR2 I16 (.Z(G16), .A(G3), .B(G8));
ND2 I9 (.Z(G9), .A(G16), .B(G15));
NR2 I10 (.Z(G10), .A(G14), .B(G11));
NR2 I11 (.Z(G11), .A(G5), .B(G9));
NR2 I12 (.Z(G12), .A(G1), .B(G7));
NR2 I13 (.Z(G13), .A(G2), .B(G12));
endmodule
Figure 1-3 Verilog Structural Netlist of s27.v Design

Full-Scan Tutorial
timescale 1ns / 10ps

module TX (Z, A, E);
output Z;
input A, E;
bufif1 (Z, A, E); (file continued)
endmodule
module IV (Z, A); module EO (Z, A, B);

output Z; output Z;
input A; input A, B;
not (Z, A); xor (Z, A, B);
endmodule endmodule
module BU (Z, A); module MUX21H (Z, A, S, B);
output Z; output Z;
input A; input A, S, B;
buf (Z, A); wire SN, NA1, NA2;
endmodule not (SN, S);
and (NA1, A, SN);
module AN2 (Z, A, B); and (NA2, B, S);
output Z; or (Z, NA1, NA2);
input A, B; endmodule
and (Z, A, B);
endmodule module FD1 (Q, QN, CP, D);
output Q, QN;
module ND2 (Z, A, B); input CP, D;
output Z; DFF I1 (.Q(Q), .D(D), .CK(CP));
input A, B; not (QN, Q);
nand (Z, A, B); endmodule
endmodule
module FD1S (Q, QN, D, TI, CP, TE);
module OR2 (Z, A, B); output Q, QN;
output Z; input D, TI, CP, TE;
input A, B; not (TEN, TE);
or (Z, A, B); and (NA1, D, TEN);
endmodule and (NA2, TI, TE);
or (Z, NA1, NA2);
module NR2 (Z, A, B); DFF I1 (.Q(Q), .D(Z), .CK(CP));
output Z; not (QN, Q);
nor (Z, A, B);
endmodule
Figure 1-4 Cell Library - s27lib.v File

Full-Scan Tutorial
Creating Directory Structure
In this section, you will create directories to be used to organize the design files. The
directories you will create are:
lib, directory used to store cell library definitions
designs, directory used to store design database information
123, directory used to store testability analysis (TurboCheck) output files (asic123)
fscan, directory used to store test pattern generation (TurboScan) results (asicgen)
dbg, directory used to store scan verification output files (scandbg)
1. Change to the syntest/ directory and source the .syntest script file . From the Shell
prompt,
a) cd $SYNTEST
b) source .syntest
Sourcing this file sets Unix variables for SynTest. The .syntest file is shown in
Figure 1-5.
setenv SYNTEST /disk1/usr/home/syntest

set path=(/usr/openwin/bin /usr/openwin/demo/xview $path)
set path=(. $SYNTEST/bin $path)
setenv LD_LIBRARY_PATH /usr/openwin/lib:/usr/lib
setenv SYNTEST_LIB_PATH $SYNTEST
setenv HELPPATH $SYNTEST/help
setenv SYNTEST_TMP .
setenv XKEYSYMDB $SYNTEST/syntest.key
setenv LM_LICENSE_FILE $SYNTEST/.float_lic.dat
Figure 1-5 The .syntest File
2. Change your current working directory to fscan/ (this directory is under $SYNTEST/
tutorial). From the syntest/ directory Shell prompt,
cd tutorials/fscan
3. Examine the design files (netlist and cell library). From the Shell prompt,
more netsrc/s27.v
You will see a Verilog structural netlist file for the s27 design as shown in Figure 1-3.
more libsrc/s27lib.v
You will see a Cell library file for the s27 design as shown in Figure 1-4.

Full-Scan Tutorial
4. Create the required directories using the mkdir command. From the Shell prompt,
mkdir lib designs 123 fscan dbg
This action will create five directories: lib, designs, 123, fscan, and dbg.
NOTE
The lib and designs directories are created for use by
Syntest applications such as expin, and are included in
the default search order.
Compiling the Design Cell Library and Netlist
In this section, you will:

Translate the Verilog structural netlist and cell library files (s27.v and s27lib.v) into
Syntest intermediate file (.sdb) using the vlogin translator
Link and expand the design using the expin program

Full-Scan Tutorial
The design netlist and cell library translating, compiling, and linking and expanding flow is
shown in Figure 1-6.
primitive.def primitive.def primitive.def

design.vhd design.v design.edif
syntest.def syntest.def edif2tdl

Step 1
Netlist
Translators vhdlin vlogin
& Complier design.tdl
syntest.def
syntest.def primitive.def
library cells.sdb
design.sdb
Step2
Netlist Linker expin
& Expander
design.x.sdb
design.c.sdb
design.conp
- Note -
The expanded design outputs are s27.c.sdb, s27.x.sdb, and s27.conp.
Figure 1-6 Compiling Process Flow
Translating and Compiling the Verilog Netlist and Library
vlogin translates and complies the Verilog .v netlist and library into SynTest intermediate
format (.sdb).
The vlogin utility reads:

Verilog files

Full-Scan Tutorial
syntest.def and primitive.def files (required files located in the $SYNTEST/designs

directory. See Creating the Syntest Database and Libraries, Chapter 3 for a
discussion of these files)
1. Convert and compile the input s27.v and s27lib.v files. From the Shell prompt,
vlogin netsrc/s27.v -opath designs -lib libsrc/s27lib.v
This action will generate the design sdb files for each module in the netlist and the cell sdb
files for each cell in the library file.
Since only one module, s27, exists in the netlist s27.v, only one module .sdb of the netlist is
created. The -opath option redirects the compiled .sdb files of the netlist to the designs sub-
directory.
For the part of the translation and compilation of the netlist, The -nf, -drc, and -opath lib
options, which are used for compiling .sdb files of the library typically, are turn-on
automatically by setting this option -lib.
The -nf and -drc options disable faulting within the library cells and run design-rule-check
separately.
The -opath option outputs the .sdb files into the lib sub-directory created for this run. Since
one .sdb file is created for each cell in the library, the directory organization eliminates
cluttering the main design directory with many files.
Detailed information regarding this translator can be found in Command Reference,

Chapter 11 and Creating the SynTest Database and Libraries, Chapter 3.
1 - 10 SynTest Tutorials
Full-Scan Tutorial
The processing messages are shown in Figure 1-7.
=================== VLOGIN V2.0.0 r01 (Tue Nov 25 14:45:57 1997) ===================
Copyright (c), 1991-1998, SynTest Technologies, Inc. All rights reserved.
TIME: Wed Dec 17 20:55:42 1997
***** Pass One *****

File: netsrc/s27.v
Parsed: s27 (interface only)
File: libsrc/s27lib.v
Parsed: TX (interface only)
Parsed: IV (interface only)
Parsed: BU (interface only)
Parsed: AN2 (interface only)
Parsed: ND2 (interface only)
Parsed: OR2 (interface only)
Parsed: NR2 (interface only)
Parsed: EO (interface only)
Parsed: MUX21H (interface only)
Parsed: FD1 (interface only)
Parsed: FD1S (interface only)
***** Pass Two ***** These messages are logged in the s27.vlog.log file
File: netsrc/s27.v
Created: designs/s27.sdb
Created: lib/TX.sdb
Created: lib/IV.sdb
Created: lib/BU.sdb
Created: lib/AN2.sdb
Created: lib/ND2.sdb
Created: lib/OR2.sdb
Created: lib/NR2.sdb
Created: lib/EO.sdb These messages are logged in the s27lib.vlog.log file
Created: lib/MUX21H.sdb
Created: lib/FD1.sdb
Created: lib/FD1S.sdb
Figure 1-7 Translator vlogin Processing Messages
The output files created are:

s27.vlogin.log, contains parsing messages in the netlist translation
s27lib.vlogin.log, contains parsing messages in the library translation
NOTE
If your library has already been compiled, you can
simply create a soft link ("ln -s <library directory> lib")
to the compiled library, and skip the library translation
and compilation step.
SynTest Tutorials 1 - 11
Full-Scan Tutorial
Linking and Expanding the Design
The design must be linked and expanded (flattened) before you can perform testability
analysis, synthesis or run the test vector generation programs.
The expin utility is used to link and expand the design. This program reads:
top-level and sub-module .sdb files
cell library .sdb files
Detailed information regarding this program can be found in Command Reference,

Chapter 11 and Creating the Syntest Database and Libraries, Chapter3.
2. Expand the design .sdb files. From the Shell prompt,
expin s27
This command execution will create three new design files in the same directory as the
specified source file, or in the directory specified with the -opath option. The files are:
s27.c.sdb, contains design linked and flattened down to the library cell level. This
file will be used by the testability synthesis application (scansyn)
s27.x.sdb, contains the design linked and flattened down to the Syntest primitive
level. This file will be used by the testability analysis application and test vectors
generation (asic123 & asicgen)
s27.conp, contains design connectivity information used to link the .c.sdb to .x.sdb
files. If missing, errors may occur.
Full-Scan Tutorial
The expansion processing messages are shown in Figure 1-8.
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Thu Jan 1 13:56:23 1998
Expanded: ./designs/s27.x.sdb
* Library Cell FD1
* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
Expanded: ./designs/s27.c.sdb
Figure 1-8 Expansion Processing Messages
Full-Scan Tutorial
Running Testability Analysis
In this section, you will use the testability analysis program, asic123 (TurobCheck), to do
the following:
Determine the controllability and observability for the design using full-scan
Generate reports detailing controllability and observability
The testability audits allow you to:

Create designs that are conducive to test pattern generation
Greatly simplify the overall test generation process
Enhance the predictability of the automated test pattern generation flow
The testability analysis flow is shown in Figure 1-9.
s27.x.sdb
s27.psi (optional, required only for partial-scan)
(optional) s27.conp
s27.dft (optional file)
asic123
s27.clk.rpt
s27.123.rpt
Figure 1-9 Testability Analysis Flow
The tool asic123 reads:

the required expanded primitive-level input file .x.sdb
the connectivity information .conp file (can be optional)
the .dft file that can contains logic value and condition settings (optional)
the .psi file if you run partial-scan. This file is used to instruct asic123 which FFs
can be used. If it is not available, asic123 will automatically determine optimum
Flip-Flops to use as scan elements
Full-Scan Tutorial
NOTE
The .dft file is SynTest template file used to set logic values at primary inputs and memory
elements for the testability analysis program to generate more accurate feedback. The
conditions set in this file can be modified to check problems in normal mode
(before synthesis), shift, hold, and capture mode.
The asic123 program searches for this file by default. This program also reads a .def file for
older releases. The .dft file is now used in place of the .def file.
See more details of a .dft file in File Reference & Examples chapter 10.
1. Observe the s27.dft file. From the shell prompt,
more s27.dft
The user-defined s27.dft is shown in Figure 1-10.
// For full-scan test pattern generation

%ATPG_CONSTRAINTS
(File continued)
{
%ATPG_MODE "FULL_SCAN" // Define a scan chain with type MDFF and name chain_1
{ %CONNECT_SCAN chain_1 MDFF
%FORCE CLK = 0; {
} %SCAN_CLOCK_1
} {
%SEQUENCE shift_seq /* The port providing shift clock */
{ %CLOCK = CLK;
%FORCE CLK = 010; %GLOBAL_CLOCK = CLK;
%CYCLE_LENGTH = 3; }
} %SCAN_INSTANCES_FILE
%SEQUENCE hold_seq {
{ %FILE_NAME = "s27.sel1.pso";
%FORCE CLK = 000; }
%CYCLE_LENGTH = 1; %SCAN_PORT
} {
%SEQUENCE capture_seq /* scan data is shifted thru these two ports */
{ %SCAN_IN = SCAN_IN;
%FORCE CLK = 010; %SCAN_OUT = SCAN_OUT;
%CYCLE_LENGTH = 1; %DEFAULT = SCAN_;
} }
%READ_MAP %SCAN_INSTRUCTION
{ {
%FILE_NAME = "s27.map"; %INSTRUCTION = instruction1;
} }
}
%INSTRUCTION instruction1
{ %SCAN_DECODER
%MODE = "scan"; {
%SHIFT = shift_seq; %CONTROL_PORT_1 = STI_TM1;
%HOLD = hold_seq; %CONTROL_PORT_2 = STI_TM2;
%CAPTURE = capture_seq; }
}
Figure 1-10 The User-defined s27.dft
Full-Scan Tutorial
2. Run testability analysis. From the Shell prompt,
asic123 s27 -o 123/s27
The -o option in asic123 redirects the output report to the 123 directory, under the prefix
name s27. The processing messages generated are saved to the report file, s27.123.rpt,
shown in Figure 1-11 to Figure 1-15.
NOTE
If you run several iterations of asic123 using different
options, you can store them using different target
filenames or subdirectories.
Detailed information regarding TurboCheck, asic123,

can be found in Using TurboCheck Testability
Analysis Tools, chapter 1.
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Thu Jan 1 13:59:23 1998
Options selected: -o 123/s27.123.rpt
CHECKING PI SHORTED WITH OTHER OBJECT OUTPUT..............................
No Rule Violation Found
CHECKING FLOATING BIDIRECTIONAL PORTS.....................................
CHECKING CONSTANT PI PORTS................................................
CHECKING FLOATING PI PORTS................................................
Figure 1-11 Testability Analysis Processing Messages - Report File
Full-Scan Tutorial
CHECKING FLOATING PO PORTS................................................
CHECKING OBJECTS WITH FLOATING INPUTS.....................................
CHECKING OBJECTS WITH FLOATING OUTPUTS....................................
CHECKING A NET IS NOT DRIVEN BY A DRIVING OBJECT..........................
CHECKING OBJECTS WITH IDENTICAL INPUTS....................................
CHECKING MERGING PARALLEL OBJECTS.........................................
CHECKING BUSSES WITH NON TRISTATE GATE OR BIDI............................
CHECKING BUS HOLDER.......................................................
CHECKING CROSS-COUPLED NAND/NOR GATES.....................................
CHECKING INACCESSIBLE MEMORY OBJECTS......................................
Figure 1-12 Testability Analysis Processing Messages - Report File (continued)
Full-Scan Tutorial
CHECKING COMBINATIONAL LOOPS AND POTENTIAL COMBINATIONAL LOOPS............
Clock net driving information is saved in 123/s27.clk.rpt.
CHECKING PULSE GENERATORS.................................................
CHECKING HARD-TO-DETECT NODES.............................................
CHECKING SEQUENTIAL/COMBINATIONAL GATED CLOCK.............................
CHECKING GENERATED CLOCKS.................................................
CHECKING CLOCK PINS CONNECT TO PO OR DFF/LATS D PIN......................
CHECKING ASYNCHRONOUS SET/RESET...........................................
CHECKING POTENTIAL BUS CONTENTION.........................................
CHECKING FLOATING BUSSES..................................................
**** CIRCUIT STATISTICS ****
Number of input pins .............. = 5

Number of output pins ............. = 1
Full-Scan Tutorial
Number of bidirectional pins ...... = 0

Number of accessible objects ...... = 19
Number of accessible nets ......... = 21
Number of delay objects ........... = 0
Number of inserted delay objects .. = 0
Number of accessible flip-flops ... = 3
Number of accessible latches ...... = 0
Number of accessible RAMs/ROMs .... = 0
Total accessible memory elements .. = 3
Number of inaccessible flip-flops . = 0

Number of inaccessible latches .... = 0
Number of inaccessible RAMs/ROMs .. = 0
Total inaccessible memory elements = 0
**** TESTABILITY ANALYSIS SUMMARY ****
Logic levels .............................. = 5

Cell elements ............................. = 13
Tri-state gates and NMOS/PMOS transistors . = 0
Missing tri-state bi-directional ports .... = 0

Constant primary input ports .............. = 0
Floating primary input ports .............. = 0
Floating primary output ports ............. = 0
Objects with floating inputs .............. = 0
Objects with floating outputs ............. = 0
Floating nets ............................. = 0
Busses with non tri-state inputs .......... = 0
Combinational feedback loops .............. = 0
Potentially combinational feedback loops .. = 0
Pulse generators .......................... = 0
Sequentially gated clocks ................. = 0
Combinationally gated clocks .............. = 0
Generated clocks .......................... = 0
Clock pins to D or PO ..................... = 0
Asynchronous set/reset .................... = 0
Floating busses ........................... = 0
Potential bus contention .................. = 0
Combinational gates with identical inputs . = 0
Cross-coupled NAND/NORs ................... = 0
Bus holders ............................... = 0
Merging parallel objects .................. = 0
Full-Scan Tutorial

Floating nets ............................. = 0
Floating busses ........................... = 0
Bus holders ............................... = 0
**** SYNTEST TESTABILITY REPORT ****
MAXIMUM COUNT AVERAGE COUNT

VALUE MAX VAL VALUE UNTESTABLE
---------- ------- ---------- ----------
0-CONTROLLABILITY (C0) 206 1 35 0
OBSERVABILITY (OBV) 306 1 148 0
MEAN - - 68 -
STANDARD DEVIATION - - 49 -
CPU TIME = 0:00:01

Entries in this column should be given
serious consideration. They indicated
END TIME : Thu Jan 1 13:59:28 1998 potentially impossible detects during test.
Figure 1-15 Testability Analysis Processing Messages - Report File (end)
The files generated by Asic123 at the directory 123/ are:

s27.123.rpt, file containing processing messages and a testability analysis report
s27.clk.rpt, clock tree information report file
Full-Scan Tutorial
The s27.clk.rpt is shown in Figure 1-16.
**** Order: Type Clock_Polarity Root_Clock -> Local_Clock Object ****

1) DFF P CLK -> CLK I5
Figure 1-16 The Clock Report s27.clk.rpt
Full-Scan Tutorial
Running Scan Selection
Before synthesizing scan into your design, you must select scan elements and list them in a
file. This file, created by scansel, determines the scan order for scan chains. The scan
selection flow is shown in Figure 1-17.
s27.x.sdb
(optional, required only
s27.psi for partial-scan)
scansel
s27.sel1.pso
Figure 1-17 Scan Selection Flow
The scansel program reads:

an expanded cell level .c.sdb file
an expanded primitive level .x.sdb file
a .psi file if running partial-scan
1. Run scan selection. From the Shell prompt,
scansel -fscan s27
The processing messages are shown in Figure 1-18 and Figure 1-19.
Full-Scan Tutorial
=================== SCANSEL V2.0.0 r01 (12/22/97 17:06:40) ===================
TIME: Thu Jan 1 14:18:43 1998
Options selected:
-level 2: effort level is 2.
-acyclic: Break Self & Global Loops.
-fscan: Do Full-Scan Scan Selection.
-o s27: report file will be saved to s27.sel.rpt.
Process s27 ...

Start scan element selection ...
START TIME = Thu Jan 1 14:18:44 1998
Read in and check circuit at TIME Thu Jan 1 14:18:44 1998


End circuit check at TIME Thu Jan 1 14:18:47 1998
CPU TIME = 0:00:02
Max Sequential Depth = 0

Scan Count = 3
Memory Count = 3
3 out of 3 memory elements are scannable
Figure 1-18 scansel Processing Messages - s27.sel.rpt
Full-Scan Tutorial
END TIME = Thu Jan 1 14:18:47 1998
CPU TIME = 0:00:02
Figure 1-19 scansel Processing Messages - s27.sel.rpt (continued)
The output files generated by scansel are:

s27.sel1.pso, file produced by the -fscan option containing a list of flip-flops from
the design (with netlist default order)
s27.sel.rpt, file recording processing message and a report
NOTE
The default ordering of scan elements is organized by
the hierarchical order of module in your design.You can
rearrange the order by copying the .pso file to a different
name, then reorder the flip-flops in the appropriate
ordering. This is usually sufficient for most purposes.
The s27.sel1.pso is shown in Figure 1-20.
MUST_SCAN I5;
MUST_SCAN I6;
MUST_SCAN I7;
Figure 1-20 s27.sel1.pso File
Running Scan Synthesis and Debug
The purpose of scan synthesis is to replace non-scan flip flop with scan flip flop.
In this section you will perform the following:

Synthesize the design to include scan
Scan debugging
Full-Scan Tutorial
The scan synthesis program, scansyn, reads:

a .pso, scan element list file created by scansel or by the designers
a .dft file containing design specific information (see Figure 1-10, this file can be
modified)
a .map file containing mapping information between generic and scannable memory
cells. The s27.map is shown in Figure 1-21.
%MAP_SCAN MDFF /* Mapping for chain type == MDFF */

{
/* Replace all FD1 scan instance with FD1S */
%MAP_CELL FD1 => FD1S
{
%SCAN_PORT %SYSTEM_IN => D;
%SCAN_PORT %SCAN_IN => TI;
%SCAN_PORT %SCAN_OUT => Q;
%SCAN_SELECT_1 %SELECT => TE;
%SCAN_CLOCK_1 %CLOCK => CP;
}
}
%REPAIR_CELL
{
%CELL BUF BU;
%CELL INV IV;
%CELL AND AN2;
%CELL NAND ND2;
%CELL OR OR2;
%CELL NOR NR2;
%CELL XOR EO;
%CELL TBUF TX
{
%ENABLE = E;
}
%CELL MUX MUX21H
{
%DATA_0 = A;
%DATA_1 = B;
%SELECT = S;
}
}
Figure 1-21 The s27.map File
Synthesizing the Design
1. Run scan synthesis. From the Shell prompt,
scansyn -fscan s27
Full-Scan Tutorial
The processing messages (or the s27.syn.rpt report file) are shown in Figure 1-22.
Scansyn replaces the memory elements with scan elements and inserts the scan-decoder in
the netlist first, then enables the utilities vlogin and expin to modify the .sdb, and created the
relevant data and files. In the end, scansyn system-calls the option -extract-only
automatically to self-test if the scan-chain(s) is stitched successfully. The referenced
detailed process is in Figure 1-22 to Figure 1-25. All the data of the modified scan design is
named as s27_s0.*.
The scansyn program generates:

report and log files (s27.syn.rpt, s27.syn.log). Actually, s27.syn.log contains three
log files: scan_decoder.vlogin.log, s27_s0.expin.log, and s27_s0.syn.rpt.
scansyn_lib sub-directory containing a new version of the design files (s27_s0.*)
that can be translated to VHDL, Edif, and Verilog format using the lsdb translator.
s27_s0.dft, the modified .dft file for running scandbg, asicgen, and tpout to
generate test vectors for the scan design.
s27_s0.syn1.pso and s27_s0.ext1.pso, which are generated by scansyn and scansyn
-extract_only (automatically) separately, containing a list of the scan flip-flops.
Full-Scan Tutorial
=================== SCANSYN V2.0.0 r01 (12/24/97 17:34:29) ===================
TIME: Thu Jan 1 15:03:41 1998
Options selected: -fscan -o s27.syn.rpt
- Reading top level netlist ./designs/s27.sdb ...
- Reading expanded netlist ./designs/s27.x.sdb ...
- Reading cell-level netlist ./designs/s27.c.sdb ...
- Setting up hierarchical information ...

- Init forced value simulation data structure ...
- Create directory ./scansyn_lib.

- Replace 3 memory elements to scan elements.
- Insert 0 delay cells.
- Start building scan synthesis table ...
- Start Hierarchical Repair Process ...
- Copy ./designs/s27.sdb => ./scansyn_lib/s27_s0.sdb.
- Start Building Scan Decoder ...
- Start executing synthesis commands ...
- Please read s27.syn.log for messages.
- Executing commands in ./scansyn_lib/s27_s0.cmd ...
- Generating new cell level pso file s27_s0.syn1.pso ...
- Generating new dft file s27_s0.dft...

- In %SEQUENCE shift_seq, Add %FORCE STI_TM1 = 111;
=============================================
Object Error Status after Hierarchical Repair
=============================================
- No error found after repair.
Figure 1-22 scansyn Processing Messages (s27.syn.rpt File)
Full-Scan Tutorial
- Expanding synthesized design s27_s0.sdb ...
- Extract scan chain from s27_s0 ...

please refer to s27_s0.syn.rpt.
======================================================
Report
======================================================
Circuit Name : s27

New Circuit Name : s27_s0
Scan Decoder Cell : SCAN_DECODER_CLASS
Scan In Port Name : Chain 1 -> SCAN_IN
Scan Out Port Name : Chain 1 -> SCAN_OUT
Added Control Port : STI_TM1
Synthesis Status
------------------------------------------
Replaced Memory Cells : 3
Inserted Delay Cells : 0
DRC Error Status

------------------------------------
Set Error
Found : 0
Fixed : 0
Skiped : 0
Reset Error
Found : 0
Fixed : 0
Skiped : 0
Shift Clock Error

Found : 0
Fixed : 0
Skiped : 0
Capture Clock Error

Found : 0
Fixed : 0
Skiped : 0
Figure 1-23 scansyn Processing Messages (s27.syn.rpt File) (continued)
Full-Scan Tutorial
Transparent Error
Found : 0
Fixed : 0
Skiped : 0
Bidi Error
Found : 0
Fixed : 0
Skiped : 0
Bus Error
Found : 0
Fixed : 0
Skiped : 0
Cross Coupled Error

Found : 0
Fixed : 0
Skiped : 0
RAM Error
Found : 0
Fixed : 0
Skiped : 0
Tri-State Pad Error

Found : 0
Fixed : 0
Skiped : 0
Scan Decoder Loading Information

----------------------------------------------
SCANSYN_SCAN uses BUF(BU) to drive 3 gates.
Scan Decoder Control Table

------------------------------------------
Sequence | STI_TM1
-----------+------------------------------
Normal | 0
Shift | 1
Hold | X
Capture | X
------------------------------------------
Figure 1-24 scansyn Processing Messages (s27.syn.rpt File) (continued)
Full-Scan Tutorial
Report File : s27.syn.rpt

Log File : s27.syn.log
======================================================
CPU TIME = 0:00:13
END TIME : Thu Jan 1 15:04:00 1998
Figure 1-25 scansyn Processing Messages (s27.syn.rpt File) (end)
The s27.syn.log file is shown in Figure 1-26 and Figure 1-27.
Full-Scan Tutorial
--- vlogin ./scansyn_lib/scan_decoder ----

ld.so: warning: /usr/lib/libc.so.1.8 has older revision than expected 9
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Thu Jan 1 15:03:46 1998
***** Pass One *****

File: ./scansyn_lib/scan_decoder.v
Parsed: SCAN_DECODER_CLASS (interface only)
***** Pass Two *****
Created: ./scansyn_lib/SCAN_DECODER_CLASS.sdb
--- Modification Information ---
--- run ./scansyn_lib/s27_s0.cmd ----

--- /home/users/barbara/syntest/bin/expin s27_s0.sdb ----
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Thu Jan 1 15:03:54 1998

Expanded: SCAN_DECODER_CLASS
Expanded: ./scansyn_lib/s27_s0.x.sdb
* Library Cell FD1S

* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
* Library Cell BU
Expanded: ./scansyn_lib/s27_s0.c.sdb
--- verify by extraction ---
=================== SCANSYN V2.0.0 r01 (12/24/97 17:34:29) ===================
TIME: Thu Jan 1 15:03:58 1998
Figure 1-26 The s27.syn.log file
Full-Scan Tutorial
Options selected: -fscan -extract_only -o s27_s0.syn.rpt
- Reading top level netlist ./scansyn_lib/s27_s0.sdb ...
- Reading expanded netlist ./scansyn_lib/s27_s0.x.sdb ...

---==========--- Scan Extraction ---==========---

Attention: All object names appeared in message are in .x level
and the object number are resorted for simulation.
------=======================================================------
Initializing ...
- Extracting Scan Chain 1 ...

Successfully!
************** Extraction report **************
Chain 1: extracted successfully!!

%CHAIN_SO specified in the dft is SCAN_OUT.
%FOUND_SO is SCAN_OUT.
3 scan cells were written into file s27_s0.ext1.pso.
************ End Scan Extraction Session ************
- Scan DELAY & CROSS-COUPLE ...

- Saving debug data ...
CPU TIME = 0:00:01
END TIME : Thu Jan 1 15:04:00 1998
Figure 1-27 The s27.syn.log file (continued)
Beside replacing non-scan flip-flops and Latches in the design with their scannable
counterparts, scansyn also does rule checks and makes necessary changes to the design.
Running Scan Debug
2. Run scan debug to check if the scan chain(s) works by inserting some flush test vectors.
Full-Scan Tutorial
From the Shell prompt to verify,
a) scandbg -flush_test 10110 s27_s0 -o dbg/s27_s0.1
b) scandbg -flush_test 01001 s27_s0 -o dbg/s27_s0.2
The outputs report files created under the sub-directory dbg/ are shown in Figure 1-28 and
Figure 1-29.
Full-Scan Tutorial
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Thu Jan 1 15:13:17 1998
Options selected: -flush_test 10110 -o dbg/s27_s0.1.dbg.rpt
(File continued)
**** CIRCUIT STATISTICS **** *FLUSH PATTERN TEST:

Number of output pins ............. = 2 simulation 1 : cycle 1 : =>
Number of bidirectional pins ...... = 0 success!!
Number of accessible nets ......... = 44 simulation 4 : cycle 2 : =>
Number of delay objects ........... = 0 success!!
Number of accessible latches ...... = 0 simulation 7 : cycle 3 : =>
Number of accessible flip-flops ... = 3 success!!
Total accessible memory elements .. = 3 simulation 10 : cycle 4 : =>
success!!
Number of inaccessible flip-flops . = 0 simulation 13 : cycle 5 : =>
Number of inaccessible RAMs/ROMs .. = 0 success!!
simulation 16 : cycle 6 : =>
chain - chain_1 OK.
LEVELIZATION CPU TIME = 0:00:02 generating chain_1.dbg.pso file ....
success!!
LEVELIZATION END TIME : Thu Jan 1 15:13:22 1998
Simulation Complete!!
Scan-Chain 1 - chain_1:
SCAN_IN : SCAN_IN ---------------------------- CHAIN STATUS ------------------------------
SCAN_OUT : SCAN_OUT
CLOCK : CLK [NAME] [STATUS] [PSO-FILE] [INV]
SHIFT :
FORCE : CLK ---> 010 chain_1 CHAIN_OK chain_1.dbg.pso N
FORCE : STI_TM1 ---> 111
INSTANCES : 3 ---> 3 scan objects
CPU TIME = 0:00:02
END TIME : Thu Jan 1 15:13:23 1998
Figure 1-28 s27_s0.1.dbg.rpt
Full-Scan Tutorial
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Thu Jan 1 15:19:08 1998
**** CIRCUIT STATISTICS **** (File continued)

success!!
Number of inaccessible RAMs/ROMs .. = 0 success!!
chain - chain_1 OK.
LEVELIZATION CPU TIME = 0:00:02 generating chain_1.dbg.pso file ....
success!!
SCAN_IN : SCAN_IN ---------------------------- CHAIN STATUS ------------------------------
SCAN_OUT : SCAN_OUT
CLOCK : CLK [NAME] [STATUS] [PSO-FILE] [INV]
SHIFT :
FORCE : CLK ---> 010 chain_1 CHAIN_OK chain_1.dbg.pso N
CPU TIME = 0:00:02
*FLUSH PATTERN TEST: END TIME : Thu Jan 1 15:19:14 1998
Full-Scan Tutorial
Figure 1-30 illustrates the s27 design flow during design synthesis, debug, and netlist
conversion processes.
s27.x.sdb
s27.dft
s27.c.sdb
s27.map
s27.sel1.pso
scansyn Synthesize
scansyn_lib
s27_s0.x.sdb
s27_s0.c.sdb
s27.syn.rpt
s27_s0.sdb
s27.syn.log
s27_s0.conp
s27_s0.syn.rpt
s27_s0.cmd
s27_s0.syn1.pso
SCAN_DECODER_CLASS.sdb
scan_decoder.v
Debug scandbg
lsdb Netlist
Conversion
s27_s0.dbg.rpt
s27_s0.vhd
s27_s0.v
s27_s0.edif
Figure 1-30 Scan Synthesis Flow
Full-Scan Tutorial
Creating a Verilog Netlist
If you may need a Verilog netlist of the synthesized version of the design, you will need to
use the lsdb utility to translate the sdb files created by scansyn (s27_s0.x.sdb).
1. Convert the s27 scannable SynTest database to a Verilog netlist. From the Shell prompt,
lsdb s27_s0 -verilog -hierarchy -timescale -o s27_s0.v
The -verilog option creates a Verilog netlist (-vhdl, -edif and -tdl are also supported).
The -hierarchy option creates a hierarchical netlist which will reconstruct the original
design hierarchy.
The -timescale option allows insertion of a timescale directive in Verilog for simulation
purposes.
The -o option directs the output to the filename you specify.
=================== LSDB V2.0.0 r01 (12/23/97 09:14:37) ===================
TIME: Thu Jan 1 15:24:37 1998
Netlist output is saved in s27_s0.v.
Figure 1-31 The lsdb Processing Messages
2. Display the s27_s0.v file. From the Shell prompt,
more s27_s0.v
The Verilog netlist is shown in Figure 1-32.
Full-Scan Tutorial
// File : s27_s0.v
// Created: Thu Jan 1 15:23:16 1998
// By : lsdb version V2.1.0 of 12/23/97 09:14:47
// lsdb -verilog s27_s0
// sdb verison 230
//
// (c) 1991-1998, SynTest Technologies, Inc.

module s27_s0 ( G17 , SCAN_OUT , G0 , G1 ,
G2 , G3 , SCAN_IN , CLK ,
STI_TM1 ) ;
output G17 , SCAN_OUT ;
input G0 , G1 , G2 , G3 ,
SCAN_IN , CLK , STI_TM1 ;
wire G10 , G11 , G12 , G5 ,
G13 , G6 , G14 , G7 ,
G15 , G8 , G9 , G16 ;
FD1S I5 ( .CP ( CLK ) , .D ( G10 ) , .Q ( G5 ) ,
.TE ( I5_TE ) , .TI ( SCAN_IN ) ) ;
FD1S I6 ( .CP ( CLK ) , .D ( G11 ) , .Q ( G6 ) ,
.TE ( I5_TE ) , .TI ( G5 ) ) ;
FD1S I7 ( .CP ( CLK ) , .D ( G13 ) , .Q ( G7 ) ,
.TE ( I5_TE ) , .TI ( G6 ) ) ;
IV I14 ( .A ( G0 ) , .Z ( G14 ) ) ;
IV I17 ( .A ( G11 ) , .Z ( G17 ) ) ;
AN2 I8 ( .A ( G14 ) , .B ( G6 ) , .Z ( G8 ) ) ;
OR2 I15 ( .A ( G12 ) , .B ( G8 ) , .Z ( G15 ) ) ;
OR2 I16 ( .A ( G3 ) , .B ( G8 ) , .Z ( G16 ) ) ;
ND2 I9 ( .A ( G16 ) , .B ( G15 ) , .Z ( G9 ) ) ;
NR2 I10 ( .A ( G14 ) , .B ( G11 ) , .Z ( G10 ) ) ;
NR2 I11 ( .A ( G5 ) , .B ( G9 ) , .Z ( G11 ) ) ;
NR2 I12 ( .A ( G1 ) , .B ( G7 ) , .Z ( G12 ) ) ;
NR2 I13 ( .A ( G2 ) , .B ( G12 ) , .Z ( G13 ) ) ;
SCAN_DECODER_CLASS SCAN_DECODER ( .CTRL1 ( STI_TM1 ) , .SCANSYN_SCAN ( I5_TE ) ) ;
BU SCANSYN_BUF_0 ( .A ( G7 ) , .Z ( SCAN_OUT ) ) ;
endmodule
// File : s27_s0.v
// Created: Thu Jan 1 15:23:16 1998
// sdb verison 230
//
module SCAN_DECODER_CLASS ( SCANSYN_SCAN , CTRL1 ) ;

output SCANSYN_SCAN ;
input CTRL1 ;
BU C1 ( .A ( CTRL1 ) , .Z ( SCANSYN_SCAN ) ) ;
endmodule
Figure 1-32 The converted Verilog File - s27_s0.v
Full-Scan Tutorial
Generating and Translating Test Patterns
After your design is synthesized to include scan, you can then generate and translate test
patterns. In this section, you will :
Use the test pattern generation utility, asicgen (TurboScan tool), to generate the test
patterns for the s27 design
Use the Unix ln command to create an internal link
Use the test pattern translation utility, tpout, to translate the test patterns into a
Verilog test-bench
Generating the Test Pattern
The asicgen utility reads the synthesized output files from the scansyn utility, they are:
s27_s0.x.sdb file, the design compiled and flattened to the SynTest primitive level
s27_s0.dft, file contains an entry regarding "%ATPG_CONSTRAINTS" which
outlines any logic pre-conditioning for the design to run in hold mode
Figure 1-33 shows the full-scan ATPG flow.
s27_s0.x.sdb
s27_s0.dft
asicgen
s27_s0.rpt
s27_s0.tp
s27_s0.int
s27_s0.hdt
s27_s0.pso
s27_s0.red
s27_s0.udt
Figure 1-33 Test Pattern Generation Flow
Full-Scan Tutorial
The s27_s0.dft file is shown in Figure 1-34.
// File : ./s27_s0.dft
( File continued)
// Connect Scan Chain
// Scan instruction sequence before scan, during scan, and %CONNECT_SCAN chain_1 MDFF
after scan {
%SEQUENCE shift_seq %SCAN_PORT
{ {
%FORCE CLK = 010; %SCAN_IN = SCAN_IN;
%FORCE STI_TM1 = 111; %SCAN_OUT = SCAN_OUT;
} }
%SEQUENCE hold_seq %SCAN_CLOCK_1
{ {
%FORCE CLK = 000; %CLOCK = CLK;
%FORCE STI_TM1 = 000; %GLOBAL_CLOCK = CLK;
%SEQUENCE capture_seq {
{ %FILE_NAME = "s27_s0.ext1.pso";
%FORCE CLK = 010; }
%FORCE STI_TM1 = 000; %SCAN_INSTRUCTION
%CYCLE_LENGTH = 1; {
} %INSTRUCTION = instruction1;
// Instruction }
%INSTRUCTION instruction1 }
{ // Test Generation Constraints
%MODE = "scan"; %ATPG_CONSTRAINTS
%SHIFT = shift_seq; {
%HOLD = hold_seq; %ATPG_MODE "FULL_SCAN"
%CAPTURE = capture_seq; {
} %FORCE CLK = 0;
// Read Mapping_cell File }
%READ_MAP }
{ // Scan Decoder
%FILE_NAME = "s27.map"; %SCAN_DECODER
} {
// Connect Scan Chain %CONTROL_PORT_1 = STI_TM1;
%CONTROL_PORT_2 = STI_TM2;
}
Figure 1-34 The s27_s0.dft File
1. Generate the test patterns. From the Shell prompt,
asicgen -post_fscan s27_s0 -o fscan/s27_s0
The -post_fscan option sets all the default options, such like -dont_scan_loop, for full-
scan test pattern generation on the synthesized netlist.
The -o option redirects the output to the fscan subdirectory.
Full-Scan Tutorial
The asicgen processing messages are shown in Figure 1-35, Figure 1-36, and Figure 1-37.
=================== ASICGEN V2.0.0 r01 (02/17/98 19:06:10) ===================
TIME: Tue Feb 17 19:22:04 1998
Options selected: -post_fscan -fscan -atpg -verbose 2 -limit 10000

-dont_scan_loop -must_scan_only -o fscan/s27_s0.rpt
Read constraints from s27_s0.dft.....

Force CLK Pattern=0
Read scan specifications from s27_s0.dft.....
Automatic selected option: -compact 0.
Automatic selected option: -weighted 2.


LEVELIZATION CPU TIME = 0:00:02

LEVELIZATION END TIME : Tue Feb 17 19:22:09 1998
Creating capture mode information...

62 collapsed and 112 uncollapsed faults
Generating objects for capture(propagate) mode...
Reading stimulus input file s27_s0.stm ...
fsim: Simulation packets [ 1] ( 8 pattern) ... detected faults 62
62 Hard detected faults are saved in fscan/s27_s0.hdt.
The circuit s27_s0.x.sdb has 7 inputs, 3 scan objects, and 2 outputs.
This circuit has 8 test patterns and contains 62 faults of which

62 (100.00%) faults were Hard detected (HD).
0 ( 0.00%) data faults were Potentially testable (PT).
0 ( 0.00%) clock/enable faults were Potentially untestable (PU).
Figure 1-35 asicgen Processing Messages - s27_s0.rpt
Full-Scan Tutorial
0( 0.00%) Untestable (UT) faults were Ignored (IG) or Tied to VCC/GND.

0( 0.00%) Untestable (UT) faults were Uncontrollable.
0( 0.00%) Untestable (UT) faults were Blocked (Unobservable).
0( 0.00%) Untestable (UT) faults were due to circuit design.
0( 0.00%) faults were Undetected (UD).
fsim pessimistic fault coverage = HD/(Total-IG) = 100.0000 %.

fsim pessimistic test coverage = HD/(Total-UT) = 100.0000 %.
fsim pessimistic test efficiency = (HD+UT)/Total = 100.0000 %.
fsim optimistic fault coverage = (HD+PT)/(Total-IG) = 100.0000 %.

fsim optimistic test coverage = (HD+PT)/(Total-UT-PU) = 100.0000 %.
fsim optimistic test efficiency = (Total-UD)/Total = 100.0000 %.
This circuit has 8 test patterns and contains 112 UNCOLLAPSED faults of which
0 ( 0.00%) Untestable (UT) faults were Ignored (IG) or Tied to VCC/GND.
0 ( 0.00%) Untestable (UT) faults were Uncontrollable.
0 ( 0.00%) Untestable (UT) faults were Blocked (Unobservable).
0 ( 0.00%) Untestable (UT) faults were due to circuit design.
0 ( 0.00%) faults were Undetected (UD).


Before Pass 0: CPU TIME = 0:00:02

0 ( 0.00%) clock/enable faults were Aborted for backtrack count exceeding 10000.
0 ( 0.00%) data faults were Aborted for backtrack count exceeding 10000.
atpg pessimistic fault coverage = HD/(Total-IG) = 100.0000 %.

atpg pessimistic test coverage = HD/(Total-UT) = 100.0000 %.
atpg pessimistic test efficiency = (HD+UT)/Total = 100.0000 %.
atpg optimistic fault coverage = (HD+PT)/(Total-IG) = 100.0000 %.

atpg optimistic test coverage = (HD+PT)/(Total-UT-PU) = 100.0000 %.
Figure 1-36 asicgen Processing Messages - s27_s0.rpt (continued)
Full-Scan Tutorial
atpg optimistic test efficiency = (Total-Abort)/Total = 100.0000 %.


CPU TIME = 0:00:02
END TIME : Tue Feb 17 19:22:13 1998
The output files generated by asicgen include:

s27_s0.rpt, fault coverage report file
s27_s0.tp, test pattern file
s27_s0.hdt, hard-detected faults
s27_s0.red, redundant or untestable faults file
s27_s0.udt, undetected faults file
s27_s0.int, top module pin interface file
s27_s0.pso, scan elements list file
Full-Scan Tutorial
The test pattern file is shown in Figure 1-38.
S
SS C
TC AIII
IA N567
_N ____
C T_ GOPPP
LGGGGMIIII1UPPP
K01231N5677TOOO
-STEM-
1 S LHLHHLHLLL---+-
2 S LLLLLLHHHL+----
3 S LLHHLHLLHL----+
4 S LHHLHLHLHH+++-+
5 S LLLLHLLHHH++--+
6 S LLHLLLHLLL+---+
7 S LHLHLHHLLL+-+--
8 S LLHHLLLHLL+----
Figure 1-38 The s27_s0.tp File
The s27_s0.hdt, s27_s0.int, and s27_s0.pso files are shown in Figure 1-39.
(file continued)
/0 /1 CP I6 I CLK
/0 /1 CP I7 I G0
/0 /1 CP I5 /1 Z I15 I G1
/0 /1 CLK /0 /1 SCAN_IN I G2
/0 B I10 /0 /1 STI_TM1 I G3
/0 /1 D I6 /0 /1 Q I5 I STI_TM1
/0 /1 Z I17 /0 /1 Z I SCAN_IN
/0 A I11 SCANSYN_BUF_0 S I5 I1
/0 B I13 /0 /1 G3 S I6 I1
/0 B I16 /0 /1 G0 S I7 I1
/0 B I15 /0 /1 G1 O G17
/0 A I15 /0 /1 G2 O SCAN_OUT
/1 A I8 /0 /1 TE I5
/0 /1 Z I8 /0 Z I16
/0 /1 TI I6 /0 /1 TE I6 The s27_s0.int File
/0 /1 TI I7 /0 /1 Q I7
/0 /1 Z I10 /0 /1 TE I7 MUST_SCAN 24 I5;
/0 Z I9 /1 Z I12 MUST_SCAN 44 I6;
/0 B I12 /1 Z I11 MUST_SCAN 64 I7;
/0 A I10 /1 Z I13
/1 B I8
The s27_s0.hdt File The s27_s0.pso File
Figure 1-39 The s27_s0.hdt , s27_s0.int, and s27_s0.pso Files
Running a Logic Simulation
In this section, you will run a logic simulation to verify the logic using the test vectors,
s27_s0.tp, generated by asicgen. You will again use asicgen to run the logic simulation.
Full-Scan Tutorial
This utility requires a test pattern with a .stm file. This file can be a user defined or can be a
copy of .tp file. For this simulation, you will make a copy from the s27_s0.tp file.
2. Copy the s27_s0.tp to s27_s0.stm. From the Shell prompt,
cp s27_s0.tp s27_s0.stm
3. Run logic simulation. From the Shell prompt,
asicgen s27_s0 -lsim -fscan
=================== ASICGEN V2.0.0 r01 (12/24/97 15:52:33) ===================
TIME: Sun Feb 8 15:12:11 1998
Options selected: -fscan -lsim -verbose 2 -o lsim/s27_s0.rpt

Force CLK Pattern=0



LEVELIZATION END TIME : Sun Feb 8 15:12:14 1998

Running on stitw5.
lsim: Test pattern [ 1] ...
*Finish Logic Simulation on stitw5.
CPU TIME = 0:00:02
Figure 1-40 Logic Simulation Processing Messages
Full-Scan Tutorial
Running a Fault Simulation
Now you can use the test vector to run the fault simulation using asicgen with -fsim option.
Asicgen requires a test pattern with a .stm file. This file can be a user defined or can be a
copy of .tp file.
4. Run a fault simulation. From the Shell prompt,
asicgen s27_s0 -fsim -fscan
Full-Scan Tutorial
The processing messages are shown in Figure 1-41 to Figure 1-42.
=================== ASICGEN V2.0.0 r01 (12/24/97 15:52:33) ===================
TIME: Sun Feb 8 15:08:43 1998
Options selected: -fscan -fsim -verbose 2 -o fsim/s27_s0.rpt

Force CLK Pattern=0




62 Hard detected faults are saved in fsim/s27_s0.hdt.

Figure 1-41 Fault Simulation Processing Messages (partial)
Full-Scan Tutorial
0( 0.00%) Untestable (UT) faults were Ignored (IG) or Tied to VCC/GND.

0( 0.00%) Untestable (UT) faults were Uncontrollable.
0( 0.00%) Untestable (UT) faults were Blocked (Unobservable).
0( 0.00%) Untestable (UT) faults were due to circuit design.
0( 0.00%) faults were Undetected (UD).




CPU TIME = 0:00:02
END TIME : Sun Feb 8 15:08:48 1998
Figure 1-42 Fault Simulation Processing Messages (continued)
Full-Scan Tutorial
Translating the Test Pattern
The test pattern files created by asicgen are stored in the fscan sub-directory. Before
translating these files, you must create internal links to these files.
1. Create links to the test pattern files. From the Shell prompt,
a) ln -s fscan/s27_s0.tp .
b) ln -s fscan/s27_s0.int .
2. Translate the test pattern to a Verilog serial format. From the Shell prompt,
tpout -vlog -fscan s27_s0
The -vlog option translates to a Verilog serial test-bench format.

The -fscan option specifies translation of full-scan vectors.
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 19:25:46 1998

Shift sequence
OPTIONS : -vlog -fscan CLK = 010
STI_TM1 = 1
- Processing interface file s27_s0.int ...
Hold sequence
Number of input pins = 7 CLK = 0
Number of bidi pins =0
Number of output pins = 2 Capture sequence
Number of scan instances = 3 CLK = 010
- Processing DFT file s27_s0.dft ... Clock information :
Scan information : CLK (P) = 010
Chain 1, Length is 3 - Processing test vector file s27_s0.tp ...

Scan-in pin = SCAN_IN
Scan-out pin = SCAN_OUT Number of vectors = 8
Length of a vector = 15
Sequence information :
- Translating patterns and generating driver file ...
Verilog vectors were saved in s27_s0.vector.

(File continued) Verilog driver was saved in s27_s0.drv.v.
Figure 1-43 tpout Processing Messages - s27_s0.tpout.rpt File
Full-Scan Tutorial
Test pattern translation produces five output files:

a report file, s27_s0.tpout.rpt file
a Verilog timing driver file, s27_s0.drv.v
a Verilog pattern file, s27_s0.vector
The Verilog driver file, s27_s0.drv.v, controls a Verilog simulation of the full set of patterns
generated by asicgen. It reads the scan test data and compares the expected data both from
s27_s0.vector file. This verification process in Verilog can be used to completely verify the
pattern set before taping out the design. The s27_s0.drv.v is shown in Figure 1-44, Figure 1-
45, and Figure 1-46.
Full-Scan Tutorial
// FILE : SynTest Verilog driver file (file continued)

// NAME : s27_s0.drv.v
// TIME : Thu Jan 1 15:44:57 1998 //-------------------------------------------------------
// OPTIONS : -vlog -fscan //-- Call module --
//-------------------------------------------------------
timescale 1ns / 10ps s27_s0 s27_s0_inst (
.G17 ( STI_G17 ) ,
define TRUE 1 .SCAN_OUT ( STI_SCAN_OUT ) ,
define FALSE 0 .CLK ( STI_CLK ) ,
.G0 ( STI_G0 ) ,
module s27_s0_top ; .G1 ( STI_G1 ) ,
//------------------------------------------------------- .G2 ( STI_G2 ) ,
//-- Declare parameters -- .G3 ( STI_G3 ) ,
//------------------------------------------------------- .STI_TM1 ( STI_STI_TM1 ) ,
parameter .SCAN_IN ( STI_SCAN_IN ) );
SHIFT_PHASE = 3, //-------------------------------------------------------
SHIFT_CYCLE = 3, //-- Init variables --
HOLD_PHASE = 3, //-------------------------------------------------------
CAP_PHASE = 3, task init_variables;
PI_LEN = 7, begin
PO_LEN = 2, shift_1 = 3b010;
SO_LEN = 1, cap_1 = 3b010;
CHAIN1_LEN = 3, scan_out[1] = 2;
NUM_VEC = 8; strobe_so = FALSE;
//------------------------------------------------------- strobe_po = FALSE;
//-- Declare statements -- po_mismatch = 0;
//------------------------------------------------------- so_mismatch = 0;
reg [1:SHIFT_PHASE] shift_1; end
reg [1:CAP_PHASE] cap_1; endtask
integer scan_out[1:SO_LEN]; //-------------------------------------------------------
integer strobe_so, strobe_po; //-- Main routine --
integer in, i, error, bit_count; //-------------------------------------------------------
integer cycle, phase; initial
integer so_mismatch, po_mismatch; begin
integer ppi, ppo; init_variables;
integer num_shift_cycle; num_shift_cycle = SHIFT_CYCLE;
integer vec_print; for (in = 1; in <= NUM_VEC; in = in + 1)
integer inst; begin
reg [1:PI_LEN] pi_vector; #1000.00; // settle vectors
reg [1:PO_LEN] po_expected; shift_sequence;
reg [1:SO_LEN] so_expected; $display(\nSimulation processing test vector %0d\n, in);
reg [1:CHAIN1_LEN] si1_vector; vec_print = in;
reg [1:CHAIN1_LEN] so1_expected; hold_sequence;
reg [1:PI_LEN] work_vector; ppo = 0;
reg [1:PO_LEN] sim_response; inst = 1;
reg [1:PI_LEN] pre_work_vector; capture_sequence;
//------------------------------------------------------- reshift_sequence;
//-- Declare wires -- end
//------------------------------------------------------- num_shift_cycle = SHIFT_CYCLE - 1;
wire STI_G17 ; shift_sequence; // scan out the very last pattern
wire STI_SCAN_OUT ; $display(\n*** Test vectors simulated : %d, NUM_VEC);
wire STI_CLK ; $display(*** Number of PO mismatch : %d, po_mismatch);
wire STI_G0 ; $display(*** Number of SO mismatch : %d, so_mismatch);
wire STI_G1 ; $finish;
wire STI_G2 ; end
wire STI_G3 ;
wire STI_STI_TM1 ;
wire STI_SCAN_IN ;
Figure 1-44 The s27_s0.drv.v File (partial)
Full-Scan Tutorial
(file continued) (file continued)

//------------------------------------------------------- end
//-- Sequence tasks -- endtask
//-------------------------------------------------------
task shift_sequence; task reshift_sequence;
begin begin
work_vector = pi_vector; pre_work_vector = work_vector;
work_vector[6] = 1b1; work_vector = pi_vector;
ppi = SHIFT_CYCLE; work_vector[6] = 1b1;
for (cycle = 1; cycle <= num_shift_cycle; cycle = cycle + 1) work_vector[1] = pre_work_vector[1];
begin phase = 1;
phase = 1; while (phase <= SHIFT_PHASE)
while (phase <= SHIFT_PHASE) begin
begin #1.00;
#1.00; #997.00;
work_vector[1] = shift_1[phase]; if (phase == SHIFT_PHASE)
if (ppi > CHAIN1_LEN) work_vector[7] = 1b0; strobe_so = TRUE;
else work_vector[7] = si1_vector[ppi]; phase = phase + 1;
#2.00;
#997.00; end
if (phase == SHIFT_PHASE && in != 1 && cycle != end
SHIFT_CYCLE) endtask
strobe_so = TRUE;
phase = phase + 1; //-------------------------------------------------------
#2.00; //-- Set clock values --
end //-------------------------------------------------------
ppi = ppi - 1; assign #200.00 STI_CLK = work_vector[1];
end //-------------------------------------------------------
end //-- Set input values --
endtask //-------------------------------------------------------
assign #100.00 STI_G0 = work_vector[2];
task hold_sequence; assign #100.00 STI_G1 = work_vector[3];
begin assign #100.00 STI_G2 = work_vector[4];
work_vector = pi_vector; assign #100.00 STI_G3 = work_vector[5];
work_vector[1] = 1b0; assign #100.00 STI_STI_TM1 = work_vector[6];
phase = 1; assign #100.00 STI_SCAN_IN = work_vector[7];
while (phase <= HOLD_PHASE) //-------------------------------------------------------
begin //-- Get output values --
#1.00; //-------------------------------------------------------
#997.00; always
if (phase == HOLD_PHASE) begin
strobe_po = TRUE; fork
phase = phase + 1; #900.00 sim_response[1] = STI_G17 ;
#2.00; #900.00 sim_response[2] = STI_SCAN_OUT ;
end #1000.00;
end join
endtask end
//-------------------------------------------------------
task capture_sequence; //-- Compare expected outputs to simulation results --
begin //-------------------------------------------------------
work_vector = pi_vector; always #999.00
phase = 1; begin
while (phase <= CAP_PHASE) if (strobe_so) // compare scan out
begin begin
#1.00; compare_so;
work_vector[1] = cap_1[phase]; if (error)
#997.00; begin
phase = phase + 1; print_so_mismatch;
#2.00; so_mismatch = so_mismatch + 1;
end end
Figure 1-45 The s27_s0.drv.v File (continued)
Full-Scan Tutorial
(file continued) (file continued)

inst = inst + 1;
strobe_so = FALSE; bit_count = bit_count + 1;
end end
if (strobe_po) // compare primary output $write(\n);
begin end
compare_po; endtask
if (error)
begin task compare_po;
print_po_mismatch; begin
po_mismatch = po_mismatch + 1; error = FALSE;
end for (i=1; i <= PO_LEN && error === FALSE; i=i+1)
strobe_po = FALSE; begin
end if (po_expected[i] !== 1bx && po_expected[i] !== 1bz)
#1.00; if (po_expected[i] !== sim_response[i]) error = TRUE;
end end
end
task compare_so; endtask
begin
i = CHAIN1_LEN - ppo; task print_po_mismatch;
if (i <= 0) so_expected[1] = 1bx; begin
else so_expected[1] = so1_expected[i]; $write(*** PO mismatch at vector %0d,, vec_print, time
error = FALSE; %0d\n, $time);
for (i=1; i <= SO_LEN && error === FALSE; i=i+1) bit_count = 1;
begin for (i = 1; i <= PO_LEN; i = i + 1)
if (so_expected[i] !== 1bx && so_expected[i] !== 1bz) begin
if (so_expected[i] !== sim_response[scan_out[i]]) error = if (po_expected[i] !== 1bx && po_expected[i] !== 1bz)
TRUE; begin
end if (po_expected[i] !== sim_response[i])
ppo = ppo + 1; $write(PO #%0d expected = %b simulated = %b\n,
end bit_count, po_expected[i], sim_response[i]);
endtask end
bit_count = bit_count + 1;
task print_so_mismatch; end
begin $write(\n);
$write(*** SO mismatch at vector %0d,, vec_print, scan end
out number %0d,, inst, time %0d\n, $time); endtask
bit_count = 1;
for (i = 1; i <= SO_LEN; i = i + 1)
begin include s27_s0.vector
if (so_expected[i] !== 1bx && so_expected[i] !== 1bz)
begin endmodule
if (so_expected[i] !== sim_response[scan_out[i]])
$write(scan chain #%0d expected = %b simulated =
%b\n,
bit_count, so_expected[i], sim_response[scan_out[i]]);
end
Figure 1-46 The s27_s0.drv.v File (end)
Full-Scan Tutorial
The s27_s0.vector file is shown in Figure 1-47.
// FILE : SynTest Verilog vector file

// NAME : s27_s0.vector (file continued)
// TIME : Thu Jan 1 15:44:57 1998
// OPTIONS : -vlog -fscan pi_vector = 7b0000100;
po_expected = 2b11;
initial si1_vector = 3b111;
begin #12000.00;
pi_vector = 7b0101101; so1_expected = 3b001;
po_expected = 2b00; #7000.00;
si1_vector = 3b000;
#12000.00; pi_vector = 7b0010001;
po_expected = 2b10;
so1_expected = 3b010; si1_vector = 3b000;
#7000.00; #12000.00;
po_expected = 2b10; #7000.00;
si1_vector = 3b110;
#12000.00; pi_vector = 7b0101011;
po_expected = 2b10;
#7000.00; #12000.00;
po_expected = 2b00; #7000.00;
si1_vector = 3b010;
#12000.00; pi_vector = 7b0011000;
po_expected = 2b10;
#7000.00; #12000.00;
po_expected = 2b11; #7000.00;
si1_vector = 3b011;
#12000.00; end
so1_expected = 3b101;
#7000.00;
Figure 1-47 s27_s0.vector File
Full-Scan Tutorial
Running a Full-Scan Test Using a Script File
The frun script shown in can be used to run the full-scan test with the same result as the
previous interactive run.
#!/bin/csh -f
##1) Create Directory Structure
mkdir designs lib 123 fscan dbg
##2) Compile cell library and netlist

expin s27
##3) Do testability analysis

asic123 s27 -o 123/s27
##4) Do full-scan selection

scansel -fscan s27
##5) Do full-scan synthesis and debug

scansyn -fscan s27
scandbg -flush_test 10110 s27_s0 -o dbg/s27_s0.1
##6) Output synthesized netlist

##7) Do full-scan ATPG

asicgen -post_fscan s27_s0 -o fscan/s27_s0
##8) Do pattern conversion

ln -s fscan/s27_s0.tp .
ln -s fscan/s27_s0.int .
tpout -vs -fscan s27_s0
Figure 1-48 Full-Scan Script File - frun
The script will:

Compile cell library and netlist
Do full-scan selection
Do scan extraction and scan verification
1. Execute the frun script. From the Shell prompt,
frun <CR>
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
Full-Scan Tutorial
TIME: Thu Jan 1 15:52:32 1998
***** Pass One *****

File: netsrc/s27.v
***** Pass Two *****
File: netsrc/s27.v
Created: lib/TX.sdb
Created: lib/IV.sdb
Created: lib/BU.sdb
Created: lib/EO.sdb
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Thu Jan 1 15:52:36 1998
* Library Cell FD1

* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Thu Jan 1 15:52:40 1998
Options selected: -o 123/s27.123.rpt
Full-Scan Tutorial
Full-Scan Tutorial


Logic levels .............................. = 5

Cell elements ............................. = 13

Floating nets ............................. = 0
Floating busses ........................... = 0
Bus holders ............................... = 0
Full-Scan Tutorial

---------- ------- ---------- ----------
MEAN - - 68 -
CPU TIME = 0:00:01
END TIME : Thu Jan 1 15:52:43 1998
=================== SCANSEL v2.0.0 r01 (12/22/97 17:06:40) ===================
TIME: Thu Jan 1 15:52:43 1998
Options selected:
Process s27 ...

START TIME = Thu Jan 1 15:52:43 1998
Read in and check circuit at TIME Thu Jan 1 15:52:43 1998


End circuit check at TIME Thu Jan 1 15:52:46 1998
CPU TIME = 0:00:01

Scan Count = 3
Memory Count = 3
END TIME = Thu Jan 1 15:52:47 1998
CPU TIME = 0:00:02
Full-Scan Tutorial
=================== SCANSYN V2.0.0 r01 (12/24/97 17:34:29) ===================
TIME: Thu Jan 1 15:52:47 1998
Options selected: -fscan -o s27.syn.rpt



=============================================
=============================================

======================================================
Report
======================================================
Circuit Name : s27

Full-Scan Tutorial
Synthesis Status
------------------------------------------
DRC Error Status

------------------------------------
Set Error
Found : 0
Fixed : 0
Skiped : 0
Reset Error
Found : 0
Fixed : 0
Skiped : 0
Shift Clock Error

Found : 0
Fixed : 0
Skiped : 0
Capture Clock Error

Found : 0
Fixed : 0
Skiped : 0
Transparent Error
Found : 0
Fixed : 0
Skiped : 0
Bidi Error
Found : 0
Fixed : 0
Skiped : 0
Bus Error
Found : 0
Fixed : 0
Skiped : 0
Cross Coupled Error

Found : 0
Fixed : 0
Skiped : 0
RAM Error
Found : 0
Fixed : 0
Skiped : 0
Tri-State Pad Error

Found : 0
Fixed : 0
Skiped : 0

----------------------------------------------

------------------------------------------
Sequence | STI_TM1
-----------+------------------------------
Full-Scan Tutorial
Normal | 0
Shift | 1
Hold | X
Capture | X
------------------------------------------

======================================================
CPU TIME = 0:00:12
END TIME : Thu Jan 1 15:53:11 1998
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Thu Jan 1 15:53:11 1998


SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :
FORCE : CLK ---> 010
*FLUSH PATTERN TEST:

success!!

success!!
Full-Scan Tutorial
success!!

success!!

success!!

chain - chain_1 OK.
generating chain_1.dbg.pso file ....
success!!
---------------------------- CHAIN STATUS ------------------------------
[NAME] [STATUS] [PSO-FILE] [INV]
chain_1 CHAIN_OK chain_1.dbg.pso N
CPU TIME = 0:00:02
END TIME : Thu Jan 1 15:53:15 1998
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Thu Jan 1 15:53:16 1998


SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :
Full-Scan Tutorial

success!!

success!!

success!!

success!!

success!!

chain - chain_1 OK.
success!!
---------------------------- CHAIN STATUS ------------------------------
CPU TIME = 0:00:02
END TIME : Thu Jan 1 15:53:19 1998
=================== LSDB V2.0.0 r01 (12/23/97 09:14:47) ===================
TIME: Thu Jan 1 15:53:19 1998
=================== ASICGEN V2.0.0 r01 (02/17/98 19:06:10) ===================
TIME: Tue Feb 17 19:22:04 1998

-dont_scan_loop -must_scan_only -o fscan/s27_s0.rpt

Force CLK Pattern=0

Full-Scan Tutorial









Full-Scan Tutorial





CPU TIME = 0:00:02
END TIME : Tue Feb 17 19:22:13 1998
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 19:25:46 1998
OPTIONS : -vlog -fscan
Number of input pins = 7

Number of output pins = 2
Number of scan instances = 3
Full-Scan Tutorial
- Processing DFT file s27_s0.dft ...
Scan information :
Chain 1, Length is 3
Scan-out pin = SCAN_OUT
Shift sequence
CLK = 010
STI_TM1 = 1
Hold sequence
CLK = 0
Capture sequence
CLK = 010
Clock information :
CLK (P) = 010
- Processing test vector file s27_s0.tp ...
Number of vectors = 8

Verilog driver was saved in s27_s0.drv.v.
*********** END FULL-SCAN ***********
Full-Scan Tutorial
Processing a Full-Scan Design with Memory
In this section, you will run the full-scan test on the Ripple_Rom design. This design is an
8-bit ripple counter which drives the address lines of a ROM. The process and steps are
similar to the s27 design.
designs, directory used to store design database information.
123, directory usedd to store testability analysis (TurboCheck) output files (asic123)
fscan, directory used to store test pattern generation (TurboScan) results (asicgen)
prompt,
a) cd $SYNTEST
b) source .syntest
Sourcing this file sets Unix variables for SynTest.
2. Change your current working directory to ripple_rom/ (this directory is under

$SYNTEST/tutorial). From the syntest/ directory Shell prompt,
cd tutorials/ripple_rom
mkdir lib designs 123 fscan dbg
This action will create five directories: lib, designs, 123, fscan, and dbg.
NOTE
Syntest applications such as expin, and are inluded in
Full-Scan Tutorial

Compile the Verilog netlist and library format into Syntest intermediate file (.sdb)
format using the vlogin utility
design.v
vlogin
library cells .sdb
design .sdb
expin
design.x.sdb
design.c.sdb
design.conp
Figure 1-49 Compiling Process Flow for s27rom Design
Full-Scan Tutorial
To run s27rom flow, you have to convert your memory behavior models and rom codes
(Figure 1-50) into SynTest rom format (Figure 1-51).
// sim_rom.v file for Verilog simulation

// SynTest, Jan 98
module init_rom ( a0 , a1 , a2, q0 , q1 , q2 , ce , re );
input a0 , a1 , a2, ce, re;

output q0 , q1 , q2 ;
reg [3:0] Q;
wire [2:0] A;
wire out0 , out1 , out2 ;
wire CS;
reg [3:0] mem [7:0];
assign { out2 , out1 , out0 } = Q ;

buf buf_a_0 ( A[0] , a0 ) ;
buf buf_a_1 ( A[1] , a1 ) ;
buf buf_a_2 ( A[2] , a2 ) ;
buf buf_q_0 ( q0 , out0 ) ;
and ( CS, ce, re );
initial
begin
$readmemb(sim_rom.rom, mem);
end // sim_rom.rom file for Verilog simulation
always @(CS or A) // binary mapping
begin 000 001 010 011 100 101 110 111
Q = mem[A];
end The original rom
endmodule codes for Verilog
simulation
The behavior memory model in Verilog format
Figure 1-50 The Verilog Beahvior Rom Model and Codes
Full-Scan Tutorial
module init_rom ( q0, q1, q2, a0, a1, a2, ce, re ); # s27rom.rom file
output q0, q1, q2; # binary explicit mapping
input a0, a1, a2, ce, re; .r I27.I0
.i 3
ROM8x3 I0 ( .Q0(q0), .o 3
.Q1(q1), .p 8
.Q2(q2), 000 000
.A0(a0), 001 001
.A1(a1), 010 010
.A2(a2), 011 011
.D0(1b0), 100 100
.D1(1b0), 101 101
.D2(1b0), 110 110
.CS(cs), 111 111
.RWB(1b1)
); The mapping rom codes
and I1 ( cs, ce, re );
endmodule
The mapping rom model
Figure 1-51 Mapping Rom Model and Binary Rom Codes in SynTest Format
The Verilog cell library file and the Verilog netlist file are shown in Figure 1-52 and Figure
1-53.
Full-Scan Tutorial

module TX (Z, A, E); module EO (Z, A, B);
output Z; output Z;
input A, E; input A, B;
bufif1 (Z, A, E); xor (Z, A, B);
endmodule endmodule
module IV (Z, A); module MUX21H (Z, A, S, B);

output Z; output Z;
not (Z, A); wire SN, NA1, NA2;
and (NA1, A, SN);
module BU (Z, A); and (NA2, B, S);
input A; endmodule
buf (Z, A);
output Q, QN;
module AN2 (Z, A, B); input CP, D;
and (Z, A, B); endmodule
endmodule
module ND2 (Z, A, B); output Q, QN;
nand (Z, A, B); and (NA1, D, TEN);
or (Z, NA1, NA2);
module OR2 (Z, A, B); DFF I1 (.Q(Q), .D(Z), .CK(CP));
or (Z, A, B);
endmodule
module NR2 (Z, A, B);

output Z;
input A, B;
nor (Z, A, B);
endmodule
Figure 1-52 Cell Library s27lib.v File
Full-Scan Tutorial
module s27rom (G17, CLK, G0, G1, G2, G3, rom_init, a0, a1, a2 );
output G17;
input CLK, G0, G1, G2, G3, rom_init, a0, a1, a2;
wire G5, G10, G6, G11, G7;
wire G13, G14, G8, G15, G12;
wire G16, G9;
// modified circuit for rom by syntest 01/14/98
wire G51, G61, G71, normal, read_rom;
wire q5, q6, q7;
FD1 I5 (.Q(G5), .D(G10), .CP(CLK));
FD1 I6 (.Q(G6), .D(G11), .CP(CLK));
FD1 I7 (.Q(G7), .D(G13), .CP(CLK));
IV I14 (.Z(G14), .A(G0));
IV I17 (.Z(G17), .A(G11));
AN2 I8 (.Z(G8), .A(G14), .B(G61));
OR2 I15 (.Z(G15), .A(G12), .B(G8));
OR2 I16 (.Z(G16), .A(G3), .B(G8));
ND2 I9 (.Z(G9), .A(G16), .B(G15));
NR2 I10 (.Z(G10), .A(G14), .B(G11));
NR2 I11 (.Z(G11), .A(G51), .B(G9));
NR2 I12 (.Z(G12), .A(G1), .B(G71));
NR2 I13 (.Z(G13), .A(G2), .B(G12));
// modified circuit for rom by syntest 01/14/98
TX I20 ( .Z(G51), .A(G5), .E(normal) );
TX I21 ( .Z(G61), .A(G6), .E(normal) );
TX I22 ( .Z(G71), .A(G7), .E(normal) );
IV I23 ( .Z(normal), .A(read_rom) );
TX I24 ( .Z(G51), .A(q5), .E(read_rom) );
init_rom I27 ( .q0(q5), .q1(q6), .q2(q7),
.a0(a0), .a1(a1), .a2(a2),
.ce(rom_init), .re(read_rom)
);
AN2 I28 ( .Z(read_rom), .A(CLK_bar), .B(rom_init) );
IV I29 ( .Z(CLK_bar), .A(CLK) );
endmodule
Figure 1-53 Netlist s27rom.v File
Compiling the Verilog Files
You will use vlogin to compile the Verilog netlist and cell library files into SynTest
intermediate format (.sdb). Detailed information regarding this utility can be found in
Command Reference, Chapter 11 and Creating the Syntest Database and Libraries,
Chapter 3.
4. Compile the library, s27lib.v and init_rom.v. From the Shell prompt,
vlogin -lib libsrc/s27lib.v
vlogin -lib libsrc/init_rom.v
Full-Scan Tutorial
This action will generate a cell sdb files for each cell in the library file. The processing
messages are shown in Figure 1-54.
The -nf option disables faulting within the library cells, and -drc performs connectivity
design rule checks on the cells. The two option are typically used for library compilation and
enabled automatically by turning on the option -lib.
The other option which is on always when -lib is specified is -opath lib. This option outputs
the .sdb files into the lib sub-directory created for this run. Since one .sdb file is created for
each cell in the library, the directory organization eliminates cluttering the main design
directory with many files.
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Sun Feb 8 15:55:22 1998
***** Pass Two *****
Created: lib/TX.sdb ================ VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ================
Created: lib/IV.sdb
Created: lib/BU.sdb Copyright (c), 1991-1997, SynTest Technologies, Inc. All rights reserved.
Created: lib/ND2.sdb TIME: Sun Feb 8 16:02:33 1998
Created: lib/NR2.sdb File: libsrc/init_rom.v
Created: lib/EO.sdb Parsed: init_rom (interface only)
Created: lib/MUX21H.sdb ***** Pass Two *****
Created: lib/FD1.sdb File: libsrc/init_rom.v
Figure 1-54 Library Compilation Processing Messages
5. Compile the netlist, s27.v. From the Shell prompt:
vlogin s27rom.v -opath designs
This action will create the design module sdb files, s27rom.sdb. The processing
messages are shown in Figure 1-55.
Full-Scan Tutorial
The -opath option redirects the compiled .sdb files to the designs sub-directory.
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Sun Feb 8 16:02:50 1998
File: netsrc/s27rom.v
Parsed: s27rom (interface only)
***** Pass Two *****
Created: designs/s27rom.sdb
Figure 1-55 Netlist Compilation Processing Messages
The design must be linked and expanded (flattened) before you can perform synthesis or run
the test vector generation programs.
discussion of these files). In this example the primitive.def file has been modified to
describe the 8X3 ROM.
expin s27rom
This command execution will create three new design files in the sub-directory designs. The
files are:
s27rom.c.sdb, contains design linked and flattened down to the library cell level.
This file will be used by the scan synthesis application (scansyn)
s27rom.x.sdb, contains the design linked and flattened down to the Syntest primitive
level. This file will be used by the testability analysis application and test patterns
s27rom.conp, contains design connectivity information used to link the .c.sdb to
.x.sdb files. If missing, errors may occur.
Full-Scan Tutorial
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Sun Feb 8 16:04:36 1998
Expanded: ./designs/s27rom.x.sdb
* Library Cell FD1
* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
* Library Cell TX
* Library Cell init_rom
Expanded: ./designs/s27rom.c.sdb
In this section, you will use the testability analysis program, asic123 (TurobCheck), to do
the following:
Determine the controllability and observability for the design using full-scan with a
rom

The tool asic123 reads:

the .dft file that can contains logic value and condition settings (optional)
can be used. If it is not available, asic123 will automatically determine optimum
Full-Scan Tutorial
the binary rom codes .rom file
1. Observe the s27rom.dft file. From the shell prompt,
more s27rom.dft
The user-defined s27rom.dft is shown in Figure 1-57.

(File continued)
%ATPG_CONSTRAINTS
{
%ATPG_MODE FULL_SCAN // Define a scan chain with type MDFF and name chain_1
%FORCE CLK = 0; {
} %SCAN_CLOCK_1
%ATPG_MODE PF_SCAN {
{ /* The port providing shift clock */
%FORCE CLK = 0; %CLOCK = CLK;
} %GLOBAL_CLOCK = CLK;
} }
%SCAN_INSTANCES_FILE
%SEQUENCE shift_seq {
{ %FILE_NAME = s27rom.sel1.pso;
%FORCE CLK = 010; }
} %SCAN_PORT
{
%SEQUENCE hold_seq /* scan data is shifted thru these two ports */
} %DEFAULT = SCAN_;
}
%SEQUENCE capture_seq %SCAN_INSTRUCTION
{ {
%FORCE CLK = 010; %INSTRUCTION = instruction1;
} }
}
%READ_MAP
{ %SCAN_DECODER
%FILE_NAME = s27.map; {
} %CONTROL_PORT_1 = STI_TM1;
%CONTROL_PORT_2 = STI_TM2;
{
%MODE = scan;
%SHIFT = shift_seq;
%HOLD = hold_seq;
%CAPTURE = capture_seq;
}
Figure 1-57 The User-defined s27rom.dft
Full-Scan Tutorial
asic123 s27rom -o 123/s27rom
name s27rom. The processing messages generated are saved to the report file
s27rom.123.rpt, shown in Figure 1-58 to Figure 1-61.
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Sun Feb 8 16:06:23 1998
Options selected: -fscan -o 123/s27rom.123.rpt
Figure 1-58 Testability Analysis Processing Message - Report File
Full-Scan Tutorial
Loading memory data from s27rom.rom: rom code detected

Memory object: I27.I0 (ROM8x3)
Clock net driving information is saved in 123/s27rom.clk.rpt.
Figure 1-59 Testability Analysis Processing Message - Report File (continued)
Full-Scan Tutorial
**** The following bus outputs do not have a PULLUP/PULLDOWN/REPEATER :

1) G51
2) G61
3) G71

The rom is detected.

Logic levels .............................. = 5
Figure 1-60 Testability Analysis Processing Message - Report File (continued)
Full-Scan Tutorial
Cell elements ............................. = 23


Floating nets ............................. = 0
Floating busses ........................... = 3
Bus holders ............................... = 0

---------- ------- ---------- ----------
MEAN - - 12 -
CPU TIME = 0:00:02
END TIME : Sun Feb 8 16:06:28 1998
Figure 1-61 Testability Analysis Processing Message - Report File (end)

s27rom.123.rpt, file containing processing messages and a testability analysis report
s27rom.clk.rpt, clock tree information report file
Full-Scan Tutorial
The s27rom.clk.rpt is shown in Figure 1-62.
**** Order: Type Root_Clock -> Local_Clock Object ****

1) DFF CLK -> CLK I5
Figure 1-62 The Clock Report s27rom.clk.rpt
Full-Scan Tutorial
file. This file, created by scansel, determines the scan order for scan chains.

scansel -fscan s27rom

s27rom.sel1.pso, file produced by the -fscan option containing a list of flip-flops
from the design (with netlist default order)
s27rom.sel.rpt, file recording processing message and a report
The processing messages and the list of flip-flops file are the same as Figure 1-18, Figure 1-
The purpose of scan synthesis is to replace non-scan flip flop with scan flip flop.

Scan debugging

a .pso, scan element list file created by scansel or by the designers
a .dft file containing design specific information
a .map file containing mapping information between generic and scanable memory
cells. The s27.map is the same as Figure 1-21.
Full-Scan Tutorial
a .rom file containg the binary rom codes
1. Copy the rom codes file. From the Shell prompt,
cp s27rom.rom s27_rom.rom
2. Copy the rom codes file. From the Shell prompt,
scansyn -fscan s27rom
The processing messages are shown in Figure 1-63 and Figure 1-64.

report and log files (s27rom.syn.rpt, s27rom.syn.log). Actually, s27rom.syn.log
contains three log files: scan_decoder.vlogin.log, s27rom_s0.expin.log, and
s27rom_s0.syn.rpt.
scansyn_lib sub-directory containing a new version of the design files
(s27rom_s0.*) that can be translated to VHDL, Edif, and Verilog format using the
lsdb translator.
s27rom_s0.dft, the modified .dft file for running scandbg, asicgen, and tpout to
s27rom_s0.syn1.pso and s27rom_s0.ext1.pso, which are generated by scansyn and
scansyn -extract_only (automatically) separately, containing a list of the scan flip-
flops.
Full-Scan Tutorial
=================== SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ===================
TIME: Wed Feb 11 18:33:44 1998
Options selected: -fscan -o s27rom.syn.rpt
- Reading top level netlist ./designs/s27rom.sdb ...
- Reading expanded netlist ./designs/s27rom.x.sdb ...
- Reading cell-level netlist ./designs/s27rom.c.sdb ...


- Copy ./designs/s27rom.sdb => ./scansyn_lib/s27rom_s0.sdb.
- Please read s27rom.syn.log for messages.
- Executing commands in ./scansyn_lib/s27rom_s0.cmd ...
- Generating new cell level pso file s27rom_s0.syn1.pso ...
- Generating new dft file s27rom_s0.dft...

=============================================
=============================================
- Expanding synthesized design s27rom_s0.sdb ...
- Extract scan chain from s27rom_s0 ...

please refer to s27rom_s0.syn.rpt.
======================================================
Report
======================================================
Figure 1-63 scansyn Processing Messages - s27rom.syn.rpt File
Full-Scan Tutorial
Circuit Name : s27rom (Messages continued)

New Circuit Name : s27rom_s0
Scan In Port Name : Chain 1 -> SCAN_IN RAM Error
Scan Out Port Name : Chain 1 -> SCAN_OUT Found : 0
Added Control Port : STI_TM1 Fixed : 0
Synthesis Status Skiped : 0
------------------------------------------
Replaced Memory Cells : 3 Tri-State Pad Error
Found : 0
DRC Error Status Fixed : 0
------------------------------------ Skiped : 0
Set Error
Found : 0
Fixed : 0
Skiped : 0
Reset Error Scan Decoder Loading Information

Found : 0 ----------------------------------------------
Fixed : 0 SCANSYN_SCAN uses BUF(BU) to drive 3 gates.
Skiped : 0
Shift Clock Error

Found : 0 Scan Decoder Control Table
Fixed : 0
Skiped : 0 ------------------------------------------
Sequence | STI_TM1
Capture Clock Error -----------+------------------------------
Found : 0
Fixed : 0 Normal | 0
Skiped : 0 Shift | 1
Hold | X
Transparent Error
Found : 0 Capture | X
Fixed : 0 ------------------------------------------
Skiped : 0
Bidi Error Report File : s27rom.syn.rpt

Found : 0 Log File : s27rom.syn.log
Fixed : 0 ======================================
Skiped : 0 ================
Bus Error
Found : 0 CPU TIME = 0:00:14
Fixed : 0
Skiped : 0
END TIME : Wed Feb 11 18:34:06 1998
Cross Coupled Error
Found : 0
Fixed : 0
Skiped : 0
Figure 1-64 scansyn Processing Messages - s27rom.syn.rpt File (continued)
The s27rom.syn.log file is shown in Figure 1-65 and Figure 1-66.
Full-Scan Tutorial
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Wed Feb 11 18:33:51 1998
***** Pass One *****

***** Pass Two *****
--- run ./scansyn_lib/s27rom_s0.cmd ----

--- /home/users/barbara/syntest/bin/expin s27rom_s0.sdb ----
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Wed Feb 11 18:33:59 1998
Expanded: ./scansyn_lib/s27rom_s0.x.sdb
* Library Cell FD1S

* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
* Library Cell TX
* Library Cell BU
Expanded: ./scansyn_lib/s27rom_s0.c.sdb
=================== SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ===================
TIME: Wed Feb 11 18:34:03 1998
Options selected: -fscan -extract_only -o s27rom_s0.syn.rpt
- Reading top level netlist ./scansyn_lib/s27rom_s0.sdb ...
- Reading expanded netlist ./scansyn_lib/s27rom_s0.x.sdb ...

Figure 1-65 The s27rom.syn.log file
Full-Scan Tutorial
---==========--- Scan Extraction ---==========---

------=======================================================------
Initializing ...

Successfully!

3 scan cells were written into file s27rom_s0.ext1.pso.

CPU TIME = 0:00:02
END TIME : Wed Feb 11 18:34:06 1998
Figure 1-66 The s27rom.syn.log file (continued)
Beside replacing non-scan flip-flops and Latches in the design with their scanable
Running Scan Debug
3. Run scan debug. From the Shell prompt,
scandbg -flush_test 10110 s27rom_s0 -o dbg/s27rom_s0.1
Full-Scan Tutorial
The outputs report files created under the sub-directory dbg/ are shown in Figure 1-67 and
Figure 1-68.
========== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===========
Copyright (c), 1991-1997, SynTest Technologies, Inc. All rights reserved. (File continued)
TIME: Wed Feb 11 18:35:29 1998 INSTANCES : 3 ---> 3 scan objects
Options selected: -flush_test 10110 -o dbg/s27rom_s0.1.dbg.rpt

Loading memory data from s27rom_s0.rom:

Memory object: I27.I0 (ROM8x3) simulation 1 : cycle 1 : =>
success!!
**** CIRCUIT STATISTICS **** simulation 4 : cycle 2 : =>

success!!
chain - chain_1 OK.
Number of inaccessible latches .... = 0 generating chain_1.dbg.pso file ....
Number of inaccessible flip-flops . = 0 success!!
Total inaccessible memory elements = 0 Simulation Complete!!
---------------------------- CHAIN STATUS ----------------------------

LEVELIZATION CPU TIME = 0:00:02 --
LEVELIZATION END TIME : Wed Feb 11 18:35:33 1998 [NAME] [STATUS] [PSO-FILE] [INV]
Scan-Chain 1 - chain_1: chain_1 CHAIN_OK chain_1.dbg.pso N

SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK CPU TIME = 0:00:02
SHIFT :
FORCE : CLK ---> 010 END TIME : Wed Feb 11 18:35:35 1998
Figure 1-67 s27rom_s0.1.dbg.rpt File
Full-Scan Tutorial
=========== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ============
TIME: Wed Feb 11 18:36:14 1998

(File continued)

Memory object: I27.I0 (ROM8x3) *FLUSH PATTERN TEST:
**** CIRCUIT STATISTICS **** simulation 1 : cycle 1 : =>

success!!
success!!
Number of inaccessible RAMs/ROMs .. = 0 chain - chain_1 OK.
Total inaccessible memory elements = 0 generating chain_1.dbg.pso file ....
success!!
LEVELIZATION CPU TIME = 0:00:02 Simulation Complete!!
LEVELIZATION END TIME : Wed Feb 11 18:36:17 1998 ---------------------------- CHAIN STATUS ------------------------------
Scan-Chain 1 - chain_1: [NAME] [STATUS] [PSO-FILE] [INV]

SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT chain_1 CHAIN_OK chain_1.dbg.pso N
CLOCK : CLK
SHIFT :
FORCE : CLK ---> 010 CPU TIME = 0:00:02
INSTANCES : 3 ---> 3 scan objects END TIME : Wed Feb 11 18:36:18 1998
Figure 1-68 s27rom_s0.2.dbg.rpt File
Figure 1-69 illustrates the s27rom design flow during design synthesis, debug, and netlist
Full-Scan Tutorial
s27rom.x.sdb
s27rom.dft
s27rom.c.sdb
s27rom.map
s27rom.sel1.pso
s27rom.rom
scansyn Synthesize
scansyn_lib
s27rom_s0.x.sdb
s27rom_s0.c.sdb
s27rom.syn.rpt
s27rom_s0.sdb
s27rom.syn.log
s27rom_s0.conp
s27rom_s0.syn.rpt
s27rom_s0.cmd s27rom_s0.rom
s27rom_s0.syn1.pso
scan_decoder.v
Debug scandbg
lsdb Netlist
Conversion
s27rom_s0.dbg.rpt
s27rom_s0.vhd
s27rom_s0.v
s27rom_s0.edif
Full-Scan Tutorial
use the lsdb utility to translate the sdb files created by scansyn (s27rom_s0.x.sdb).
1. Convert the s27rom scannable SynTest database to a Verilog netlist. From the Shell
prompt,
lsdb s27rom_s0 -verilog -hierarchy -timescale -o s27rom_s0.v
design hierarchy.
purposes.
The -o option directs the output to the filename
=================== LSDB V2.0.0 r01 (12/23/97 09:14:47) ===================

TIME: Sun Feb 0815:04:43 1998
Netlist output is saved in s27rom_s0.v.
Figure 1-70 The lsbd Processing Messages
2. Display the s27rom_s0.v file. From the Shell prompt,
more s27rom_s0.v
The Verilog netlist is shown in Figure 1-71 abd Figure 1-72.
Full-Scan Tutorial
// File : s27rom_s0.v
// Created: Sun Feb 8 17:09:45 1998
// lsdb -verilog s27rom_s0
// sdb verison 230
//

module s27rom_s0 ( G17 , SCAN_OUT , G0 , G1 ,
G2 , a0 , G3 , a1 ,
a2 , SCAN_IN , CLK , rom_init ,
STI_TM1 ) ;
input G0 , G1 , G2 , a0 ,
G3 , a1 , a2 , SCAN_IN ,
CLK , rom_init , STI_TM1 ;
wire q5 , normal , q6 , q7 ,
G10 , G11 , G12 , G5 ,
G13 , G6 , G14 , G7 ,
G51 , G15 , G8 , read_rom ,
G61 , G9 , G16 , G71 ;
FD1S I5 ( .CP ( CLK ) , .D ( G10 ) , .Q ( G5 ) ,
.TE ( I5_TE ) , .TI ( SCAN_IN ) ) ;
FD1S I6 ( .CP ( CLK ) , .D ( G11 ) , .Q ( G6 ) ,
.TE ( I5_TE ) , .TI ( G5 ) ) ;
FD1S I7 ( .CP ( CLK ) , .D ( G13 ) , .Q ( G7 ) ,
.TE ( I5_TE ) , .TI ( G6 ) ) ;
IV I14 ( .A ( G0 ) , .Z ( G14 ) ) ;
IV I17 ( .A ( G11 ) , .Z ( G17 ) ) ;
AN2 I8 ( .A ( G14 ) , .B ( G61 ) , .Z ( G8 ) ) ;
OR2 I15 ( .A ( G12 ) , .B ( G8 ) , .Z ( G15 ) ) ;
OR2 I16 ( .A ( G3 ) , .B ( G8 ) , .Z ( G16 ) ) ;
ND2 I9 ( .A ( G16 ) , .B ( G15 ) , .Z ( G9 ) ) ;
NR2 I10 ( .A ( G14 ) , .B ( G11 ) , .Z ( G10 ) ) ;
NR2 I11 ( .A ( G51 ) , .B ( G9 ) , .Z ( G11 ) ) ;
NR2 I12 ( .A ( G1 ) , .B ( G71 ) , .Z ( G12 ) ) ;
NR2 I13 ( .A ( G2 ) , .B ( G12 ) , .Z ( G13 ) ) ;
TX I20 ( .A ( G5 ) , .E ( normal ) , .Z ( G51 ) ) ;
TX I21 ( .A ( G6 ) , .E ( normal ) , .Z ( G61 ) ) ;
TX I22 ( .A ( G7 ) , .E ( normal ) , .Z ( G71 ) ) ;
IV I23 ( .A ( read_rom ) , .Z ( normal ) ) ;
Figure 1-71 The converted Verilog File - s27rom_s0.v (partial)
Full-Scan Tutorial
TX I24 ( .A ( q5 ) , .E ( read_rom ) , .Z ( G51 ) ) ;

init_rom I27 ( .a0 ( a0 ) , .a1 ( a1 ) , .a2 ( a2 ) ,
.ce ( rom_init ) , .q0 ( q5 ) , .q1 ( q6 ) , .q2 ( q7 ) ,
.re ( read_rom ) ) ;
AN2 I28 ( .A ( CLK_bar ) , .B ( rom_init ) , .Z ( read_rom ) ) ;
IV I29 ( .A ( CLK ) , .Z ( CLK_bar ) ) ;
SCAN_DECODER_CLASS SCAN_DECODER ( .CTRL1 ( STI_TM1 ) , .SCANSYN_SCAN ( I5_TE ) )
;
endmodule
// File : s27rom_s0.v
// Created: Sun Feb 8 17:09:45 1998
// lsdb -verilog s27rom_s0
// sdb verison 230
//

input CTRL1 ;
endmodule
Figure 1-72 The converted Verilog File - s27rom_s0.v (continued)
Full-Scan Tutorial
Use the test pattern generation utility, asicgen (TurboScan tool), to generate the test
patterns for the s27rom design
Verilog test-bench
s27rom_s0.x.sdb file, the design compiled and flattened to the SynTest primitive
level
s27rom_s0.dft, file contains an entry regarding "%ATPG_CONSTRAINTS" which
s27rom_s0.rom, file contains the binary rom codes, which are copied from the
original file s27rom.rom
s27rom_s0.x.sdb
s27rom_s0.dft
s27rom_s0.rom
asicgen
s27rom_s0.rpt
s27rom_s0.tp
s27rom_s0.int
s27rom_s0.hdt
s27rom_s0.pso
s27rom_s0.red
s27rom_s0.udt
Full-Scan Tutorial
The s27rom_s0.dft file is shown in Figure 1-74.
// File : s27rom_s0.dft
// (c) 1991-1995, SynTest Technologies, Inc. ( File continued)
/* scan data is shifted thru these two ports */

%SCAN_IN = SCAN_IN;
// Scan instruction sequence %SCAN_OUT = SCAN_OUT;
%SEQUENCE shift_seq %DEFAULT = SCAN_;
{ }
%FORCE CLK = 010; %SCAN_CLOCK_1
%FORCE STI_TM1 = 111; {
} /* The port providing shift clock */
%SEQUENCE hold_seq %CLOCK = CLK;
{ %GLOBAL_CLOCK = CLK;
%FORCE CLK = 000; }
%SEQUENCE capture_seq {
{ %FILE_NAME = s27rom_s0.ext1.pso;
%FORCE CLK = 010; }
} %SCAN_INSTRUCTION
{
%INSTRUCTION = instruction1;
// Instruction }
{ // Test Generation Constraints
%MODE = scan; // For full-scan test pattern generation
%SHIFT = shift_seq; %ATPG_CONSTRAINTS
%HOLD = hold_seq; {
%CAPTURE = capture_seq; %ATPG_MODE FULL_SCAN
} {
%FORCE CLK = 0;
}
// Read Mapping_cell File %ATPG_MODE PF_SCAN
%READ_MAP {
{ %FORCE CLK = 0;
%FILE_NAME = s27.map; }
} }
// Connect Scan Chain // Scan Decoder

// Define a scan chain with type MDFF and name chain_1 %SCAN_DECODER
%CONNECT_SCAN chain_1 MDFF {
{ %CONTROL_PORT_1 = STI_TM1;
%SCAN_PORT %CONTROL_PORT_2 = STI_TM2;
{ }
Figure 1-74 The s27rom_s0.dft File
3. Generate the test patterns. From the Shell prompt,
asicgen -post_fscan s27rom_s0 -o fscan/s27rom_s0
Full-Scan Tutorial
The -post_fscan option causes full-scan test pattern generation.

The -o option redirects the output to the fscan subdirectory.
The asicgen processing messages are shown in Figure 1-75 and Figure 1-76.
=================== ASICGEN V2.0.0 r01 (02/17/98 19:06:10) ===================
TIME: Tue Feb 17 21:04:48 1998

-dont_scan_loop -must_scan_only -o fscan/s27rom_s0.rpt
Read constraints from s27rom_s0.dft.....

Force CLK Pattern=0
Read scan specifications from s27rom_s0.dft.....





Select 2 weighted patterns detected 63 faults

Pass 0: CPU TIME = 0:00:02
atpg: Pass 1 [ 6] 75 DET ( 65.2%), 7 UNT ( 6.1%), 3 vec

CPU time: 0:00:00
CPU time: 0:00:00
Figure 1-75 asicgen Processing Messages - s27rom_s0.rpt
Full-Scan Tutorial
Before static compact: CPU TIME = 0:00:02 10 vec

Building fault dictionary...
Selecting patterns...
After static compact: CPU TIME = 0:00:02 9 vec
95 Hard detected faults are saved in fscan/s27rom_s0.hdt.
20 Redundant faults are saved in fscan/s27rom_s0.red.
The circuit s27rom_s0.x.sdb has 11 inputs, 3 scan objects, and 2 outputs.
95 ( 82.61%) faults were Hard detected (HD).




CPU TIME = 0:00:02
END TIME : Tue Feb 17 21:04:57 1998
Figure 1-76 asicgen Processing Messages - s27rom_s0.rpt (continued)

s27rom_s0.rpt, fault coverage report file
Full-Scan Tutorial
s27rom_s0.tp, test pattern file

s27rom_s0.hdt, hard-detected faults
s27rom_s0.udt, undetected faults
s27rom_s0.red, redundant or untestable faults file
s27rom_s0.int, top module pin interface file
s27rom_s0.pso, scan elements list file
r S
o SS C
m TC AIII
_ IA N567
i _N ____
C n T_ GOPPP
LGGGGiaaaMIIII1UPPP
K0123t0121N5677TOOO
-STEM-
1 S LLLLLHLHHLLHLL---++
2 S LLHHLHLLHLHLHH++---
3 S LHLLHHHLLLLHHL+-+--
4 S LHLHHHLLLLHHLL---+-
5 S LLHLLLHLHLHHHL+---+
6 S LLLLLLLLHLLLLL+----
7 S LLHLLLHLHHLLHL----+
8 S LHHLHLHLHHLLHH++--+
9 S LLLHHLLHHLHLLH++---
Figure 1-77 The s27rom_s0.tp File
Full-Scan Tutorial
The test pattern files created by asicgen are stored in the fscan sub-directory. Before
a) ln -s fscan/s27rom_s0.tp .
b) ln -s fscan/s27rom_s0.int .
tpout -vlog -fscan s27rom_s0

The -fscan option specifies translation of full-scan vectors.
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 21:06:04 1998
- Processing interface file s27rom_s0.int ...

Capture sequence
- Processing DFT file s27rom_s0.dft ... CLK = 010
Scan information : Clock information :
Chain 1, Length is 3 CLK (P) = 010

Scan-out pin = SCAN_OUT - Processing test vector file s27rom_s0.tp ...
Sequence information : Number of vectors = 9

Shift sequence
CLK = 010 - Translating patterns and generating driver file ...
STI_TM1 = 1
Verilog vectors were saved in s27rom_s0.vector.
Hold sequence Verilog driver was saved in s27rom_s0.drv.v.
CLK = 0
Figure 1-78 tpout Processing Messages - s27rom_s0.tpout.rpt File

Full-Scan Tutorial

a report file, s27rom_s0.tpout.rpt
a Verilog timing driver file, s27rom_s0.drv.v
a Verilog pattern file, s27rom_s0.vector
The Verilog driver file, s27rom_s0.drv.v, controls a Verilog simulation of the full set of
patterns generated by asicgen. It reads the scan test data and compares the expected data
both from s27rom_s0.vector file. This verification process in Verilog can be used to
completely verify the pattern set before taping out the design. The s27rom_s0.drv.v is shown
from Figure 1-79 to Figure 1-82.
// FILE : SynTest Verilog driver file (file continued)

// NAME : s27rom_s0.drv.v reg [1:PO_LEN] po_expected;
// TIME : Sun Feb 8 18:03:30 1998 reg [1:SO_LEN] so_expected;
// OPTIONS : -vlog -fscan reg [1:CHAIN1_LEN] si1_vector;
reg [1:CHAIN1_LEN] so1_expected;
timescale 1ns / 10ps reg [1:PI_LEN] work_vector;
reg [1:PO_LEN] sim_response;
define TRUE 1 reg [1:PI_LEN] pre_work_vector;
define FALSE 0 //-------------------------------------------------------
//-- Declare wires --
module s27rom_s0_top ; //-------------------------------------------------------
//------------------------------------------------------- wire STI_G17 ;
//-- Declare parameters -- wire STI_SCAN_OUT ;
//------------------------------------------------------- wire STI_CLK ;
parameter wire STI_G0 ;
SHIFT_PHASE = 3, wire STI_G1 ;
SHIFT_CYCLE = 3, wire STI_G2 ;
HOLD_PHASE = 3, wire STI_G3 ;
CAP_PHASE = 3, wire STI_rom_init ;
PI_LEN = 11, wire STI_a0 ;
PO_LEN = 2, wire STI_a1 ;
SO_LEN = 1, wire STI_a2 ;
CHAIN1_LEN = 3, wire STI_STI_TM1 ;
NUM_VEC = 12; wire STI_SCAN_IN ;
//------------------------------------------------------- //-------------------------------------------------------
//-- Declare statements -- //-- Call module --
//------------------------------------------------------- //-------------------------------------------------------
reg [1:SHIFT_PHASE] shift_1; s27rom_s0 s27rom_s0_inst (
reg [1:CAP_PHASE] cap_1; .G17 ( STI_G17 ) ,
integer scan_out[1:SO_LEN]; .SCAN_OUT ( STI_SCAN_OUT ) ,
integer strobe_so, strobe_po; .CLK ( STI_CLK ) ,
integer in, i, error, bit_count; .G0 ( STI_G0 ) ,
integer cycle, phase; .G1 ( STI_G1 ) ,
integer so_mismatch, po_mismatch; .G2 ( STI_G2 ) ,
integer ppi, ppo; .G3 ( STI_G3 ) ,
integer num_shift_cycle; .rom_init ( STI_rom_init ) ,
integer vec_print; .a0 ( STI_a0 ) ,
integer inst; .a1 ( STI_a1 ) ,
reg [1:PI_LEN] pi_vector; .a2 ( STI_a2 ) ,
Figure 1-79 The s27rom_s0.tim.drv.v File (partial)

Full-Scan Tutorial
(file continued)
.STI_TM1 ( STI_STI_TM1 ) ,
.SCAN_IN ( STI_SCAN_IN ) ); begin
//------------------------------------------------------- #1.00;
//-- Init variables -- work_vector[1] = shift_1[phase];
//------------------------------------------------------- if (ppi > CHAIN1_LEN) work_vector[11] =
task init_variables; 1b0;
begin else work_vector[11] = si1_vector[ppi];
shift_1 = 3b010;
cap_1 = 3b010; #997.00;
scan_out[1] = 2; if (phase == SHIFT_PHASE && in != 1 &&
strobe_so = FALSE; cycle != SHIFT_CYCLE)
strobe_po = FALSE; strobe_so = TRUE;
po_mismatch = 0; phase = phase + 1;
so_mismatch = 0; #2.00;
end end
endtask ppi = ppi - 1;
//------------------------------------------------------- end
//-- Main routine -- end
//------------------------------------------------------- endtask
initial
begin task hold_sequence;
init_variables; begin
num_shift_cycle = SHIFT_CYCLE; work_vector = pi_vector;
for (in = 1; in <= NUM_VEC; in = in + 1) work_vector[1] = 1b0;
begin phase = 1;
#1000.00; // settle vectors while (phase <= HOLD_PHASE)
shift_sequence; begin
$display(\nSimulation processing test vector #1.00;
%0d\n, in); #997.00;
vec_print = in; if (phase == HOLD_PHASE)
hold_sequence; strobe_po = TRUE;
ppo = 0; phase = phase + 1;
inst = 1; #2.00;
capture_sequence; end
reshift_sequence; end
end endtask
num_shift_cycle = SHIFT_CYCLE - 1;
shift_sequence; // scan out the very last pattern task capture_sequence;
$display(\n*** Test vectors simulated : %d, begin
NUM_VEC); work_vector = pi_vector;
$display(*** Number of PO mismatch : %d, phase = 1;
po_mismatch); while (phase <= CAP_PHASE)
$display(*** Number of SO mismatch : %d, begin
so_mismatch); #1.00;
$finish; work_vector[1] = cap_1[phase];
end #997.00;
//------------------------------------------------------- phase = phase + 1;
//-- Sequence tasks -- #2.00;
//------------------------------------------------------- end
task shift_sequence; end
begin endtask
work_vector = pi_vector;
work_vector[10] = 1b1; task reshift_sequence;
ppi = SHIFT_CYCLE; begin
for (cycle = 1; cycle <= num_shift_cycle; cycle = pre_work_vector = work_vector;
cycle + 1) work_vector = pi_vector;
begin work_vector[10] = 1b1;
phase = 1; work_vector[1] = pre_work_vector[1];
while (phase <= SHIFT_PHASE) phase = 1;
Figure 1-80 The s27rom_s0.tim.drv.v File (continued)

Full-Scan Tutorial
(file continued)
while (phase <= SHIFT_PHASE)
begin begin
#1.00; compare_po;
#997.00; if (error)
if (phase == SHIFT_PHASE) begin
strobe_so = TRUE; print_po_mismatch;
phase = phase + 1; po_mismatch = po_mismatch + 1;
#2.00; end
end strobe_po = FALSE;
end end
endtask #1.00;
end
//-------------------------------------------------------
//-- Set clock values -- task compare_so;
//------------------------------------------------------- begin
assign #200.00 STI_CLK = work_vector[1]; i = CHAIN1_LEN - ppo;
//------------------------------------------------------- if (i <= 0) so_expected[1] = 1bx;
//-- Set input values -- else so_expected[1] = so1_expected[i];
//------------------------------------------------------- error = FALSE;
assign #100.00 STI_G0 = work_vector[2]; for (i=1; i <= SO_LEN && error === FALSE;
assign #100.00 STI_G1 = work_vector[3]; i=i+1)
assign #100.00 STI_G2 = work_vector[4]; begin
assign #100.00 STI_G3 = work_vector[5]; if (so_expected[i] !== 1bx && so_expected[i]
assign #100.00 STI_rom_init = work_vector[6]; !== 1bz)
assign #100.00 STI_a0 = work_vector[7]; if (so_expected[i] !==
assign #100.00 STI_a1 = work_vector[8]; sim_response[scan_out[i]]) error = TRUE;
assign #100.00 STI_a2 = work_vector[9]; end
assign #100.00 STI_STI_TM1 = work_vector[10]; ppo = ppo + 1;
assign #100.00 STI_SCAN_IN = end
work_vector[11]; endtask
//-------------------------------------------------------
//-- Get output values -- task print_so_mismatch;
//------------------------------------------------------- begin
always $write(*** SO mismatch at vector %0d,,
begin vec_print, scan out number %0d,, inst, time
fork %0d\n, $time);
#900.00 sim_response[1] = STI_G17 ; bit_count = 1;
#900.00 sim_response[2] = STI_SCAN_OUT ; for (i = 1; i <= SO_LEN; i = i + 1)
#1000.00; begin
join if (so_expected[i] !== 1bx && so_expected[i]
end !== 1bz)
//------------------------------------------------------- begin
//-- Compare expected outputs to simulation if (so_expected[i] !==
results -- sim_response[scan_out[i]])
//------------------------------------------------------- $write(scan chain #%0d expected = %b sim-
always #999.00 ulated = %b\n,
begin bit_count, so_expected[i],
if (strobe_so) // compare scan out sim_response[scan_out[i]]);
begin end
compare_so; bit_count = bit_count + 1;
if (error) end
begin $write(\n);
print_so_mismatch; end
so_mismatch = so_mismatch + 1; endtask
end
inst = inst + 1; task compare_po;
strobe_so = FALSE; begin
end error = FALSE;
if (strobe_po) // compare primary output for (i=1; i <= PO_LEN && error === FALSE;
Figure 1-81 The s27rom_s0.tim.drv.v File (continued)

Full-Scan Tutorial
i=i+1)
begin
if (po_expected[i] !== 1bx && po_expected[i] !== 1bz)
if (po_expected[i] !== sim_response[i]) error = TRUE;
end
end
endtask
task print_po_mismatch;
begin
$write(*** PO mismatch at vector %0d,, vec_print, time %0d\n, $time);
bit_count = 1;
for (i = 1; i <= PO_LEN; i = i + 1)
begin
if (po_expected[i] !== 1bx && po_expected[i] !== 1bz)
begin
if (po_expected[i] !== sim_response[i])
$write(PO #%0d expected = %b simulated = %b\n,
bit_count, po_expected[i], sim_response[i]);
end
bit_count = bit_count + 1;
end
$write(\n);
end
endtask
include s27rom_s0.vector
endmodule
Figure 1-82 The s27rom_s0.tim.drv.v File (end)

Full-Scan Tutorial
The s27rom_s0.vector, files is shown in Figure 1-83.
// FILE : SynTest Verilog vector file

// NAME : s27rom_s0.vector
// TIME : Sun Feb 8 18:03:30 1998 (File continued)
// OPTIONS : -vlog -fscan
initial
begin pi_vector = 11b00000001000;
po_expected = 2b10;
pi_vector = 11b00011110001; si1_vector = 3b100;
po_expected = 2b11; #12000.00;
si1_vector = 3b101;
#12000.00; so1_expected = 3b000;
#7000.00;
#7000.00; pi_vector = 11b01111000100;
po_expected = 2b11;
po_expected = 2b00; #12000.00;
si1_vector = 3b100;
#12000.00; so1_expected = 3b100;
#7000.00;
#7000.00; pi_vector = 11b00100010110;
po_expected = 2b10;
po_expected = 2b00; #12000.00;
si1_vector = 3b100;
#12000.00; so1_expected = 3b000;
#7000.00;
#7000.00; pi_vector = 11b00010011011;
po_expected = 2b10;
po_expected = 2b11; #12000.00;
si1_vector = 3b101;
#12000.00; so1_expected = 3b111;
#7000.00;
#7000.00; pi_vector = 11b01001000100;
po_expected = 2b11;
po_expected = 2b11; #12000.00;
si1_vector = 3b011;
#12000.00; so1_expected = 3b101;
#7000.00;
#7000.00; pi_vector = 11b01101100000;
po_expected = 2b10;
po_expected = 2b01; #12000.00;
si1_vector = 3b011;
#12000.00; so1_expected = 3b101;
#7000.00;
#7000.00; end
Figure 1-83 The s27rom_s0.vector Files

Full-Scan Tutorial
Running a Full-Scan Test Using a Script File
The run_rom script shown in can be used to run the full-scan test including a ripple rom
with the same result as the previous interactive run.
#!/bin/csh -f
# Create Directory Structure
mkdir designs lib 123 fscan dbg
# Compile cell library and netlist

vlogin -lib libsrc/s27lib.v
vlogin -lib libsrc/init_rom.v
vlogin netsrc/s27rom.v -o designs
# expand top module name to flattern circuit
expin s27rom
# Do testability analysis
asic123 -fscan s27rom -o 123/s27rom
# Do full-scan selection
scansel -fscan s27rom
# Do full-scan synthesis and debug

cp s27rom.rom s27rom_s0.rom
scansyn -fscan s27rom
# Output synthesized netlist

lsdb s27rom_s0 -verilog -hierarchy -timescale -o s27rom_s0.v
# Do full-scan ATPG
asicgen -post_fscan s27rom_s0 -weighted 0 -o fscan/s27rom_s0
# Do pattern conversion
ln -s fscan/s27rom_s0.tp .
ln -s fscan/s27rom_s0.int .
tpout -vlog -fscan s27rom_s0
Figure 1-84 Full-Scan Script File - run_rom
The script will:


Full-Scan Tutorial
1. Execute the run_rom script. From the Shell prompt,
run_rom <CR>
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Wed Feb 11 18:42:40 1998
***** Pass One *****

***** Pass Two *****
Created: lib/TX.sdb
Created: lib/IV.sdb
Created: lib/BU.sdb
Created: lib/EO.sdb
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Wed Feb 11 18:42:45 1998
***** Pass One *****

File: libsrc/init_rom.v
Parsed: init_rom (interface only)
***** Pass Two *****
File: libsrc/init_rom.v
Created: lib/init_rom.sdb
=================== VLOGIN V2.0.0 r02 (10/28/97 15:19:49) ===================
TIME: Wed Feb 11 18:42:52 1998
***** Pass One *****

Parsed: s27rom (interface only)
***** Pass Two *****

Full-Scan Tutorial
Created: designs/s27rom.sdb
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Wed Feb 11 18:42:56 1998
Expanded: ./designs/s27rom.x.sdb
* Library Cell FD1

* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
* Library Cell TX
Expanded: ./designs/s27rom.c.sdb
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Wed Feb 11 18:43:02 1998
Options selected: -fscan -o 123/s27rom.123.rpt

Full-Scan Tutorial
Loading memory data from s27rom.rom:

Clock net driving information is saved in 123/s27rom.clk.rpt.
**** The following bus outputs do not have a PULLUP/PULLDOWN/REPEATER :

1) G51
2) G61
3) G71


Full-Scan Tutorial


Logic levels .............................. = 5

Cell elements ............................. = 23

Floating nets ............................. = 0
Floating busses ........................... = 3
Bus holders ............................... = 0

---------- ------- ---------- ----------
MEAN - - 12 -
CPU TIME = 0:00:02
END TIME : Wed Feb 11 18:43:05 1998
=================== SCANSEL V2.0.0 r01 (12/22/97 17:06:40) ===================
TIME: Wed Feb 11 18:43:06 1998

Full-Scan Tutorial
Options selected:
-o s27rom: report file will be saved to s27rom.sel.rpt.
Process s27rom ...

START TIME = Wed Feb 11 18:43:06 1998
Read in and check circuit at TIME Wed Feb 11 18:43:06 1998


End circuit check at TIME Wed Feb 11 18:43:10 1998
CPU TIME = 0:00:02

Scan Count = 3
Memory Count = 3
END TIME = Wed Feb 11 18:43:10 1998
CPU TIME = 0:00:02
=================== SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ===================
TIME: Wed Feb 11 18:43:10 1998
Options selected: -fscan -o s27rom.syn.rpt
- Reading top level netlist ./designs/s27rom.sdb ...
- Reading expanded netlist ./designs/s27rom.x.sdb ...
- Reading cell-level netlist ./designs/s27rom.c.sdb ...



Full-Scan Tutorial

- Copy ./designs/s27rom.sdb => ./scansyn_lib/s27rom_s0.sdb.
- Please read s27rom.syn.log for messages.
- Executing commands in ./scansyn_lib/s27rom_s0.cmd ...
- Generating new cell level pso file s27rom_s0.syn1.pso ...
- Generating new dft file s27rom_s0.dft...

=============================================
=============================================
- Expanding synthesized design s27rom_s0.sdb ...
- Extract scan chain from s27rom_s0 ...

please refer to s27rom_s0.syn.rpt.
======================================================
Report
======================================================
Circuit Name : s27rom

New Circuit Name : s27rom_s0
Synthesis Status
------------------------------------------
DRC Error Status

------------------------------------
Set Error
Found : 0
Fixed : 0
Skiped : 0
Reset Error
Found : 0
Fixed : 0
Skiped : 0
Shift Clock Error

Found : 0
Fixed : 0
Skiped : 0
Capture Clock Error

Full-Scan Tutorial
Found : 0
Fixed : 0
Skiped : 0
Transparent Error
Found : 0
Fixed : 0
Skiped : 0
Bidi Error
Found : 0
Fixed : 0
Skiped : 0
Bus Error
Found : 0
Fixed : 0
Skiped : 0
Cross Coupled Error

Found : 0
Fixed : 0
Skiped : 0
RAM Error
Found : 0
Fixed : 0
Skiped : 0
Tri-State Pad Error

Found : 0
Fixed : 0
Skiped : 0

----------------------------------------------

------------------------------------------
Sequence | STI_TM1
-----------+------------------------------
Normal | 0
Shift | 1
Hold | X
Capture | X
------------------------------------------
Report File : s27rom.syn.rpt

Log File : s27rom.syn.log
======================================================
CPU TIME = 0:00:13
END TIME : Wed Feb 11 18:43:26 1998
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Wed Feb 11 18:43:27 1998

Full-Scan Tutorial


LEVELIZATION END TIME : Wed Feb 11 18:43:29 1998
SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :

success!!

success!!

success!!

success!!

success!!

chain - chain_1 OK.
success!!
---------------------------- CHAIN STATUS ------------------------------

Full-Scan Tutorial
CPU TIME = 0:00:02
END TIME : Wed Feb 11 18:43:29 1998
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Wed Feb 11 18:43:30 1998


LEVELIZATION END TIME : Wed Feb 11 18:43:32 1998
SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :

success!!

success!!

success!!

success!!

success!!

Full-Scan Tutorial
chain - chain_1 OK.

success!!
---------------------------- CHAIN STATUS ------------------------------
CPU TIME = 0:00:02
END TIME : Wed Feb 11 18:43:32 1998
=================== LSDB V2.0.0 r01 (12/23/97 09:14:47) ===================
TIME: Wed Feb 11 18:43:33 1998
Netlist output is saved in s27rom_s0.v.

=================== ASICGEN V2.0.0 r01 (02/17/98 19:06:10) ===================
TIME: Tue Feb 17 21:04:48 1998

-dont_scan_loop -must_scan_only -o fscan/s27rom_s0.rpt
Read constraints from s27rom_s0.dft.....

Force CLK Pattern=0
Read scan specifications from s27rom_s0.dft.....




Full-Scan Tutorial

Select 2 weighted patterns detected 63 faults

Pass 0: CPU TIME = 0:00:02

CPU time: 0:00:00
CPU time: 0:00:00
Before static compact: CPU TIME = 0:00:02 10 vec

Building fault dictionary...
Selecting patterns...
After static compact: CPU TIME = 0:00:02 9 vec
95 Hard detected faults are saved in fscan/s27rom_s0.hdt.
20 Redundant faults are saved in fscan/s27rom_s0.red.
The circuit s27rom_s0.x.sdb has 11 inputs, 3 scan objects, and 2 outputs.




CPU TIME = 0:00:02
END TIME : Tue Feb 17 21:04:57 1998

Full-Scan Tutorial
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 21:06:04 1998
- Processing interface file s27rom_s0.int ...

- Processing DFT file s27rom_s0.dft ...
Scan information :
Shift sequence
CLK = 010
STI_TM1 = 1
Hold sequence
CLK = 0
Capture sequence
CLK = 010
Clock information :
CLK (P) = 010
- Processing test vector file s27rom_s0.tp ...
Verilog vectors were saved in s27rom_s0.vector.

Verilog driver was saved in s27rom_s0.drv.v.

Partial-Scan Tutorials
Product Tutorial
The purpose of this tutorial is to familiarize you with the steps required to process a
Partial-Scan design using SynTest products. You will learn how to:
Synthesize a scan chain into a non-scan design
Extract scan information from a design
To complete the full-scan run, you will perform the following steps and procedures:
Compile a cell library and netlist
Do partial-scan selection
Do partial-scan synthesis and debug
Do scan extraction
Do scan verification
Fault test the design
Logic test the design
This knowledge forms the foundation for the concepts and skills you will need to integrate
the SynTest tools into your work environment.

Assumptions
It is assumed that:
Syntest software has been installed. Further installation and user setup information
can be found in the Quick Installation Procedure in the SynTest Users Guide,
chapter 1.
You have a basic understanding of Unix Workstation and variables.
Tutorials Directory and File Structure
The directories and files needed for the tutorials are shown in Figure 2-1. You will be using
the same design, s27, for all three tutorials.
syntest
tutorials syntest.def
Full Partial
Scan Scan
fscan pscan
libsrc libsrc
netsrc netsrc Boundary
s27lib.v s27lib.v
Full Scan
s27.v Scan s27.v
s27.map s27.map
s27.dft ripple_rom s27.dft bscan
frun s27.psi
libsrc netsrc
netsrc prun
s27lib.v libsrc
ripple_rom.tdl s27.v
example.v
init_rom.v
ripple_rom.map example.pin brun
s27.dft
s27rom.rom example.lib
ripple_rom.pso s27.map
run_rom example.bsc
Figure 2-1 Tutorial Directory and Files Structure

Table 2-1 Tutorial Files and Directories
Files/Directories Function
netsrc Directory containing design.v files (Verilog structural file)
libsrc Directory containing lib.v files (Verilog source file for libraries)
*.dft File containing information that sets condition for testability analysis.
*.map Files describing relationship between generic memory cell and scannable memory
cell.
*.pso File containing a list of cells to be converted to scan, and .psi file information.
*.psi File containing a list of cells to be converted to scan required for partial scan.
*.pin Pin list file used by boundary-scan.
*.lib Cell library file used by boundary-scan.
*.bsc File containing information that sets condition used by boundary-scan.
frun Script file to run a full-scan synthesis.
prun Script file to run a partial-scan synthesis.
brun Script file to run a boundary-scan synthesis.
run_rom Script file to run a full-scan synthesis for the Ripple Rom design.

The s27 Design
The schematic representation of the s27.v design is shown in Figure 2-2. Its Verilog
structural netlist and cell library are shown in Figure 2-3 and Figure 2-4 respectively.
I10
I14 I5
G10 G5
G14 D Q
G0
FD1
I11 I17
I8
CP
I6 G11 G17
G8 G17
G6
D Q
FD1
CP
I15
I9
G15
G9
I12
G1 G12
I13 I7
G13 G7
D Q
FD1
CLK CP
G2
I16
G16
G3
Figure 2-2 The s27.v Design Schematic

module s27 (G17, CLK, G0, G1, G2, G3);

output G17;
input CLK, G0, G1, G2,
G3;
wire G5, G10, G6, G11, G7;
wire G13, G14, G8, G15, G12;
wire G16, G9;
FD1 I5 (.Q(G5), .D(G10), .CP(CLK));
FD1 I6 (.Q(G6), .D(G11), .CP(CLK));
FD1 I7 (.Q(G7), .D(G13), .CP(CLK));
IV I14 (.Z(G14), .A(G0));
IV I17 (.Z(G17), .A(G11));
AN2 I8 (.Z(G8), .A(G14), .B(G6));
OR2 I15 (.Z(G15), .A(G12), .B(G8));
OR2 I16 (.Z(G16), .A(G3), .B(G8));
ND2 I9 (.Z(G9), .A(G16), .B(G15));
NR2 I10 (.Z(G10), .A(G14), .B(G11));
NR2 I11 (.Z(G11), .A(G5), .B(G9));
NR2 I12 (.Z(G12), .A(G1), .B(G7));
NR2 I13 (.Z(G13), .A(G2), .B(G12));
endmodule
Figure 2-3 Verilog Structural Netlist of s27.v Design


module TX (Z, A, E);
output Z;
input A, E;
bufif1 (Z, A, E); (file continued)
endmodule
module IV (Z, A); module EO (Z, A, B);

output Z; output Z;
input A; input A, B;
not (Z, A); xor (Z, A, B);
endmodule endmodule
module BU (Z, A); module MUX21H (Z, A, S, B);
output Z; output Z;
buf (Z, A); wire SN, NA1, NA2;
and (NA1, A, SN);
module AN2 (Z, A, B); and (NA2, B, S);
and (Z, A, B);
output Q, QN;
module ND2 (Z, A, B); input CP, D;
nand (Z, A, B); endmodule
endmodule
module OR2 (Z, A, B); output Q, QN;
or (Z, A, B); and (NA1, D, TEN);
or (Z, NA1, NA2);
module NR2 (Z, A, B); DFF I1 (.Q(Q), .D(Z), .CK(CP));
nor (Z, A, B);
endmodule
Figure 2-4 Cell Library - s27lib.v File

designs, directory used to store design database information
123, directory used to store testability analysis (TurboCheck) output files (asic123)
pscan, directory used to store test pattern generation (TurboScan) results (asicgen)
prompt,
a) cd $SYNTEST
b) source .syntest
Sourcing this file sets Unix variables for SynTest. The .syntest file is shown in
Figure 2-5.
setenv SYNTEST /disk1/usr/home/syntest

set path=(/usr/openwin/bin /usr/openwin/demo/xview $path)
set path=(. $SYNTEST/bin $path)
setenv LD_LIBRARY_PATH /usr/openwin/lib:/usr/lib
setenv SYNTEST_LIB_PATH $SYNTEST
setenv HELPPATH $SYNTEST/help
setenv SYNTEST_TMP .
setenv XKEYSYMDB $SYNTEST/syntest.key
setenv LM_LICENSE_FILE $SYNTEST/.float_lic.dat
Figure 2-5 The .syntest File
2. Change your current working directory to pscan/ (this directory is under $SYNTEST/
tutorial). From the syntest/ directory Shell prompt,
cd tutorials/pscan
3. Examine the design file (netlist and cell library). From the Shell prompt,
more netsrc/s27.v
You will see a Verilog structural netlist file for the s27 design as shown in Figure 2-3.
more libsrc/s27lib.v
You will see a Cell library file for the s27 design as shown in Figure 2-4.

mkdir lib designs 123 pscan dbg
This action will create five directories: lib, designs, 123, pscan, and dbg.
NOTE
Syntest applications such as expin, and are inluded in

Translate the Verilog structural netlist and cell library files (s27.v and s27lib.v) into
Syntest intermediate file (.sdb) using the vlogin translator

primitive.def primitive.def primitive.def

design.vhd design.v design.edif
syntest.def syntest.def edif2tdl

Step 1
Netlist
Translators vhdlin vlogin
& Complier design.tdl
syntest.def
library cells.sdb
design.sdb
Step2
Netlist Linker expin
& Expander
design.x.sdb
design.c.sdb
design.conp
- Note -
The expanded design outputs are s27.c.sdb, s27.x.sdb, and s27.conp.
Figure 2-6 Compiling Process Flow
Translating the Verilog Files
vlogin translates and complies the Verilog .v netlist and library into SynTest intermediate
format (.sdb).
The vlogin utility reads:

Verilog files


1. Convert and compile the input s27.v and s27lib.v files. From the Shell prompt,
This action will generate the design sdb files for each module in the netlist and the cell sdb
files for each cell in the library file.
Since only one module, s27, exists in the netlist s27.v, only one module .sdb of the netlist is
created. The -opath option redirects the compiled .sdb files of the netlist to the designs sub-
directory.
For the part of the translation and compilation of the netlist, The -nf, -drc, and -opath lib
options, which are used for compiling .sdb files of the library typically, are turned on
automatically by setting this option -lib.
The -nf and -drc options disable faulting within the library cells and run design-rule-check
seperately.
The -opath option outputs the .sdb files into the lib sub-directory created for this run. Since
one .sdb file is created for each cell in the library, the directory organization eliminates
cluttering the main design directory with many files.
Detailed information regarding this translator can be found in Command Reference,

Chapter 11 and Creating the SynTest Database and Libraries, Chapter 3.
================= VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ==================
TIME: Thu Jan 8 11:56:46 1998
***** Pass One *****

File: netsrc/s27.v
***** Pass Two *****
File: netsrc/s27.v
Created: lib/TX.sdb
Created: lib/IV.sdb
Created: lib/BU.sdb
Created: lib/EO.sdb
Figure 2-7 Translator vlogin Processing Message
The output files created are:

s27.vlogin.log, contains parsing messages from the netlist translation
s27lib.vlogin.log, contains parsing messages from the library translation
NOTE
If your library has already been compiled, you can
simply create a soft link ("ln -s <library directory> lib")
to the compiled library, and skip the library translation
and compilation step.
The design must be linked and expanded (flattened) before you can perform testability
analysis, synthesis or run the test vector generation programs.
Detailed information regarding this program can be found in Command Reference,

Chapter 11 and Creating the Syntest Database and Libraries, Chapter3.
expin s27
This command execution will create three new design files in the same directory as the
specified source file, or in the directory specified with the -opath option. The files are:
s27.c.sdb, contains design linked and flattened down to the library cell level. This
file will be used by the testability synthesis application (scansyn)
s27.x.sdb, contains the design linked and flattened down to the Syntest primitive
level. This file will be used by the testability analysis application and test vectors
s27.conp, contains design connectivity information used to link the .c.sdb to .x.sdb
files. If missing, errors may occur.
============= EXPIN V2.0.0 r01 (07/14/97 09:59:05) =============
TIME: Thu Jan 8 12:15:08 1998
* Library Cell FD1
* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
In this section, you will use the testability analysis program, asic123 (TurboCheck), to do
the following:
Determine the controllability and observability for the design using full-scan

The testability analysis flow is shown in Figure 2-9.
s27.x.sdb
s27.psi (optional, required only for partial-scan)
(optional) s27.conp
s27.dft (optional file)
asic123
s27.clk.rpt
s27.123.rpt
Figure 2-9 Testability Analysis Flow
The utility asic123 reads:

the template.dft file that contains logic value and condition settings (optional)
can be used. It is not available asic123 will automatically determine optimum
NOTE
The .dft file is SynTest template file used to set logic values at primary inputs and memory
elements for the testability analysis program to generate more accurate feedback. The
conditions set in this file can be modified to check problems in normal mode
(before synthesis), shift, hold, and capture mode.
The asic123 program searches for this file by default. This program also reads a .def file for
older releases. The .dft file is now used in place of the .def file.
See more details of a .dft file in File Reference & Examples chapter 10.
1. Observe the s27.dft file. From the shell prompt,
more s27.dft
The user-defined s27.dft is shown in Figure 2-10.

%ATPG_CONSTRAINTS
(File continued)
{
%ATPG_MODE "PARTIAL_SCAN" // Define a scan chain with type MDFF and name chain_1
%CLOCK CLK = 010; {
} %SCAN_CLOCK_1
} {
%SEQUENCE shift_seq /* The port providing shift clock */
{ %CLOCK = CLK;
%FORCE CLK = 010; %GLOBAL_CLOCK = CLK;
%SEQUENCE hold_seq {
{ %FILE_NAME = "s27.sel1.pso";
%FORCE CLK = 000; }
%CYCLE_LENGTH = 1; %SCAN_PORT
} {
%SEQUENCE capture_seq /* scan data is shifted thru these two ports */
} }
%READ_MAP %SCAN_INSTRUCTION
{ {
%FILE_NAME = "s27.map"; %INSTRUCTION = instruction1;
} }
}
{ %SCAN_DECODER
%MODE = "scan"; {
%SHIFT = shift_seq; %CONTROL_PORT_1 = STI_TM1;
%HOLD = hold_seq; %CONTROL_PORT_2 = STI_TM2;
%CAPTURE = capture_seq; }
}
Figure 2-10 The User-defined s27.dft
asic123 -pscan s27 -o 123/s27
name s27. The processing messages generated are saved to the report file, s27.123.rpt,
shown in Figure 2-11 to Figure 2-14.
NOTE
If you run several iterations of asic123 using different
options, you can store them using different target
filenames or subdirectories.
Detailed information regarding Pioneer, asic123, can be

found in Using Pioneer Testability Analysis Tools,
chapter 1.
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Tue Feb 17 18:38:25 1998
Options selected: -pscan -o 123/s27.123.rpt
Read constraints from s27.dft.....

FORCE CLK = 0
Figure 2-11 Testability Analysis Processing Messages - Report File
Reading scan specification input file s27.psi ...
**** The following dominating nodes cannot be set to 0 (~0) or 1 (~1) :

1) ~0 ~1 Q I5
2) ~0 Z I17
**** The following flip-flops cannot be set to 0 (~0) or 1 (~1), observed (~B)
or clock port stuck at 0/1 (~P) :
1) ~0 ~1 ~p Q I5.I1
2) ~p Q I6.I1
3) ~p Q I7.I1
**** The following dominating nodes cannot be observed :

1) Z I13
2) Z I10
3) Z I9


Logic levels .............................. = 5

Cell elements ............................. = 13

Floating nets ............................. = 0
Floating busses ........................... = 0
Bus holders ............................... = 0

---------- ------- ---------- ----------
MEAN - - 0 -
CPU TIME = 0:00:02
END TIME : Tue Feb 17 18:38:32 1998

s27.123.rpt, file containing processing messages and a testability analysis report
s27.clk.rpt, clock tree information report file
The s27.clk.rpt is shown in Figure 2-15.
**** Order: Type Root_Clock -> Local_Clock Object ****

Figure 2-15 The Clock Report - s27.clk.rpt
file. This file, created by scansel, determines the scan order for scan chains. The scan
selection flow is shown in Figure 2-16.
s27.x.sdb
s27.psi
s27.c.sdb
scansel
s27.sel1.pso
s27.sel.rpt
Figure 2-16 Scan Selection Flow

Figure 2-17 shows the content of the .psi file. The file is used in scan selection to select the
user-defined MUST_SCAN memory cells as scannable elements and leave the
DONT_SCAN cells as non-scannable ones. When scansel detects the .psi file, it genreates a
.pso file based on .psi file for scan synthesis and debugging.
DONT_SCAN I5.I1;
MUST_SCAN I6.I1; Set the memory element I5.I1 as
MUST_SCAN I7.I1;
DONT_SCAN.
Figure 2-17 The User-defined .psi File
scansel s27
======== SCANSEL V2.0.0 r01 (12/22/97 17:06:40) =========
Copyright (c), 1991-1996, SynTest Technologies, Inc. All rights ( File continued )
reserved.
TIME: Sun Feb 8 17:46:45 1998

CPU TIME = 0:00:02
Options selected:
Start circuit graph creation at TIME Sun Feb 8 17:46:49 1998
-acyclic: Break Self & Global Loops. 2 memory elements are specified as MUST_SCAN
End circuit graph creation at TIME Sun Feb 8 17:46:49 1998
Process s27 ...
CPU TIME = 0:00:00
START TIME = Sun Feb 8 17:46:45 1998
Start circuit graph reduction at TIME Sun Feb 8 17:46:49 1998
Read in and check circuit at TIME Sun Feb 8 17:46:45 1998
Reading scan file - s27.psi ... End circuit graph reduction at TIME Sun Feb 8 17:46:49 1998
CPU TIME = 0:00:00

Start checking SPS property ...
Circuit s27 is a SPS
Start sps_balance at TIME Sun Feb 8 17:46:49 1998
Number of accessible nets ......... = 21 End sps_balance at TIME Sun Feb 8 17:46:49 1998
CPU TIME = 0:00:00
Max sequential depth = 0
Scan count = 2
Total accessible memory elements .. = 3 Memory count = 3
Number of inaccessible latches .... = 0 WARNING: Could not break all self & global loops due to
DONT_SCAN constraint.
END TIME = Sun Feb 8 17:46:49 1998
End circuit check at TIME Sun Feb 8 17:46:49 1998
CPU TIME = 0:00:02
Figure 2-18 Scansel Proccessing Messages - s27.sel.rpt File
s27.sel1.pso, file produced by the -pscan option containing a list of flip-flops from
the design (with netlist default order)
s27.sel.rpt, processing messages report file
NOTE
The default ordering of scan elements is organized by
the hierarchical order of modules in your design.You
can rearrange the order by copying the .pso file to a
different name, then reorder the flip-flops in the
appropriate ordering. This is usually
sufficient for most purposes.
The s27.sel1.pso is shown in Figure 2-19.
DONT_SCAN I5;
MUST_SCAN 17 I6; The elements which are set to
MUST_SCAN 24 I7;
be DONT_SCAN
Figure 2-19 s27.sel1.pso File
The purpose of scan synthesis is to replace non-scan flip flops with scan flip flops.

Scan debugging

a .pso, scan element list file created by scansel or the designer
a .dft file containing design specific information (see Figure 2-10, this file can be
modified)
a .map file containing mapping information between generic and scanable memory
cell. The s27.map is shown in Figure 2-20.
%MAP_SCAN MDFF /* Mapping for chain type == MDFF */

{
/* Replace all FD1 scan instance with FD1S */
%MAP_CELL FD1 => FD1S
{
%SCAN_PORT %SYSTEM_IN => D;
%SCAN_PORT %SCAN_IN => TI;
%SCAN_PORT %SCAN_OUT => Q;
%SCAN_SELECT_1 %SELECT => TE;
%SCAN_CLOCK_1 %CLOCK => CP;
}
}
%REPAIR_CELL
{
%CELL BUF BU;
%CELL INV IV;
%CELL AND AN2;
%CELL NAND ND2;
%CELL OR OR2;
%CELL NOR NR2;
%CELL XOR EO;
%CELL TBUF TX
{
%ENABLE = E;
}
%CELL MUX MUX21H
{
%DATA_0 = A;
%DATA_1 = B;
%SELECT = S;
}
}
Figure 2-20 The s27.map File
1. Run scan synthesis. From the Shell prompt,
scansyn -pscan s27
The processing messages (or the s27.syn.rpt report file) are shown in Figure 2-21.

report and log files (s27.syn.rpt, s27.syn.log). Actually, s27.syn.log contains three
log files: scan_decoder.vlogin.log, s27_s0.expin.log, and s27_s0.syn.rpt.
scansyn_lib sub-directory containing a new version of the design files (s27_s0.*)

that can be translated to VHDL, Edif, and Verilog format by using the lsdb
translator.
s27_s0.dft, the modified .dft file for running scandbg, asicgen, and tpout to
s27_s0.syn1.pso and s27_s0.ext1.pso, which are generated by scansyn and scansyn
-extract_only (automatically) separately, containing a list of the scan flip-flops.
(Messages continued)
============= SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ============ DRC Error Status
------------------------------------
Copyright (c), 1991-1997, SynTest Technologies, Inc. All rights reserved. Set Error
Found : 0
TIME: Sun Feb 8 17:49:23 1998 Fixed : 0
Skiped : 0
Options selected: -pscan -o s27.syn.rpt
Reset Error
Found : 0
- Reading top level netlist ./designs/s27.sdb ... Fixed : 0
Skiped : 0
Shift Clock Error
- Reading cell-level netlist ./designs/s27.c.sdb ... Found : 0
Fixed : 0
- Setting up hierarchical information ... Skiped : 0
Capture Clock Error
- Create directory ./scansyn_lib. Found : 0
- Replace 2 memory elements to scan elements. Fixed : 0
- Insert 0 delay cells. Skiped : 0
Transparent Error
- Start Hierarchical Repair Process ... Found : 0
Fixed : 0
Skiped : 0
Bidi Error
- Start Building Scan Decoder ... Found : 0
Fixed : 0
- Start executing synthesis commands ... Skiped : 0
- Please read s27.syn.log for messages. Bus Error
Found : 0
- Executing commands in ./scansyn_lib/s27_s0.cmd ... Fixed : 0
Skiped : 0
Cross Coupled Error
- Generating new dft file s27_s0.dft... Found : 0
- In %SEQUENCE shift_seq, Add %FORCE STI_TM1 = 111; Fixed : 0
Skiped : 0
=============================================
Object Error Status after Hierarchical Repair RAM Error
============================================= Found : 0
- No error found after repair. Fixed : 0
Skiped : 0
Tri-State Pad Error
- Extract scan chain from s27_s0 ... Found : 0
please refer to s27_s0.syn.rpt. Fixed : 0
Skiped : 0
====================================================== Scan Decoder Loading Information

Report ----------------------------------------------
====================================================== SCANSYN_SCAN uses BUF(BU) to drive 2 gates.
Circuit Name : s27
New Circuit Name : s27_s0 Scan Decoder Control Table
Scan Decoder Cell : SCAN_DECODER_CLASS ------------------------------------------
Scan In Port Name : Chain 1 -> SCAN_IN Sequence | STI_TM1
Scan Out Port Name : Chain 1 -> SCAN_OUT -----------+------------------------------
Added Control Port : STI_TM1 Normal | 0
Shift | 1
Synthesis Status Hold | X
------------------------------------------ Capture | X
Replaced Memory Cells : 2 ------------------------------------------
DRC Error Status Log File : s27.syn.log
------------------------------------ ===========================================
Set Error
Found : 0 CPU TIME = 0:00:13
Fixed : 0
Skiped : 0 END TIME : Sun Feb 8 17:49:40 1998
Figure 2-21 scansyn Processing Messages - s27.syn.rpt File
The s27.syn.log file is shown in Figure 2-22 and Figure 2-23.

=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Sun Feb 8 17:49:27 1998

***** Pass One *****
***** Pass Two *****
--- run ./scansyn_lib/s27_s0.cmd ----

--- /home/users/barbara/syntest/bin/expin s27_s0.sdb ----
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Sun Feb 8 17:49:34 1998
Expanded: ./scansyn_lib/s27_s0.x.sdb
* Library Cell FD1

* Library Cell FD1S
* Library Cell IV
* Library Cell AN2
* Library Cell OR2
* Library Cell ND2
* Library Cell NR2
* Library Cell BU
Expanded: ./scansyn_lib/s27_s0.c.sdb
=================== SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ===================

TIME: Sun Feb 8 17:49:38 1998
Options selected: -fscan -extract_only -o s27_s0.syn.rpt
- Reading top level netlist ./scansyn_lib/s27_s0.sdb ...
- Reading expanded netlist ./scansyn_lib/s27_s0.x.sdb ...

---==========--- Scan Extraction ---==========---

------=======================================================------
Figure 2-22 The s27.syn.log file
Initializing ...

Successfully!

2 scan cells were written into file s27_s0.ext1.pso.

CPU TIME = 0:00:02
END TIME : Sun Feb 8 17:49:40 1998
Figure 2-23 The s27.syn.log file (continued)
Beside replacing non-scan flip-flops, and latches in the design with their scannable
Running Scan Debug
2. Run scan debug. From the Shell prompt,
a) scandbg -flush_test 10110 s27_s0 -o dbg/s27_s0.1
b) scandbg -flush_test 01001 s27_s0 -o dbg/s27_s0.2
The outputs report files created under the sub-directory dbg/, s27_s0.1.dbg.rpt,
s27_s0.2.dbg.rpt, s27_s0.1.dbg.tp, and s27_s0.2.dbg.tp are shown in Figure 2-24, Figure 2-
25, and Figure 2-26, respectively.
========== SCANDBG V2.0.0 r01 (11/07/97 11:24:04)============
SHIFT :
TIME: Sun Feb 8 17:52:12 1998

success!!
success!!
success!!
chain - chain_1 OK.
success!!

---------------------------- CHAIN STATUS -----------------------------
Total inaccessible memory elements = 0 -


Scan-Chain 1 - chain_1: CPU TIME = 0:00:02

SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT END TIME : Sun Feb 8 17:52:17 1998
CLOCK : CLK
=========== SCANDBG V2.0.0 r01 (11/07/97 11:24:04)===========
SHIFT :
TIME: Sun Feb 8 17:52:39 1998

success!!
success!!
success!!
chain - chain_1 OK.
success!!

---------------------------- CHAIN STATUS -----------------------------
Total inaccessible memory elements = 0 -


Scan-Chain 1 - chain_1: CPU TIME = 0:00:02

SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT END TIME : Sun Feb 8 17:52:44 1998
CLOCK : CLK
S S
SS C SS C
TC A TC A
IA N IA N
_N _ _N _
C T_GO C T_GO
LGGGGMI1U LGGGGMI1U
K01231N7T K01231N7T
-STEM- -STEM-
1 LXXXXHHXX 1 LXXXXHLXX
2 HXXXXHHXX 2 HXXXXHLXX
3 LXXXXHHXX 3 LXXXXHLXX
4 LXXXXHLXX 4 LXXXXHHXX
5 HXXXXHL++ 5 HXXXXHHX-
6 LXXXXHL++ 6 LXXXXHHX-
7 LXXXXHH++ 7 LXXXXHLX-
8 HXXXXHHX- 8 HXXXXHL++
9 LXXXXHHX- 9 LXXXXHL++
10 LXXXXHHX- 10 LXXXXHL++
11 HXXXXHHX+ 11 HXXXXHLX-
12 LXXXXHHX+ 12 LXXXXHLX-
s27_s0.1.dbg.tp s27_s0.2.dbg.tp
Figure 2-26 The .tp Files Generated by scandbg
Figure 2-27 illustrates the s27 design flow during design synthesis, debug, and netlist
s27.x.sdb
s27.dft
s27.c.sdb
s27.map
s27.sel1.pso
scansyn Synthesize
scansyn_lib
s27_s0.x.sdb
s27_s0.c.sdb
s27.syn.rpt
s27_s0.sdb
s27.syn.log
s27_s0.conp
s27_s0.syn.rpt
s27_s0.cmd
s27_s0.syn1.pso
scan_decoder.v
Debug scandbg
lsdb Netlist
Conversion
s27_s0.dbg.rpt
s27_s0.vhd
s27_s0.v
s27_s0.edif
use the lsdb utility to translate the sdb files created by scansyn (s27_s0.x.sdb).
1. Convert the s27 scanable to a Verilog netlist. From the Shell prompt,
design hierarchy.
purposes.
The -o option directs the output to the filename s27_s0.v
=================== LSDB V2.0.0 r01 (12/23/97 09:14:47) ===================

TIME: Sun Feb 8 17:56:33 1998
Figure 2-28 The lsdb Processing Messages
2. Display the s27_s0.v file. From the Shell prompt,
more s27_s0.v
The Verilog netlist is shown in Figure 2-29.
// File : s27_s0.v
// Created: Sun Feb 8 17:56:36 1998
// sdb verison 230
//

module s27_s0 ( G17 , SCAN_OUT , G0 , G1 ,
G2 , G3 , SCAN_IN , CLK ,
STI_TM1 ) ;
input G0 , G1 , G2 , G3 ,
SCAN_IN , CLK , STI_TM1 ;
wire G10 , G11 , G12 , G5 ,
G13 , G6 , G14 , G7 ,
G15 , G8 , G9 , G16 ;
FD1 I5 ( .CP ( CLK ) , .D ( G10 ) , .Q ( G5 ) ) ;
FD1S I6 ( .CP ( CLK ) , .D ( G11 ) , .Q ( G6 ) ,
.TE ( I6_TE ) , .TI ( SCAN_IN ) ) ;
FD1S I7 ( .CP ( CLK ) , .D ( G13 ) , .Q ( G7 ) ,
.TE ( I6_TE ) , .TI ( G6 ) ) ;
IV I14 ( .A ( G0 ) , .Z ( G14 ) ) ;
IV I17 ( .A ( G11 ) , .Z ( G17 ) ) ;
AN2 I8 ( .A ( G14 ) , .B ( G6 ) , .Z ( G8 ) ) ;
OR2 I15 ( .A ( G12 ) , .B ( G8 ) , .Z ( G15 ) ) ;
OR2 I16 ( .A ( G3 ) , .B ( G8 ) , .Z ( G16 ) ) ;
ND2 I9 ( .A ( G16 ) , .B ( G15 ) , .Z ( G9 ) ) ;
NR2 I10 ( .A ( G14 ) , .B ( G11 ) , .Z ( G10 ) ) ;
NR2 I11 ( .A ( G5 ) , .B ( G9 ) , .Z ( G11 ) ) ;
NR2 I12 ( .A ( G1 ) , .B ( G7 ) , .Z ( G12 ) ) ;
NR2 I13 ( .A ( G2 ) , .B ( G12 ) , .Z ( G13 ) ) ;
SCAN_DECODER_CLASS SCAN_DECODER ( .CTRL1 ( STI_TM1 ) , .SCANSYN_SCAN ( I6_TE ) ) ;
endmodule
// File : s27_s0.v
// Created: Sun Feb 8 17:56:36 1998
// sdb verison 230
//

input CTRL1 ;
endmodule
Figure 2-29 The converted Verilog File - s27_s0.v
Use the test pattern generation utility, asicgen (TurboScan), to generate the test
patterns for the s27 design
Verilog test-bench
s27_s0.x.sdb file, the design compiled and flattened to the SynTest primitive level
s27_s0.dft, file contains an entry regarding "%ATPG_CONSTRAINTS" which
s27_s0.x.sdb
s27_s0.dft
asicgen
s27_s0.rpt
s27_s0.tp
s27_s0.int
s27_s0.hdt
s27_s0.pso
s27_s0.red
s27_s0.udt
The s27_s0.dft file is shown in Figure 2-31.
( File continued)
// File : s27_s0.dft
%SCAN_PORT
{
/* scan data is shifted thru these two ports */
// Scan instruction sequence %SCAN_IN = SCAN_IN;
%SEQUENCE shift_seq %SCAN_OUT = SCAN_OUT;
{ %DEFAULT = SCAN_;
%FORCE CLK = 010; }
%FORCE STI_TM1 = 111; %SCAN_CLOCK_1
//%CYCLE_LENGTH = 3; <---- Now you dont {
need specify this construct. /* The port providing shift clock */
} %CLOCK = CLK;
%SEQUENCE hold_seq %GLOBAL_CLOCK = CLK;
{ }
%FORCE CLK = 000; %SCAN_INSTANCES_FILE
} {
%SEQUENCE capture_seq %FILE_NAME = s27_s0.ext1.pso;
{ }
%FORCE CLK = 010; %SCAN_INSTRUCTION
} {
%INSTRUCTION = instruction1;
}
// Instruction }
{
%MODE = scan; // Test Generation Constraints
%SHIFT = shift_seq; // For full-scan test pattern generation
%HOLD = hold_seq; %ATPG_CONSTRAINTS
%CAPTURE = capture_seq; {
} %ATPG_MODE PARTIAL_SCAN
{
%CLOCK CLK = 010;
// Read Mapping_cell File }
%READ_MAP }
{
%FILE_NAME = s27.map;
} // Scan Decoder
%SCAN_DECODER
{
// Connect Scan Chain %CONTROL_PORT_1 = STI_TM1;
// Define a scan chain with type MDFF and name chain_1 %CONTROL_PORT_2 = STI_TM2;
%CONNECT_SCAN chain_1 MDFF }
{
Figure 2-31 The s27_s0.dft File
1. Generate the test pattern. From the Shell prompt,
asicgen -post_pscan s27_s0 -o pscan/s27_s0
The -post_pscan option sets all defaults options, such like -dont_scan_loop, for partial-
scan test pattern generation.
The -o option redirects the output to the pscan sub-directory.
The asicgen processing messages are shown in Figure 2-32 to Figure 2-34.
=================== ASICGEN V2.0.0 r01 (02/17/98 18:39:02) ===================
TIME: Tue Feb 17 19:08:03 1998
Options selected: -post_pscan -pscan -atpg -limit 10000 -multi_cycle

-dont_scan_loop -must_scan_only -o pscan/s27_s0.rpt

Clock CLK Pattern=010
Checking force values .....
Checking black boxes .....
Checking bypass .....
Checking levelization type ..... LAT count: 0
DFF index: 28
Checking arguments ..... DFF count: 3
Calculating port count ..... DELAY index: 31
PI 7:PO 2: IO 0 DELAY count: 0
MEMORY index: 31
Initializing data structure for drc ..... MEMORY count: 0
RAM index: 31
Checking design rules ..... RAM count: 0
Pre-check sdb consistency ..... ROM index: 31
Change wire to wand ..... ROM count: 0
Fix common net links ..... FIFO index: 31
Fix synthesized cross-couple & delay ..... FIFO count: 0
Check bidirect ports ..... RAM2 index: 31
Fix PI links ..... RAM2 count: 0
Fix PO links .....
Sort PI nets ..... Sorting object table .....
Sort PO nets .....
Fix object-out-net links ..... Initializing memory table .....
Handle black-box bypass module ..... Sorting object flag table .....
Tie unconnected input nodes .....
Remove inaccessible objects .....
Check 1 o.k.
Check 2 o.k. Doing force values simulation .....
[ Now set SDB_LVL_KEEP_ALL_OBJS.. ]
Breaking combinational loop .....
[ Now removing inaccessible objects.. ] Allocate and initialize table .....
Compute object fanout count .....
[ Final reporting... ]
Reduce object fanout count .....
Obj count : 31 schedule all levelization loader .....
Access objs: 28 Schedule POs
Check sdb consistency ..... Schedule PPOs
Schedule valued-objects
Ordering object table ..... Schedule DESIGN_CLASS
Target obj count: 31 Schedule Dead-end obj
Ordered obj count: 31 schedule all levelized comb loader .....
Q obj index: 28
Q obj count: 3 Compute object fanin count .....
LAT index: 28
Figure 2-32 asicgen Processing Messages - s27_s0.rpt
Find levelized objects ..... ( File continued )

schedule all levelization driver .....
Schedule valued-objects
Schedule COMMON NETS
Schedule PIs **** CIRCUIT STATISTICS ****
Schedule PPIs
Schedule DESIGN_CLASS Number of input pins .............. = 7
Current queue events: 5 Number of output pins ............. = 2
schedule all levelized comb driver ..... Number of bidirectional pins ...... = 0
Total accessible obj : 28 Number of accessible objects ...... = 28
Current levelized obj: 28 Number of accessible nets ......... = 35
Current level count : 7 Number of delay objects ........... = 0
Target Combinational loops ..... Number of accessible flip-flops ... = 3
Initialize graph tab and var Number of accessible latches ...... = 0
Resorting SDB after levelization ..... Total accessible memory elements .. = 3
Reordering object table .....
Target obj count: 31 Number of inaccessible flip-flops . = 0
Ordered obj count: 28 Number of inaccessible latches .... = 0
Inacces-obj count: 3 Number of inaccessible RAMs/ROMs .. = 0
Q obj index: 25 Total inaccessible memory elements = 0
Q obj count: 3
LAT index: 25 **** The following statistics is for SDB before 1) and after 2) prun-
LAT count: 0 ing :
DFF index: 25 1) 28 objects, 39 nets, 3 memory elements
DFF count: 3 2) 28 objects, 39 nets, 3 memory elements
DELAY index: 28
DELAY count: 0
MEMORY index: 28 LEVELIZATION CPU TIME = 0:00:02
MEMORY count: 0 LEVELIZATION END TIME : Tue Feb 17 19:08:07 1998
RAM index: 28
RAM count: 0 * Scanning only MUST_SCAN objects
ROM index: 28 * (No automatic selection made)
ROM count: 0 * TARGET_SCAN_COUNT 2;
FIFO index: 28 INTERFACE==> pi 7, bidi 0, scan 2, po 2
FIFO count: 0 56 collapsed and 108 uncollapsed faults
RAM2 index: 28 fsim: Weighted pattern [ 1] ... 6 ( 10.71%) det.
RAM2 count: 0 fsim: Weighted pattern [ 2] ... 19 ( 33.93%) det.
fsim: Weighted pattern [ 3] ... 19 ( 33.93%) det.
Resorting object table ..... ..........
Sorting object flag table ..... fsim: Weighted pattern [ 1169] ... 54 ( 96.43%) det.
Reordering memory table ..... atpg: Pass 1 [ 15]
54 ( 96%) detected. tp=780
Setup levelized SDB ..... 0 redundant.
Final obj count: 31 Number of backtracks = 72.
Final net count: 39 atpg: Pass 1 [ 16]
54 ( 96%) detected. tp=780
Final check SDB consistency ..... 0 redundant.
Number of backtracks = 51.
CPU TIME = 0:00:07
END TIME : Tue Feb 17 19:08:29 1998
* TARGET_SCAN_COUNT 3;
Selecting partial-scan objects ...
Select 2 scan elements
**** Incremental Partial Scan has selected maximal number of scan elements. ****
54 Hard detected faults are saved in pscan/s27_s0.hdt.
2 Potentially detected faults are saved in pscan/s27_s0.pdt.
2 partial-scan objects are saved in pscan/s27_s0.pso.
This circuit has 780 test patterns and 2 scan_ins and 2 scan_outs,
and contains 56 faults of which


and contains 108 UNCOLLAPSED faults of which


Total number of backtracks = 123.

CPU TIME = 0:00:07
END TIME : Tue Feb 17 19:08:30 1998

s27_s0.rpt, fault coverage report file
s27_s0.tp, test pattern file
s27_s0.hdt, hard-detected faults
s27_s0.udt, undetected faults
s27_s0.red, redundant or untestable faults file
s27_s0.int, top module pin interface file
s27_s0.pso, partial-scan object file
S
SS C .............................................-
TC AII 747 N S LLLHHLHHL--+-
IA N67 748 N S LLHHLLHLH--+-
_N ___ 749 N S HLHHLLHLH--+-
C T_ GOPP 750 N S LLHHLLHLH--+-
LGGGGMIII1UPP 751 N S LHHLHLLHH+-+-
K01231N677TOO 752 N S HHHLHLLHH++-+
-STEM- 753 N S LHHLHLLHH++-+
1 I S LLHHHHLHHX+XX 754 N S LHLLLLHHH++-+
2 N S HLHHHHLHH++-+ 755 N S HHLLLLHHH++-+
3 N S LLHHHHLHH++-+ 756 N S LHLLLLHHH++-+
4 N S LHLLLLLHH++-+ 757 N S LHLLLHLHH++-+
5 N S HHLLLLLHH++-+ 758 N S HHLLLHLHH+---
6 N S LHLLLLLHH++-+ 759 N S LHLLLHLHH+---
7 N S LHLLHHLHH++-+ 760 N S LHHLHHHHH+---
8 N S HHLLHHLHH+--- 761 N S HHHLHHHHH+-+-
9 N S LHLLHHLHH+--- 762 N S LHHLHHHHH+-+-
10 N S LLHHLHHLL+--- 763 N S LLHHLHHLL+-+-
11 N S HLHHLHHLL--+- 764 N S HLHHLHHLL-+++
12 N S LLHHLHHLL--+- 765 N S LLHHLHHLL-+++
13 N S LLLLHHHLH--+- 766 N S LHLHHHLHH++++
14 N S HLLLHHHLH-+++ 767 N S HHLHHHLHH++-+
15 N S LLLLHHHLH-+++ 768 N S LHLHHHLHH++-+
16 N S LLLLLLLLH-+++ 769 N S LLHLLHLLH++-+
17 N S HLLLLLLLH-+++ 770 N S HLHLLHLLH+---
18 N S LLLLLLLLH-+++ 771 N S LLHLLHLLH+---
19 N S LLLLHLLLH-+++ 772 N S LLLHLLHHL+---
20 N S HLLLHLLLH-+++ 773 N S HLLHLLHHL+---
21 N S LLLLHLLLH-+++ 774 N S LLLHLLHHL+---
22 N S LHHHHHLLL++++ 775 N S LHHHLLHLH+---
23 N S HHHHHHLLL++-+ 776 N S HHHHLLHLH+---
24 N S LHHHHHLLL++-+ 777 N S LHHHLLHLH+---
25 N S HLLHHHLHL---- 778 N S LLLLLHHLL+---
..............................................- 779 N S HLLLLHHLL--+-
Figure 2-35 The s27_s0.tp File
The s27_s0.hdt, s27_s0.red , s27_s0.udt, s27_s0.int, and s27_s0.pso files are shown in
Figure 2-36.
/0 /1 CLK (file continued)

/0 /1 G0 MUST_SCAN I6;
/0 /1 G1 I CLK MUST_SCAN I7;
/0 /1 G2 /0 /1 Z I8 I G0 DONT_SCAN 13 ;
/0 /1 G3 /1 A I8 I G1 SELECTED_SCAN
/0 /1 STI_TM1 /1 B I8 I G2 I6
/0 /1 SCAN_IN /1 Z I15 I G3 I7;
/0 /1 Q I5 /0 A I15 I STI_TM1
/0 /1 D I6 /0 B I15 I SCAN_IN
S I6 I1 The s27_s0.pso File
/0 /1 CP I6 /0 B I16
/0 /1 Q I6 /0 Z I9 S I7 I1
/0 /1 TE I6 /0 /1 Z I10 O G17
/0 /1 TI I7 /0 A I10 O SCAN_OUT
/0 /1 CP I7 /0 B I10
/0 /1 Q I7 /1 Z I11 The s27_s0.int File
/0 /1 TE I7 /1 Z I12
/0 /1 Z I17 /0 B I12
/0 /1 Z I8 /1 Z I13
/0 B I13
/0 /1 Z
The s27_s0.hdt File SCANSYN_BUF_0
(file continued)
# Untested clock/enable faults #Faults were Ignored or Tied to VCC/GND
below: /0 CLK
/0 /1 CP I6 /0 CP I5 /1 A I8
/0 /1 CP I7 /1 B I8
#Faults were Uncontrollable /1 Z I15
/0 /1 Q I5 /0 A I15
/1 Z I17 /0 B I15
The s27_s0.udt File /0 B I16
#Faults were Blocked (Unobservable) /0 Z I9
/1 CLK /0 /1 Z I10
/0 /1 G0 /0 A I10
/0 /1 G1 /0 B I10
/0 /1 G2 /1 Z I12
/0 /1 G3 /0 B I12
/0 /1 STI_TM1 /1 Z I13
/0 /1 SCAN_IN /0 B I13
/1 CP I5
/0 /1 D I6 #Faults were due to circuit design
/0 /1 Q I6 /0 /1 Q I7
/0 /1 TE I6 /0 Z I17
/0 /1 TI I7 /1 Z I11
/0 /1 TE I7 /0 /1 Z SCANSYN_BUF_0
/0 /1 Z I8
The s27_s0.red File
Figure 2-36 The s27_s0.hdt, s27_s0.red , s27_s0.udt, s27_s0.int, and s27_s0.pso files
The test pattern files created by asicgen are stored in the pscan sub-directory. Before
a) ln -s pscan/s27_s0.tp .
b) ln -s pscan/s27_s0.int .
tpout -vlog -pscan s27_s0

The -pscan option specifies translation of partial-scan vectors.
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 19:25:54 1998

Shift sequence
OPTIONS : -vlog -pscan CLK = 010
STI_TM1 = 1
Hold sequence
Number of input pins = 7 CLK = 0
Number of output pins = 2 Capture sequence
Number of scan instances = 2 CLK = 010
- Processing DFT file s27_s0.dft ... Clock information :
Scan information : CLK (P) = 010
Chain 1, Length is 2 - Processing test vector file s27_s0.tp ...

Scan-out pin = SCAN_OUT Number of vectors = 780
(File continued) Verilog vectors were saved in s27_s0.vector.

Figure 2-37 tpout Processing Messages - s27_s0.tpout.rpt File

a report file, s27_s0.tpout.rpt file
a Verilog timing driver file, s27_s0.drv.v
a Verilog pattern file, s27_s0.vector
The Verilog driver file, s27_s0.drv.v, controls a Verilog simulation of the full set of patterns
generated by asicgen. It reads the scan test data and compares the expected data both from
s27_s0.vector file. This verification process in Verilog can be used to completely verify the
pattern set before taping out the design. The s27_s0.drv.v is shown in Figure 2-38, Figure 2-
(file continued)
// FILE : SynTest Verilog driver file
// NAME : s27_s0.drv.v
// TIME : Tue Feb 17 19:25:54 1998 wire STI_STI_TM1 ;
// OPTIONS : -vlog -pscan wire STI_SCAN_IN ;
//-------------------------------------------------------
timescale 1ns / 10ps //-- Call module --
//-------------------------------------------------------
define TRUE 1 s27_s0 s27_s0_inst (
define FALSE 0 .G17 ( STI_G17 ) ,
.SCAN_OUT ( STI_SCAN_OUT ) ,
module s27_s0_top ; .CLK ( STI_CLK ) ,
//------------------------------------------------------- .G0 ( STI_G0 ) ,
//-- Declare parameters -- .G1 ( STI_G1 ) ,
//------------------------------------------------------- .G2 ( STI_G2 ) ,
parameter .G3 ( STI_G3 ) ,
I_TYPE = 1, .STI_TM1 ( STI_STI_TM1 ) ,
N_TYPE = 2, .SCAN_IN ( STI_SCAN_IN ) );
O_TYPE = 3, //-------------------------------------------------------
SHIFT_PHASE = 3, //-- Init variables --
SHIFT_CYCLE = 2, //-------------------------------------------------------
HOLD_PHASE = 3, task init_variables;
PI_LEN = 7, begin
PO_LEN = 2, shift_1 = 3b010;
SO_LEN = 1, scan_out[1] = 2;
CHAIN1_LEN = 2, strobe_so = FALSE;
NUM_VEC = 780; strobe_po = FALSE;
//------------------------------------------------------- po_mismatch = 0;
//-- Declare statements -- so_mismatch = 0;
//------------------------------------------------------- end
reg [1:SHIFT_PHASE] shift_1; endtask
integer scan_out[1:SO_LEN]; //-------------------------------------------------------
integer strobe_so, strobe_po; //-- Main routine --
integer in, i, error, bit_count; //-------------------------------------------------------
integer cycle, phase; initial
integer so_mismatch, po_mismatch; begin
integer ppi, ppo; init_variables;
integer num_shift_cycle; num_shift_cycle = SHIFT_CYCLE;
integer vec_print; for (in = 1; in <= NUM_VEC; in = in + 1)
integer inst; begin
integer vec_type; #1000.00; // settle vectors
reg [1:PI_LEN] pi_vector; $display(\nSimulation processing test vector %0d\n, in);
reg [1:PO_LEN] po_expected; vec_print = in;
reg [1:SO_LEN] so_expected; if (vec_type === I_TYPE)
reg [1:CHAIN1_LEN] si1_vector; begin
reg [1:CHAIN1_LEN] so1_expected; shift_sequence;
reg [1:PI_LEN] work_vector; hold_sequence;
reg [1:PO_LEN] sim_response; propagate_sequence;
reg [1:PI_LEN] pre_work_vector; end
//------------------------------------------------------- else if (vec_type === N_TYPE)
//-- Declare wires -- begin
//------------------------------------------------------- propagate_sequence;
wire STI_G17 ; end
wire STI_SCAN_OUT ; else if (vec_type === O_TYPE)
wire STI_CLK ; begin
wire STI_G0 ; ppo = 0;
wire STI_G1 ; inst = 1;
wire STI_G2 ; propagate_sequence;
wire STI_G3 ; reshift_sequence;
Figure 2-38 The s27_s0.drv.v File (partial)
(file continued)
end
end
num_shift_cycle = SHIFT_CYCLE - 1; endtask
shift_sequence; // scan out the very last pattern
$display(\n*** Test vectors simulated : %d, task propagate_sequence;
NUM_VEC); begin
$display(*** Number of PO mismatch : %d, work_vector = pi_vector;
po_mismatch); #1.00;
$display(*** Number of SO mismatch : %d, #997.00;
so_mismatch); #2.00;
$finish; end
end endtask
//-------------------------------------------------------
//-- Sequence tasks -- task reshift_sequence;
//------------------------------------------------------- begin
task shift_sequence; pre_work_vector = work_vector;
begin work_vector = pi_vector;
work_vector = pi_vector; work_vector[6] = 1b1;
work_vector[6] = 1b1; work_vector[1] = pre_work_vector[1];
ppi = SHIFT_CYCLE; phase = 1;
for (cycle = 1; cycle <= num_shift_cycle; cycle = cycle + while (phase <= SHIFT_PHASE)
1) begin
begin #1.00;
phase = 1; #997.00;
while (phase <= SHIFT_PHASE) if (phase == SHIFT_PHASE)
begin strobe_so = TRUE;
#1.00; phase = phase + 1;
work_vector[1] = shift_1[phase]; #2.00;
if (ppi > CHAIN1_LEN) work_vector[7] = 1b0; end
else work_vector[7] = si1_vector[ppi]; end
endtask
#997.00;
if (phase == SHIFT_PHASE && in != 1 && cycle != //-------------------------------------------------------
SHIFT_CYCLE) //-- Set clock values --
strobe_so = TRUE; //-------------------------------------------------------
phase = phase + 1; assign #200.00 STI_CLK = work_vector[1];
#2.00; //-------------------------------------------------------
end //-- Set input values --
ppi = ppi - 1; //-------------------------------------------------------
end assign #100.00 STI_G0 = work_vector[2];
end assign #100.00 STI_G1 = work_vector[3];
endtask assign #100.00 STI_G2 = work_vector[4];
assign #100.00 STI_G3 = work_vector[5];
task hold_sequence; assign #100.00 STI_STI_TM1 = work_vector[6];
begin assign #100.00 STI_SCAN_IN = work_vector[7];
work_vector = pi_vector; //-------------------------------------------------------
work_vector[1] = 1b0; //-- Get output values --
phase = 1; //-------------------------------------------------------
while (phase <= HOLD_PHASE) always
begin begin
#1.00; fork
#997.00; #900.00 sim_response[1] = STI_G17 ;
if (phase == HOLD_PHASE) #900.00 sim_response[2] = STI_SCAN_OUT ;
strobe_po = TRUE; #1000.00;
phase = phase + 1; join
#2.00; end
end //-------------------------------------------------------
end //-- Compare expected outputs to simulation results --
//-------------------------------------------------------
Figure 2-39 The s27_s0.drv.v File (continued)
always #999.00 (file continued)

begin
if (strobe_so) // compare scan out begin
begin if (so_expected[i] !== sim_response[scan_out[i]])
compare_so; $write(scan chain #%0d expected = %b simulated
if (error) = %b\n,
begin bit_count, so_expected[i],
print_so_mismatch; sim_response[scan_out[i]]);
so_mismatch = so_mismatch + 1; end
end bit_count = bit_count + 1;
inst = inst + 1; end
strobe_so = FALSE; $write(\n);
end end
if (strobe_po) // compare primary output endtask
begin
compare_po; task compare_po;
if (error) begin
begin error = FALSE;
print_po_mismatch; for (i=1; i <= PO_LEN && error === FALSE; i=i+1)
po_mismatch = po_mismatch + 1; begin
end if (po_expected[i] !== 1bx && po_expected[i] !==
strobe_po = FALSE; 1bz)
end if (po_expected[i] !== sim_response[i]) error =
#1.00; TRUE;
end end
end
task compare_so; endtask
begin
i = CHAIN1_LEN - ppo; task print_po_mismatch;
if (i <= 0) so_expected[1] = 1bx; begin
else so_expected[1] = so1_expected[i]; $write(*** PO mismatch at vector %0d,, vec_print,
error = FALSE; time %0d\n, $time);
for (i=1; i <= SO_LEN && error === FALSE; i=i+1) bit_count = 1;
begin for (i = 1; i <= PO_LEN; i = i + 1)
if (so_expected[i] !== 1bx && so_expected[i] !== begin
1bz) if (po_expected[i] !== 1bx && po_expected[i] !==
if (so_expected[i] !== sim_response[scan_out[i]]) 1bz)
error = TRUE; begin
end if (po_expected[i] !== sim_response[i])
ppo = ppo + 1; $write(PO #%0d expected = %b simulated =
end %b\n,
endtask bit_count, po_expected[i], sim_response[i]);
end
task print_so_mismatch; bit_count = bit_count + 1;
begin end
$write(*** SO mismatch at vector %0d,, vec_print, $write(\n);
scan out number %0d,, inst, time %0d\n, $time); end
bit_count = 1; endtask
for (i = 1; i <= SO_LEN; i = i + 1)
begin
if (so_expected[i] !== 1bx && so_expected[i] !== include s27_s0.vector
1bz)
begin endmodule
Figure 2-40 The s27_s0.drv.v File (end)
The s27_s0.vector file is shown in Figure 2-41.
// FILE : SynTest Verilog vector file (file continued)

// NAME : s27_s0.vector
// TIME : Tue Feb 17 19:25:54 1998 ......................................
// OPTIONS : -vlog -pscan
vec_type = N_TYPE;
initial pi_vector = 7b1001001;
begin #2000.00;
vec_type = I_TYPE; vec_type = N_TYPE;
pi_vector = 7b0011110; pi_vector = 7b0001001;
po_expected = 2bx1; #2000.00;
si1_vector = 2b11;
#11000.00; vec_type = N_TYPE;
pi_vector = 7b0111001;
vec_type = N_TYPE; #2000.00;
#2000.00; vec_type = O_TYPE;
vec_type = N_TYPE; so1_expected = 2b10;
pi_vector = 7b0100110; #5000.00;
#2000.00;
.......................... end
Figure 2-41 s27_s0.vector File
Running a Partial-Scan Test Using a Script File
The prun script shown in Figure 2-42 can be used to run the partial-scan test with the same
result as the previous interactive run.
#!/bin/csh -f
##1) Create Directory Structure
mkdir designs lib pscan dbg
##2) Compile cell library and netlist

expin s27
##3) Do testability analysis

asic123 -pscan s27 -o 123/s27
##4) Do partial-scan selection

scansel s27
##5) Do partial-scan synthesis and debug

scansyn -pscan s27
##6) Output synthesized netlist

##7) Do partial-scan ATPG

asicgen -post_pscan s27_s0 -o pscan/s27_s0
##8) Do pattern conversion

ln -s pscan/s27_s0.tp .
ln -s pscan/s27_s0.int .
tpout -vlog -pscan s27_s0
Figure 2-42 Partial-Scan Script File - prun
The script will:

Do partial-scan selection
Do partial-scan synthesis and debug
1. Execute the prun script. From the C Shell,
prun <CR>
=================== VLOGIN V2.0.0 r01 (10/28/97 15:19:49) ===================
TIME: Tue Feb 17 19:25:06 1998
***** Pass One *****

File: netsrc/s27.v
***** Pass Two *****
File: netsrc/s27.v
Created: lib/TX.sdb
Created: lib/IV.sdb
Created: lib/BU.sdb
Created: lib/EO.sdb
=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================
TIME: Tue Feb 17 19:25:10 1998

.
* Library Cell FD1

* Library Cell IV
* Library Cell AN2
* Library Cell OR2

* Library Cell ND2
* Library Cell NR2
=================== ASIC123 V2.0.0 r01 (12/05/97 09:33:21) ===================
TIME: Tue Feb 17 19:25:13 1998
Options selected: -pscan -o 123/s27.123.rpt
Read constraints from s27.dft.....

CLOCK CLK = 010
Reading scan specification input file s27.psi ...


Logic levels .............................. = 5

Cell elements ............................. = 13

Floating nets ............................. = 0

Floating busses ........................... = 0
Bus holders ............................... = 0

---------- ------- ---------- ----------
MEAN - - 29 -
CPU TIME = 0:00:02
END TIME : Tue Feb 17 19:25:15 1998
=================== SCANSEL V2.0.0 r01 (12/22/97 17:06:40) ===================
TIME: Tue Feb 17 19:25:16 1998
Options selected:
Process s27 ...

START TIME = Tue Feb 17 19:25:16 1998
Read in and check circuit at TIME Tue Feb 17 19:25:16 1998
Reading scan file - s27.psi ...



End circuit check at TIME Tue Feb 17 19:25:18 1998
CPU TIME = 0:00:02
Start circuit graph creation at TIME Tue Feb 17 19:25:18 1998
2 memory elements are specified as MUST_SCAN
End circuit graph creation at TIME Tue Feb 17 19:25:18 1998
CPU TIME = 0:00:00
Start circuit graph reduction at TIME Tue Feb 17 19:25:18 1998
End circuit graph reduction at TIME Tue Feb 17 19:25:18 1998
CPU TIME = 0:00:00
Start checking SPS property ...

Circuit s27 is a SPS
Start sps_balance at TIME Tue Feb 17 19:25:18 1998
End sps_balance at TIME Tue Feb 17 19:25:18 1998
CPU TIME = 0:00:00
Max sequential depth = 0

Scan count = 2
Memory count = 3
WARNING: Could not break all self & global loops due to DONT_SCAN constraint.
END TIME = Tue Feb 17 19:25:18 1998
CPU TIME = 0:00:02
=================== SCANSYN V2.0.0 r01 (01/08/98 10:18:02) ===================
TIME: Tue Feb 17 19:25:18 1998
Options selected: -pscan -o s27.syn.rpt



=============================================
=============================================

======================================================
Report
======================================================
Circuit Name : s27

Synthesis Status
------------------------------------------
DRC Error Status

------------------------------------
Set Error
Found : 0
Fixed : 0
Skiped : 0
Reset Error
Found : 0
Fixed : 0
Skiped : 0
Shift Clock Error

Found : 0
Fixed : 0
Skiped : 0
Capture Clock Error

Found : 0
Fixed : 0
Skiped : 0
Transparent Error
Found : 0
Fixed : 0
Skiped : 0
Bidi Error
Found : 0
Fixed : 0
Skiped : 0
Bus Error
Found : 0
Fixed : 0
Skiped : 0
Cross Coupled Error

Found : 0
Fixed : 0
Skiped : 0
RAM Error
Found : 0
Fixed : 0
Skiped : 0
Tri-State Pad Error

Found : 0
Fixed : 0
Skiped : 0

----------------------------------------------

------------------------------------------
Sequence | STI_TM1
-----------+------------------------------
Normal | 0
Shift | 1
Hold | X
Capture | X
------------------------------------------

======================================================
CPU TIME = 0:00:13
END TIME : Tue Feb 17 19:25:33 1998
=================== SCANDBG V2.0.0 r01 (11/07/97 11:24:04) ===================
TIME: Tue Feb 17 19:25:34 1998


SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :

success!!
success!!

success!!

chain - chain_1 OK.
success!!
---------------------------- CHAIN STATUS ------------------------------
CPU TIME = 0:00:02
END TIME : Tue Feb 17 19:25:36 1998
=================== SCANDBG V1.0.9 r03 (11/07/97 11:24:04) ===================
TIME: Tue Feb 17 19:25:37 1998


SCAN_IN : SCAN_IN
SCAN_OUT : SCAN_OUT
CLOCK : CLK
SHIFT :

success!!

success!!

success!!

chain - chain_1 OK.
success!!
---------------------------- CHAIN STATUS ------------------------------
CPU TIME = 0:00:02
END TIME : Tue Feb 17 19:25:39 1998
=================== LSDB V2.0.0 r01 (12/23/97 09:14:47) ===================
TIME: Tue Feb 17 19:25:39 1998

=================== ASICGEN V2.0.0 r01 (02/17/98 19:06:10) ===================
TIME: Tue Feb 17 19:25:43 1998
Options selected: -post_pscan -pscan -atpg -limit 10000 -multi_cycle

-dont_scan_loop -must_scan_only -o pscan/s27_s0.rpt

Clock CLK Pattern=010



* Scanning only MUST_SCAN objects

* (No automatic selection made)
.............
CPU TIME = 0:00:06
END TIME : Tue Feb 17 19:25:53 1998
Selecting partial-scan objects ...
Select 2 scan elements
**** Incremental Partial Scan has selected maximal number of scan elements. ****
54 Hard detected faults are saved in pscan/s27_s0.hdt.
2 Potentially detected faults are saved in pscan/s27_s0.pdt.
2 partial-scan objects are saved in pscan/s27_s0.pso.
and contains 56 faults of which


and contains 108 UNCOLLAPSED faults of which



CPU TIME = 0:00:06
END TIME : Tue Feb 17 19:25:53 1998
=================== TPOUT V2.0.0 r01 (02/09/98 18:56:47) ===================
TIME: Tue Feb 17 19:25:54 1998
OPTIONS : -vlog -pscan

- Processing DFT file s27_s0.dft ...
Scan information :
Shift sequence
CLK = 010
STI_TM1 = 1
Hold sequence
CLK = 0
Capture sequence
CLK = 010
Clock information :
CLK (P) = 010
- Processing test vector file s27_s0.tp ...



TS Tutorial

Încărcat de

Informații document

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

TS Tutorial

Încărcat de

Drepturi de autor:

Formate disponibile

Full-Scan Tutorial

SynTest Tutorials 1-1

Tutorials Directory and File Structure

Figure 1-1 Tutorial Directory and Files Structure

1-2 SynTest Tutorials

Table 1-1 Tutorial Files and Directories

netsrc Directory containing design.v files (Verilog structural file)

*.lib Cell library file used by boundary-scan.

*.bsc File containing information that sets condition used by boundary-scan.

frun Script file to run a full-scan synthesis.

prun Script file to run a partial-scan synthesis.

brun Script file to run a boundary-scan synthesis.

SynTest Tutorials 1-3

The s27 Design

Figure 1-2 The s27.v Design Schematic

1-4 SynTest Tutorials

module s27 (G17, CLK, G0, G1, G2, G3);

Figure 1-3 Verilog Structural Netlist of s27.v Design

SynTest Tutorials 1-5

timescale 1ns / 10ps

module IV (Z, A); module EO (Z, A, B);

Figure 1-4 Cell Library - s27lib.v File

1-6 SynTest Tutorials

Creating Directory Structure

setenv SYNTEST /disk1/usr/home/syntest

Figure 1-5 The .syntest File

SynTest Tutorials 1-7

Compiling the Design Cell Library and Netlist

In this section, you will:

1-8 SynTest Tutorials

primitive.def primitive.def primitive.def

syntest.def syntest.def edif2tdl

Figure 1-6 Compiling Process Flow

Translating and Compiling the Verilog Netlist and Library

The vlogin utility reads:

SynTest Tutorials 1-9

syntest.def and primitive.def files (required files located in the $SYNTEST/designs

vlogin netsrc/s27.v -opath designs -lib libsrc/s27lib.v

Detailed information regarding this translator can be found in Command Reference,

The processing messages are shown in Figure 1-7.

=================== VLOGIN V2.0.0 r01 (Tue Nov 25 14:45:57 1997) ===================

Copyright (c), 1991-1998, SynTest Technologies, Inc. All rights reserved.

TIME: Wed Dec 17 20:55:42 1997

***** Pass One *****

Figure 1-7 Translator vlogin Processing Messages

The output files created are:

Linking and Expanding the Design

Detailed information regarding this program can be found in Command Reference,

2. Expand the design .sdb files. From the Shell prompt,

The expansion processing messages are shown in Figure 1-8.

=================== EXPIN V2.0.0 r01 (07/14/97 09:59:05) ===================

Copyright (c), 1991-1996, SynTest Technologies, Inc. All rights reserved.

TIME: Thu Jan 1 13:56:23 1998

Figure 1-8 Expansion Processing Messages

Running Testability Analysis

The testability audits allow you to:

The testability analysis flow is shown in Figure 1-9.

Figure 1-9 Testability Analysis Flow

The tool asic123 reads:

1. Observe the s27.dft file. From the shell prompt,

The user-defined s27.dft is shown in Figure 1-10.

// For full-scan test pattern generation

Figure 1-10 The User-defined s27.dft

2. Run testability analysis. From the Shell prompt,

* Pass One *

CIRCUIT STATISTICS

TESTABILITY ANALYSIS SUMMARY

SYNTEST TESTABILITY REPORT