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6. CMOS
Havingexploredthepowerfulcombinationaldeviceabstractionasamodelforourlogical
buildingblocks,weturntothesearchforapracticaltechnologyforproductionofrealistic
implementationsthatcloselymatchourmodel.Ourtechnologywishlistincludes:

Highgainandnonlinearity,asdiscussedinSection5.6,tomaximizenoiseimmunity.
Lowpowerconsumption.Somepowerwillbeusedaschangingsignallevelscausecurrent
toflowinoutoutofparasiticcapacitances,butanidealtechnologywillconsumenopower
whensignalsarestatic.
Highspeed.Ofcourse,we'dlikeourdevicestomaximizeperformance(implyingthatt pd

propagationdelaysbeminimizedandphysicalsizesbesmall.
Lowcost.

Duringthefewdecadesthatelectronicdigitalsystemshaveexplodedontheengineeringscene,a
numberofnonlineardevicetechnologieshavebeenusedrangingfromelectromagneticrelays
tovacuumtubesanddiodes.Theadventofsemiconductorelectronicsandtheminiaturization
pushofintegratedcircuits,technologybreakthroughsroughlycontemporaneouswiththedigital
revolution,openedthewaytoincorporationofbillionsofactivedevices(transistors)onthe
surfaceofasmallsiliconchip.Aremarkablesuccessionofengineeringimprovementshave
allowedthenumberoftransistorsonachiptodoubleroughlyeverytwoyearsforthelast5
decades,aphenomenonpopularlyreferredtoasMoore'sLawafteritsobservationin1965by
IntelfounderGordonMoore.

Onetechnology,CMOS(forComplementaryMetalOxideSemiconductor),hasemergedasthe
logictechnologyofchoice,gettinghighmarksineachdimensionofourwishlist.We,likemost
ofindustry,willfocusonCMOSasourchoiceforimplementinglogicdevices.

6.1. MOSFETs

ThenonlinearcircuitelementinCMOSistheMOSFETorMetalOxideSemiconductorField
EffectTransistor,whosephysicalstructureissketchedbelow.

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MOSFETphysicallayout
MOSFETsareusedinCMOSlogicasvoltagecontrolledswitches:currentmayormaynotflow
betweentwoMOSFETterminalscalledthesourceandthedraindependingonthevoltageona
thirdterminal,thegate,whichseparatesthem.

AnimportantfeatureofMOSFETsisthatnosteadystatecurrentflowsbetweenthegate
terminalandthesourceanddrain:thegatebehavesasifitiscoupledtotheotherterminals
throughacapacitor.Currentflowsintoandoutofthegateterminalonlywhenthegatevoltage
changes,andthenonlyuntilthechargeonthegatereachesanequilibriumthatmatchesthe
voltagedrop.ThisallowsMOSFETstodrawnogatecurrentwhilequiescent(i.e.,whenlogic
valuesareconstant)ifwedesignourCMOScircuitssothatsourceanddraincurrentsof
quiescentcircuitsarezeroaswell,wecanachievethegoalofzeroquiescentpowerdissipation.
Wewilladoptshortlyacookbookformulathatoffersthismajorpoweradvantage.

6.1.1. NFETs and PFETs

AkeytoCMOScircuitdesignismanufacturingtechnologythatallowsfabricationoftwo
differenttypesofMOSFETonasinglesiliconsurface.ThetwoflavorsoftransistoraretheN
channelandPchannelFET,whichperformcomplementaryfunctionsinCMOSdevices(hence
theCinCMOS).EachFETisafourterminaldevicehoweverourstylizeduseofNFETsand
PFETsinvolvesconnectingtheB(Bulk)terminaltogroundorV DD respecively,andusingthem
asthreeterminalcircuitcomponents.

Thefiguretotherightshowsthecircuitsymbolforan
NFET,alongwithasketchofitsphysicallayoutand
circuitmodelsforitsbehaviorasavoltagecontroled NFETswitchingbehavior
switch.Thetransistorisfabricatedbyembeddingn
type(doped)sourceanddrainterminalsinaptype
substrate,whichisconnectedtogroundviatheB
(Bulk)terminal.Thegateelectrodecontrolstheflowof
currentbetweensourceanddrain:ifthevoltageV GS

betweenthegateandthesourceislessthanathreshold
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,nocurrentflowsbetweensourceanddrain:
VT H ,N F ET

thetransistorbehaveslikeanopenswitch.IfV is GS

abovetheV threshold,currentflowsfrom
T H ,N F ET

draintosource,impededbyasmall"on"resistance.A
typicalswitchingthresholdvoltageisaboutahalfvolt.
IfweconnectthesourceofanNFETtoground,it
providesaneffectivemeansofselectivelygrounding
thenodeconnectedtoitsdrainbychangingitsgate
voltage.

The

complementaryPFETismadebyembeddingawellof
ntypesiliconintheptypesubstrate,andconnecting
thentypewelltothepowersupplyvoltageV via
DD

terminalBinthefigure.Withinthatwell,thePFET
transistorisfabricatedusingoppositepolaritydopings
fromthoseoftheNFET:thesourceanddrainaremade
ofptypesilicon.ThecircuitsymbolforthePFETis
similartothatoftheNFET,withtheadditionofan
smallcircleatthegateterminal:thesesocalled
inversionbubblesarewidelyusedinlogicsymbolsto
PFETswitchingbehavior
indicatethatthesenseofasignalisoppositeofwhatit
wouldbewithoutthebubble.InthecaseofthePFET,it
flagsthefactthattheswitchbehaviorisoppositeoftheNFET's:V aboveathresholdvalue
GS

makesthePFETsource/drainconnectionlooklikeanopenswitch,whileV belowthe GS

thresholdconnectssourcetodrainthroughalow"on"resistance.APFETwhosesourceis
connectedtothepowersupplyvoltageV providesaneffectivewaytoselectivelyconnectits
DD

draintoV . DD

6.1.2. Transistor Sizing

Designparametersforeachtransistorincludeitsphysicaldimensions,whicheffectitscurrent
andpowerhandlingcapacity.ItiscommontoparameterizeFETsbythewidthandlengthofthe
channelbetweenthesourceanddrain,inscaleddistanceunits:lengthisthedistancebetween
sourceanddrain,whilewidthisthewidthisthelengthofthechannel/sourceandchannel/drain
boundaries.Ofparticularinterestistheratiobetweenthewidthandlengthofthechannel,
whichdeterminesthe"on"resistanceandhencethecurrentcarryingcapacityofthesource
drainconnectionwhenthetransistoris"on".Ingeneral,thedrainsourcecurrentI DS is
proportionaltotheW idth/Lengthratio.

Whilewewilllargelyignoretransistorsizingissuesinoursubsequentcircuits,thisparameter
canplayanimportantroleintheoptimizationofperformanceandenergyconsumptionofa

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digitalcircuit.Adevicewhoseoutputdrivesalongwireorheavycapacitiveload,forexample,
maybenefitfromtuningoftransistorsizestoprovidehighercurrentoutput.

6.2. Pullup and Pulldown Circuits

EachoftheNFETandPFETdevicesbehavesasavoltagecontrolledswitch,enablingor
disablingaconnectionbetweenitssourceanddrainterminalsdependingonwhetheritsgate
voltageisaboveorbelowafixedthreshold.Ourintentionistoselectlogicmappingparameters
asdescribedinSection5.4.1thatplacetheFETswitchingthresholdsreliablyintheforbidden
zone,sothatvalidlogiclevelsappliedtogateterminalsofNFETsandPFETswillopenorclose
theirsource/drainconnections.Byusinglogiclevelstoopenandclosenetworksofswitches,we
canselectivelydriveoutputterminalsoflogicdevicestoground(0volts)orV (powersupply
DD

voltage),whichrepresentmaximallyvalid0sand1srespectively.

Ingeneral,eachlogicaloutputofadevicewillselectively
connecttogroundthroughapulldowncircuitandwill
selectivelyconnecttoV throughapullupcircuit,wherethe
DD

pulldownandpullupcircuitscontainFETswhosegatesare
connectedtologicalinputs.Givenourgoalsof(a)driving
eachoutputtoavalidlogiclevelforeachinputcombination
and(b)zeroquiescentcurrentflow,itisimportantthat
Pullup/Pulldowncircuits
exactlyoneofthepullup/pulldowncircuitspresentaclosed
circuitforanyinputcombination.Ifneithercircuitconducts,
theoutputvoltagewill"float"atsomeunspecifiedvalue,likelyinvalidifbothconduct,alow
resistancepathbetweenV andgroundwilldissipateexcessivepowerandlikelydopermanent
DD

damagetothecircuit.

NFETsarewellsuitedforuseinpulldowncircuitssincetheycanconnecttheoutputterminalto
groundpotentialviaasmall"on"resistancebutwithoutathresholdvoltagedropbetweenthe
outputvoltageandgroundforsimilarreasons,PFETsareanearlyidealchoiceforuseinpullup
circuits.ConsequentlyCMOScombinationallogicdevices(commonlycalled"gates",nottobe
confusedwiththegateterminalofaMOSFET)useonlyPFETsinpullupcircuitsandNFETsin
pulldowns.ThemainclevernessrequiredinthedesignofaCMOSgateistocomeupwithpullup
andpulldowncircuitsthatareproperlycomplementarythatis,todesignthecircuitssothat
foreverycombinationoflogicalinputs,eitherthepulluporthepulldownisactivebutnotboth.

RecallingthatanNFETisactive(conducts)whenitsgatevoltageishigh(a
logic1)andPFETisactivewhenitsgatevoltageislow(alogicalzero),wecan
constructthesimplest"interesting"CMOSgate:aninverter.Theinverterusesa
singlePFETpullupandasingleNFETpulldownasshowntotheleft.Itslogical
inputisconnectedtothegateterminalsofboththePFETpullupandtheNFET
CMOS pulldown,turningonthepulldownpathwhenitsvalueis1andturningonthe
Inverter pulluppathwhenitsvalueis0,causingtheoutputvoltagetorepresentthe
oppositelogiclevelfromitsinput.WearrangethatV iswellbelowthe
il

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switchingthresholdofbothtransistors,sothatavalid0inputcausesthepulluptoconductand
thepulldowntopresentanopencircuitsimilarly,ensuringV iswellabovethethresholds
ih

assurestheoutputterminaltobeconnectedtogroundandnotV onavalid1input. DD

IfweplotthevoltagetransfercurveoftheCMOSinverter,we
getsomethinglikethatshowntotheright:thehighgainnear
theswitchingthresholdsofthetransistorsisconfinedtothe
forbiddenzoneofourlogicmapping,neatlyavoidingthe
shadedregionscorrespondingtoinvalidoutputscausedby
validinputs.Thepullup/pulldownarchitectureofCMOSgates
assuresthatV andV canbeclosetoV and0,
OH OL DD

respectively,whileV andV needonlybracketthenearly

IL IH

verticalstepsatthetransistorswitchingthresholds.This
combinationleadstogoodnoisemargins. CMOSInverterVTC

Recallthatthevoltagetransfercurverepresentsan
equilibriumoutputvoltageforeachinputvoltage.

Itcanbemadeusingatestsetupsimilartothatshownonthe
left,wheresuccessiveinputvoltagesareappliedtoour
inverterinput,andenoughtimeisallowedtoelapsetoletV out

stabilize.Evenwithnothingconnectedtotheoutputterminal,
thismaytakesometimeduetoparasiticcapacitances,
resistances,andinductances.Atequilibrium,V willbe
out

constantandi = i :therewillbenooutputcurrent,soany
pu pd

currentflowingthroughthepullupmustcontinuethroughthe
pulldown.Oncethisequilibriumisreached,V isrecorded
out

VTCTestSetup onourvoltagetransfercurveandwemoveontothenext
inputvoltage.

6.2.1. Series and Parallel Connections

Pullupandpulldowncircuitsforlogicfunctionsofmultipleinputsinvolvesconfiguringseries
andparallelconnectionsofPFETs(inpullups)orNFETs(inpulldowns),againwitheachgate
terminalconnectedtoonelogicalinput.

Aquickreviewofparallelandseriesconnectionof"switching"circuits:

Assumethatthenotationshowntotheleftrepresentsacircuit
thatconductswhensomecircumstancewecallAistrue,and
otherwisepresentsanopencircuitbetweenitstwoterminals.

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Thentheseriescircuitshowntotheleftconductsonlywhenboth
AandBaretrue:ifeitherAorBisfalse,thecorresponding

circuitwillopenandnocurrentwillflow.Thisallowsustoeffect
alogicalANDbetweentheconditionsAandB.

Similarlytheparallelcircuitshowntotheleftrepresentsacircuit
thatconductswheneitherAorB,orbothAandB,aretrue.
ThiseffectsalogicalORbetweentheconditionsAandB.

UsingseriesandparallelcombinationsofcircuitscontainingNFETsandPFETs,wecanbuild
pullupandpulldowncircuitsthatareactivepullanoutputtogroundorV basedon DD

ANDsandORsoflogicvaluescarriedoninputwires.

6.2.2. Complementary circuits

TheremainingingredienttoourCMOSformulaistherequirementthatweconnecteachoutput
tocomplementarypullupsandpulldownsthatis,thatthepulluponanoutputisactiveon
exactlythecombinationofinputvaluesforwhichthepulldownonthatoutputisnotactive.
Circuit Complement Description

Notation:ThebarovertheconditionAindicates
acircuitthatisactivewhenAisnottruethusthe
twocircuitstotheleftarecomplementary.

GivenaseriesconnectionofcircuitsactiveonA
andB,wecanconstructitscomplementbythe
parallelconnectionofcomplementarycircuitsA

andB

.

GivenaparallelconnectionofcircuitsactiveonA
andB,wecanconstructitscomplementbythe
seriesconnectionofcomplementarycircuitsA

and B.

Finally,weobservethatanNFETconnectedtoan
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inputAisthecomplementofaPFETconnectedto
thesameinput:theNFETpresentsaclosedcircuit
whenAisalogical1,whilethePFETcloseswhen
A = 0asweobservedintheCMOSinverter.

Theastutereaderwillnoticethattheaboveobservationsgivesusapowerfultoolkitforbuilding
complementarypullupandpulldowncircuitsbasedoncombinationsofinputvalues.The
NFET/PFETruleallowsustobuildpullups/pulldownsforsinglevariables,aswedidinthe
invertertheseries/parallelconstructionsallowustocombinepullupsorpulldownsforseveral
variables,sayAandB,tomakepullupsorpulldownsforlogicalcombinationssuchastheAND
orORofAandB.

BecauseoftheelectricalcharacteristicsofPFETsandNFETs,CMOSgatesuseonlyPFETsin
pullupcircuitsandNFETsinpulldowncircuits.ThuseachoutputofaCMOSgateisconnected
toapullupcircuitcontainingseries/parallelconnectedPFETs,aswellasacomplementary
pulldowncircuitcontainingparallel/seriesconnectedNFETs.

Itisworthobservingthat

1.ForeveryPFETbasedpullupcircuit,thereisacomplementaryNFETbasedpulldown
circuitandviceversa.
2.Givenapulluporpulldowncircuit,onecanmechanicallyconstructthecomplementary
pulldown/pullupcircuitbysystematicallyreplacingserieswithparallelconnections,
parallelwithseriesconnections,PFETswithNFETs,andNFETswithPFETs.Theresulting
ciruitsaredualsofoneanother,andareactiveundercomplementaryinputcombinations.
3.OurrestrictionstoPFETsinpullupsandNFETsinpulldownsmakessingleCMOSgates
naturallyinverting:alogical1onaninputcanonlyturnonanNFETandturnoffaPFET.
ThislimitsthesetoffunctionswecanimplementassingleCMOSgates:certainfunctions
requiremultipleCMOSgatesintheirimplementation.

6.3. The CMOS Gate Recipe

WeusethetermCMOSgatetorefertoasingleoutput
combinationaldeviceimplementedasshowntotheright.The
outputnodeisconnectedtoV viaapullupconsistingofzero
DD

ormorePFETs,andisconnectedtogroundviaapulldown
consistingofzeroormoreNFETs.Thedevicehaszeroormore
logicalinputs,andthegateterminalofeachPFETorNFETis
connectedtoonesuchinput.

InthetypicalCMOSgate,

Thepullupandpulldowncircuitsaredualsofeachother,in
thesensedescribedinSection6.2.2.

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EachinputconnectstooneormorePFETsinthepullup,andtoanequalnumberof
NFETsinthedualpulldowncircuit.AnexceptionisthedegeneratecaseofaCMOSgate
whoseoutputisindependentofoneormoreinputsinthiscase,theignoredinputsarenot
connectedtoanything.
Fortheabovereasons,asingleCMOSgatetypicallycomprisesanevennumberof
transistors,withequalnumbersofNFETsandPFETs.

Ourspecificationof"zeroormore"transistorsinthepullup/pulldowncircuitsallowsusto
includethedegenerateextremesasCMOSgates:deviceswhichignorealltheirinputsand
produceaconstant0or1asoutputbyconnectingtheoutputnodetoV orground. DD

Ingeneral,wecanapproachthedesignofaCMOSgateforsomesimplefunctionFbyeither

DesigningapulldowncircuitthatisactiveforthoseinputcombinationsforwhichF = 0 ,
or
DesigningapullupcircuitthatisactiveforthoseinputcombinationsforwhichF = 1

andthensystematicallyderivingthecomplementarypullup/pulldowncircuitbytakingthedual
ofthecircuitwe'vedesigned.Finally,wecombinethemtomaketheCMOSgatepertheabove
diagram.

6.3.1. Common 2input gates

Asimpleapplicationoftheaboverecipecanbeusedtoimplementthe
popular2inputNANDgate,whosecircuitsymbolandtruthtableareshown
totheright.ThenameNANDderivesfrom"NotAND",reflectingthefact
thatthegate'soutputistheinverseofthelogicalANDofitstwoinputs.The
circuitsymbol,similarly,consistsofashapeconventionallyusedtodepictan
ANDoperationhavingastraightinputsideandacurvedoutputside
withasmallcircle(orbubble)atitsoutputwhichconventionallydenotes NANDgate
inversion.

FromtheNANDtruthtable,weobservethatthegateoutputshouldbezeroifandonlyifboth
inputvaluesare1,dictatingapulldownthatisactive(conducting)whentheAandBinputsboth
carryahighvoltage.

Thepulldownishandilyconstructedfromaseriesconnectedpairof
NFETsbetweentheoutputnodeandground,asshowninthe
diagramtotheleft.Thecomplementarypullupcircuitisthedualof
thepulldown,consistingofparallelconnectedPFETsbetweenthe
outputCandthesupplyvoltageV ,againasshowninthediagram.
DD

ThegateelementofeachFETinthepullupandpulldowncircuitsis
connectedtooneofthelogicalinputs(AorB)toourCMOSgate,
causinglogicalinputcombinationstoopenandclosetheFET

CMOSNANDgate

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switcheseffectinganappropriateconnectionoftheoutputC toV DD

orgroundaccordingtothevaluesinthetruthtable.

Alternatively,theuseofparallelconnectedNFETsinthepulldownand
seriesconnectedPFETsinthepullupyieldsaCMOSimplementationofthe
NORgatewhosecircuitsymoblandtruthtableareshowntotheright.
Again,thesymbolisacompositeofthestandard
symbolforalogicalORwithaninversionbubble
onitsoutput,indicatinga"NotOR"orNOR
operation.ThecorrespondingCMOS NORgate
implementationisshowntotheleft.

TheCMOSimplementationofa2inputNANDgatecanbeeasily
extendedtoNANDof3,4ormoreinputsbysimplyextendingthe
seriespulldownchainandparallelpullupwithadditionalFETswhose
gateelementsconnecttotheadditionallogicalinputs.Similarly,the
CMOSNORgate 2inputNORgatecanbeextendedto3ormoreinputNOR
operationsbyaddinganNFET/PFETpairforeachadditionallogical
input.Electricalconsiderations(suchasdelaysduetoparasitics)usuallylimitthenumberof
inputsofsingleCMOSgates(thesocalledfanin)toasomethinglike4or5beyondthissize,a
circuitconsistingofseveralCMOSgatesislikelytoofferbettercost/performancecharacteristics.

6.4. Properties of CMOS gates

TheCMOSgaterecipeofanoutputnodeconnectedcomplementaryPFETbasedpullupand
NFETbasedpulldowncircuitsoffersanearlyidealrealizationofthecombinationaldevice
abstraction,since

Foreachinputcombination,itwilldriveitsoutputtoanequilibriumvoltageof0(ground)
orV ,generatingidealrepresentationsoflogical0or1.
DD

Atequilibruim,theFETsusedinthepullup/pulldowncircuitsdrawzerogatecurrent.This
impliesthatCMOSgatesdrawzeroinputcurrentonceparasiticcapacitanceshavebeen
chargedtoequilibrium,henceCMOScircuitshavezerostaticpowerdissipation.

Inthefollowingsections,wewillexploreadditionalconsequencesoftheCMOSgatedesign
regimen.

6.4.1. CMOS gates are inverting

ItmayseempeculiarthattheexampleCMOSgateschosenforSection6.3.1includeNANDand
NORbutnottheconceptuallysimplerlogicaloperationsANDandOR.Infact,thischoice
reflectsafundamentalconstraintofCMOS:onlycertainlogicalfunctionsinvertingfunctions
canbeimplementedasasingleCMOSgate.OtherfunctionsmaybeimplementedusingCMOS,
buttheyrequireinterconnectionsofmultipleCMOSgates.

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Tounderstandthisrestriction,considertheeffectofaninputtoaCMOSgateonthevoltageon
itsoutputnode.Alogical0agroundpotentialcanonlyaffecttheoutputbyturningoff
NFETsinthepulldownandturningonPFETsinthepullup,forcingtheoutputtoalogical1.
Conversely,aninput1canonlyeffecttheoutputvoltagebydrivingittoalogical0.This
constraintisconsistent,forexample,withakinputNORoperation,wherea1onanyinput
forcestheoutputtobecome0however,itcannotrepresentalogicalOR,wherea1onanyinput
mustforcetheoutputtobecomea1.ThuswecanimplementkinputNORasasingleCMOS
gate,buttoimplementkinputORweuseakinputNORfollowedbyaninverter.

WecandeterminewhetheraparticularfunctionFcanbeimplementedasasingleCMOSgateby
examiningpairsofrowsofitstruthtablethatdifferinonlyoneinputvalue.Changinganinput
from0to1canonlyeffecta1to0changeontheoutputofaCMOSgate,ormayleavethe
outputunchangeditcannotcausea0to1outputchange.Norcana1to0inputchangecause
a1to0outputchange.ThustheobservationthatF (0, 1, 1) = 1butF (0, 0, 1) = 0causesusto
concludethatthefunctionF cannotbeimplmentedasasingleCMOSgate.

Togeneralizeslightly,supposethatweknowthatsome3inputfunctionF isimplementedasa
singleCMOSgate,andthatF (0, 1, 1) = 1.Sincechangingeitheroftheinput1sto0canonly
forcetheoutputtobecome1,thatimpliesF (0, x, y) = 1 foreverychoiceofxandy,an
observationthatwemightdenoteasF (0, , ) = 1usingtodenoteanunspecified"don'tcare"
value.Similarly,knowingthatF (1, 0, 1) = 0impliesthatF (1, , 1) = 0sincechangingthe
secondargumentfrom0to1canonlyforcethealready0outputto0.

KnowingthattheoutputofaCMOSgateis0forsomeparticularsetofinputvaluesassuresus
thatthe1samongitsinputsareturningonasetofNFETsinitspulldownthatconnectsits
outputnodetoground:itsoutputwillbezerosolongastheseinput1spersist,independentlyof
thevaluesontheotherinputs.Similarly,knowingthataCMOSgateoutputis1forsomeinput
combinationassuresusthatthe0samongtheinputsenableapulluppathbetweentheoutput
andV ,independentlyoftheotherinputs.
DD

Takingtheseobservationstotheextreme,aCMOSgatewhoseoutputis1whenallinputsare1
canonlybethedegenerategatewhoseoutputisalways1independentlyofitsinputs,and
similarlyforthegatewhoseoutputis0givenonly0inputvalues.

6.4.2. CMOS gates are lenient

WecantaketheobservationsoftheprevioussectiononestepfurthertoshowthatCMOSgates
arelenientcombinationaldevicesasdescribedinSection5.9.2.Recallthatlenienceimpliesthe
additionalguaranteeofoutputvaliditywhenasubsetoftheinputshavebeenstableandvalidfor
t PD,solongasthatinputsubsetissufficienttodeterminetheoutputvalue.Forexample,ifthe
truthtableofa3inputlenientgateGspecifiesthatG(0, 0, 1) = 1 = G(0, 1, 1),whichwe
abbreviateasG(0, , 1) = 1 ,thenG'slenienceassuresthatitsoutputwillbe1wheneveritsfirst
inputhasbeen0anditsthirdinputhasbeen1foratleastt PD ,independentlyofthevoltage(or
validity)ofitssecondinput.

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IfGisimplementedasasingleCMOSgate,thisleniencepropertyfollowsautomatically.Inour
example,theG(0, , 1) = 1 propertyofthetruthtabledictatesapullupwithapaththat
connectstheoutputtoV wheneverthefirstinputis0,viz.aPFETgatedbythefirstinput
DD

betweentheoutputnodeandV .Thisconnectionisindependentofthesecondinputas
DD

dictatedbythetruthtable,andisinfactindependentofthethirdinputsincePFETpathscan
onlybeturnedonby0inputs.Becauseofthecomplementarynatureofthepulldowncircuitry,a
0valueonG 'sfirstinputmustturnoffanNFETineverypathbetweentheoutputnodeand

ground,disablingthepulldown.Thusa0onthefirstinputelectricallyconnectstheoutputnode
toV independentlyofthevoltagesontheothertwoinputs:theymayrepresentvalid0,valid
DD

1,orbeinvalid(intheforbiddenzone).

AnanalogousargumentcanbemadeforaCMOSgateGwhosevalueis0(ratherthan1)for
somesubsetofinputvalues,e.g.ifG(0, , 1) = 0 .Inthiscase,G'soutputmustbeconnectedto
groundviasomeNFETinthepulldowngatedbythethirdinput,andthatconnectionisassured
bytheG(, , 1)inputpatternindependentlyofthevoltagesonthefirsttwoinputs.

Asaconcreteexample,considerthefunctionalspecificationofa2
inputNORgateshowntotheright.
Consideranexperimentwherewehold
oneinputAoftheNORgateata
logical1,andmakeatransitiononthe
otherinputfrom1to0asshowninthe
NORglitch diagramtotheleft.ConsultingtheNOR
truthtable,boththeinitialoutputofthe
gate(priortotheinputtransition)anditsfinaloutputshouldbe0.
NORgate
Assumingonlythatthegateobeysthespecificationsasa
combinationaldevice,theoutputC isconstrainedtobe0untilt CD

followingtheinputtransition,andagaint afterthetransitionhowever,itiscompletely
PD

unspecifiedbetweentheendsofthet andt windows.Duringthistimeitmayexhibita

CD PD

"glitch",evenbecomingavalid1multipletimes,beforesettlingtoitsfinalvalueof0.

Thisbehavioriscompletelyconsistentwiththecombinationaldevice
abstraction,andisusuallyunobjectionableinpractice.Butconsider
repeatingtheaboveexperimentusingourCMOSimplementationof
NOR,showntotheright.TheconnectionoftheAinputtoaconstant
1hastheeffectofturningoffoneoftheseriesconnectedPFETsin
thepullup,isolatingtheoutputfromV italsoturnsononeofthe
DD

parallelconnectedNFETsinthepulldown,assuringaconnection
betweentheoutputandground.TheA = 1constraintthusassures
anoutputof0independentlyoftheinputB,whichcanbeeitherlogic
value(orinvalid)withoutcompromisingtheoutputsolongasA
remains1.Inadditiontoobeyingtherulesforacombinational
device,theCMOSimplementationislenient:itsoutputvalidityisassuredbyanysubsetof
inputssufficienttodetermineanoutputvalue,andisuneffectedbychangesonotherinputs.

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Generalizing,ifweconsidervariouspathsthroughthepullupand
pulldowncircuitsofaCMOSgatewecansystematicallyconstuct
rowsofalenienttruthtable(containingdon'tcareinputs,written
as).Eachpathbetweentheoutputandgroundthroughthe
pulldowncircuitdeterminesasetofinputs(thosegatingtheNFETs
alongthepath)capableofforcingtheoutputto0similarly,each
LenientNORtiming paththroughthepullupcircuitdeterminesasetofinputscapable
offorcinga1output.Whenevertheinputsalongapulluppathare
all0thegateoutputwillbe1,andwhenevertheinputsalongapulldownpathareall1thegate
willoutputa0.Eachofthepulluppathscorrespondstoatruthtablelinewhoseinputsare0s
andsandwhoseoutputis1eachofthepulldownpathscorrespondstoalinewith1andsas
inputsanda0output.Ingeneral,thebehaviourofeverysingleCMOSgatecanbedescribedbya
setofsuchrules,andconformstoourdefinitionofalenientcombinationaldevice.

Itisimportanttonotethat,whileeverysingleCMOSgateislenient,combinationaldevices
constructedascircuitswhosecomponentsareCMOSgatesarenotnecessarilylenient.Thistopic
willberevisitedinSection7.7.1.

6.4.3. CMOS gate timing

Ascombinationaldevices,thetimingofaCMOSgateischaracterizedbytwoparameters:its
propagationdelayt ,anupperboundonthetimetakentoproducevalidoutputsgivenvalid
PD

inputs,anditscontaminationdelayt ,alowerboundonthetimeelapsedbetweenaninput
CD

becominginvalidandtheconsequentoutputinvalidity.Thephysicalbasisforthesedelaysisthe
timerequiredtochangevoltageoncircuitnodesduetocapacitance,includingtheunavoidable
parasiticcapacitancediscussedinSection4.3.1.

ConsideraCMOSinverterwhoseoutput
connectstoanotherinverter,asshowntothe
right.Theoutputnodeischaracterizedbysome
capacitiveload,C ,whichincludesbothintrinsic
capacitanceofconnectedinputsaswellas
parasiticcapacitanceofthewiring.Whenthe
inputV totheleftinvertermakesatransition
IN

from1to0,itenablescurrenttoflowthrough
thepulluptotheoutputnodeandchargethis
capacitance,atarateproportionaltothecurrentflowthroughtheenabledpullup.Thiscurrent
islimitedbythenonzeroonresistanceofthe
enabledPFET,aswellasparasiticresistanceof
thewiringitself.Theresultisanexponential
riseoftheoutputvoltagetowardV whose DD

timeconstantistheproductofthecapacitance
C andtheresistance,muchliketheexampleof

Section4.3.1.Whenadeviceoutputchanges

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fromalogical0toalogical1,wewillobservean
exponentialriseorfalltowardthetargetvalue
weoftenrefertothetimetakenforthiscurveto
gofromavalid0toavalid1astherisetimeof
thesignal,andtothetimingofitsopposite
transitionasthefalltime.Therewilltypicallybe
abriefdelaypriortotheriseorfalltime
correspondingtothepropagationofachanged
inputvaluethroughtheaffectedpullupand
pulldowntransistorsasshowntotheright.

6.4.4. Delay specifications

ThecombinationaldeviceabstractionofChapter5,basedasitisontheidealizedcircuit
theoreticmodelofcomponentsconnectedbyequipotentialnodes,requiresthatwebundlethe
timingbehaviordiscussedinthepriorsectionintothet andt timingspecificationsof
PD CD

devicesdrivingeachdigitaloutputnode.

Thecontaminationdelayt specifiesalowerboundonthetimeapreviouslyvalidoutputwill
CD

remainvalidafteraninputchangewechoosethisparametertoconservativelyreflectthe
minimumintervalrequiredforaninputchangetopropagatetoaffectedtransistorsandbegin
theirturnon/turnofftransition.Oftenwespecifycontaminationdelayaszero,whichisalwaysa
safeboundincertaincriticalsituations,wechooseaconservativenonzerovaluetoguaranteea
smalldelaybetweeninputandoutputinvalidity.

Sincethepropagationdelayt PD specifiesanupperboundonthetimebetweenaninput
stimulusandavalidoutputlevel,itshouldbechosentoconservativelyreflectthemaximum
delay(includingtransistorswitchingtimesandoutputrise/falltimes)weanticipate.Wemight
makethisselectionaftertestingmanysamplesunderavarietyofoutputloadingand
temperaturecircumstances,extrapolatingourworstcaseobservationstocomeupwitha
conservativet PD specification.

Thet PD /t CD timingmodelgivesourdigitalabstractionsimpleandpowerfulanalysistools,
includingtheabilitytodefineprovablyreliablecombinationalcircuits(thesubjectofSection
5.3.2)aswellassequentiallogic(Chapter8).However,itsquarelyconfrontsthemajordilemma
previewedinSection4.5.2:theabstractionofspacefromthecircuittheoreticmodelofsignal
timing.Inpractice,thetimingoftheoutputofaCMOSgatedependsnotonlyonintrinsic
propertiesofthegateitself,butalsoontheelectricalloadplacedonitsoutputbyconnected
devicesandwiring.Thedelaybetweenaninputchangetoaninverteranditsconsequentvalid
outputcannotrealisticallybeboundedbyaninverterspecificconstant:itdependsonthelength
androutingofconnectedwiresandotherdeviceinputs.Thefactthatwirelengthsandrouting
aredeterminedlateintheimplementationprocessdistinguishesthesefactorsas
implementationdetailsratherthanpropertiesofaspecifieddigitalcircuit,afactthatsimply
violatestheconstraintsofourdigitalcircuitabstraction.

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Fortunately,thepropertiesofCMOSasanimplementationtechnologyofferopportunitiesto
reachaworkablecompromisebetweenthesimplicityandpowerofourpropagationdelaytiming
modelandrealisticphysicsofdigitalsystems.Inparticular,thefactthatCMOSdevicesdrawno
steadystateinputcurrentimpliesthattheoutputofaCMOSgatewilleventuallyreachitsvalid
outputvalueitssimplynotpracticaltoboundthetimethiswilltakewithoutconsiderationof
wiringandloadingdetails.Thuswecandesigncircuitsusing"nominal"valuesfort PD

specificationschosenusinglightloadinganddesigncircuitsthatwilloperateproperlybut
whoseoveralltimingspecificationsmayturnouttobeoptimisticoncewiringistakeninto
account.InSection8.3.3,wedescribeanengineeringdisciplinefordesigningsystemswitha
singletimingparameteraclockperiodthatcontrolsthetradeoffbetweencomputational
performanceandtheamountoftimeallowedforsignalsoneverycircuitnodetosettletotheir
targetvalues.Systemswedesignusingthisdisciplinewillbeguaranteedtoworkforsome
(sufficientlyslow)settingofthisparameter,assketchedinSection4.5.2.1.

Wewillrevisitthisissueinlaterchapters.Fornow,wewillassignnominalpropagationdelaysto
devices,anddesignandanalyzeourcircuitsusingthefictitiouspromisemadeontheirbehalfby
thecombinationaldeviceabstraction.

6.5. Power Consumption

AnattractivefeatureofCMOStechnologyfordigitalsystemsisthefactthat,onceitreachesa
staticequilibriumandallcircuitnodeshavesettledtovalidlogiclevels,nocurrentflowsand
consequentlynopowerisdissipated.Thispropertyimpliesthatthepowerconsumptionofa
CMOScircuitisproportionaltotherateatwhichsignalschangelogiclevels,henceideally
totherateatwhichusefulcomputationisperformed.

TheprimarycauseofcurrentflowwithinaCMOScircuitistheneedtochargeanddischarge
parasiticcapacitancesdistributedamongthenodesofthatcircuit,andtheprimarymechanism
forenergyconsumptionisthedissipationofenergy(intheformofheat)duetoohmiclossesas
thesecurrentsflowthroughtheincidentalresistancesinwiresandtransistors.

Consider,forexample,theoperationoftheCMOSinverter
showntotherightasitsinputvoltageswitchesfromavalid0
toavalid1andbackagaintoavalid0.Theoutputnodeis
inevitablycoupledtoground(aswellasV andperhaps DD

othersignalwires)bysomeparasiticcapacitance,shownin
thediagramasalumpedcapacitortoground.IftheinitialV IN

iszero(correspondingtoavalidlogical0),theequilibrium
VOU T isV atthisstaticequilibrium,nocurrentflows,but
DD

thechargedcapacitorhasastoredenergyofC V /2joules, 2
DD

whereC isthetotalcapacitance.IfV nowmakesatransitiontoV (avalid1),thepullup

IN DD

PFETopensandthepulldowncloses,providingalowresistancepathbetweentheoutputnode
andgroundthecapacitancedischargesthroughthispath,untilitreachesitsnewequilibrium
VOU T = 0 .Thecapacitornowhasbeendischargedtozerovolts:ithaslosttheC V
DD
2
/2 joules

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ofenergyitpreviouslystored.Thisenergyhasinfactbeenconvertedtoheatbytheflowof
currentthroughtheresistancealongitsdischargepath.

Asubsequent1 0 transitiononV IN willopenthepulldownandclosethepullup,chargingthe

outputcapacitancebacktoV anddissipatinganotherC V /2joulesbyohmiclossesfrom
DD
2
DD

thenecessarycurrentflow.Thetotalenergydissipationfromthis0 1 0cycleisC V 2
DD

joules.

SimilarenergylossesoccurateachnodeofacomplexCMOScircuit,atratesproportionaltothe
frequencyatwhichtheirlogicvalueschange.IfweconsiderasystemcomprisingN CMOSgates
cyclingatafrequencyoff cycles/second,theresultingpowerconsumptionisontheorderof
f N C V watts.Asarepresentativeexample,aCMOSchipcomprising10 gatesdriving
2
DD
8

anaverageoutputcapacitanceof10 faradsusingV 15
DD = 1 voltandoperatingatagigahertz(
10 )frequencywouldconsumeabout10 10 10 = 100wattsofpower,allconverted
9 8 9 15 2
1

toheatthatmustbeconductedawayfromthechip.

Theconstraintofpower(andconsequentcooling)costshasbeenaprimemotivatorfor
technologyimprovements.Historictrendshavedriventhenumberofgates/chiphigher(dueto
Moore'slawgrowthintransistorsperchip),anduntilrecentlyoperatingfrequencieshave
increasedwitheachgenerationoftechnology.Thesetrendshavebeenpartiallyoffsetbyscaling
ofCMOSdevicestosmallersize,withproportionatedecreasesincapacitance.Lowering
operatingvoltagehasbeenaparticularpriority(duetothequadraticdependenceofpoweron
voltage),butthecurrent1voltrangemaybeclosetothelowerlimitforreasonsrelatedtodevice
physics.

6.5.1. Must computation consume power?

Thecostsofenergyconsumption(andrelatedcostofcooling)haveemergedasaprimary
constraintontheassimilationofdigitaltechnologies,andareconsequentlyanactiveareaof
research.

Alandmarkintheexplorationoffundamentalenergycostsofcomputationwasthe1961
observationbyRolfLandauerthattheactofdestroyingasinglebitofinformationrequiresat
leastk T ln2joulesofenergy,wherekistheBoltzmannconstant(1.38 10 J/K),T isthe 23

absolutetemperatureindegreesKelvin,andln2isthenaturallogarithmof2.Theattachement
ofthislowerlimittothedestructionofinformationimpliesthatthecostmightbeavoidedby
buildingsystemsthatarelosslessfromaninformationstandpoint:ifinformationlossimplies
energyloss,akeytoenergyefficientcomputationsistomakethempreserveinformation.

Landauerandothersproposedthatlowenergycomputationsbe
performedusingonlyinformationpreservingoperations.They
observedthatforcommonfunctionslikeNANDortheexclusive
or(XOR)showntotheleftcomprising2bitsofinput
informationbutproducingasingleoutputbitinformationis
necessarilylost:theinputscannotbereconstructedfromthe

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outputvalues.ConsequentlyoneachXORoperationsomeinformationislost,withthe
consequentaccruedenergycostasdictatedbytheLandauerlimit.Ifhoweverwerestrictour
basiclogicaloperationstoinformationpreservingfunctions
liketheFeynmangateshowntotheright,andcarefully
preservealloutputinformation(eventhatnotrequiredforour
computation),wemightavoidthisenergypenalty.Notethat
theQoutputoftheFeynmangatecarriesthesame
informationastheoutputoftheXORgate,buttheadditional
P outputdisambiguatestheinputcombinationgeneratingthisoutput.

Landauerandhisdisciplesobservedthatsuchlosslesscomputationcanbemadereversible:
sincenoinformationislostineachstepofthecomputation,itmayberunbackwardaswellas
forward.Althoughconstructionofacompletelyreversiblecomputersystempresentssome
interestingchallenges(e.g.input/outputoperations),itisconceptuallyfeasibletoperform
arbitrarilycomplexcomputationsreversibly.Imagine,forexample,anintricateandtime
consuminganalysisthatproducesavaluablesinglebitresult.Westartthiscomputationona
reversiblecomputerinsomepristineinitialstate,perhapswithalargememorycontainingonly
zeros.Asthecomputationprogressesusingreversibleoperations,extraneousoutputsaresaved
inthememory,whichgraduallyfillswithuninterestingdata.Duringthisprocess,wemaypump
energyintothecomputertoeffectitsstatechanges,buttheoreticallynoneofthisenergyis
dissipatedasheat.Whenwehavecomputedouranswer,wewriteitout(irreversibly)atatiny
energycost.Wethenrunourcomputationinreverse,usingthestoredextraneousdatatostep
backwardsinourcomputationintheprocess,wegetbackanyenergywespentduringthe
forwardcomputation.Whenthebackwardphaseiscompleted,themachinestatehasbeen
returnedtoitspristineinitialstate(readyforanothercomputation),wehaveouranswer,and
theonlyessentialenergycosthasbeenthetinyamountneededtooutputtheanswer.

Suchthoughtexperimentsinreversiblecomputationseem(andare)somewhatfarfetched,but
provideimportantconceptualmodelsforunderstandingtherelationbetweenlawsofphysics
andthoseofinformation.Reversiblecomputingplaysanimportantroleincontemporary
research,forexampleintheareaofquantumcomputing.

6.6. Further Reading

Moore,G.,"CrammingMoreComponentsontoIntegratedCircuits",Electronics,v36no8,
April19,1965.1965paperobservingthattheoptimaltransistorcountforachipseemedto
doubleevertwoyears,andpredictingthatgrowthratetocontinuefor"atleast10years".
ThisconservativepredictionpredatesthepopularityofCMOS(andmanyothersubsequent
technologicalbreakthroughs),andhascometobeknownasMoore'sLaw.
Landauer,Rolf,"Irreversibilityandheatgenerationinthecomputingprocess",IBMJ.
ResearchandDevelopment,1961.1961paperexploringthetheoreticallimitofenergy
consumptionofcomputation.Establishesalowerboundontheenergycostoferasingabit
ofinformation,andhenceofirreversiblecomputation.

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6.7. Chapter Summary

TheCMOStechnologydescribedinthischapterhasbecomethetoolofchoiceforimplementing
largedigitalsystems,andforanumberofgoodreasons:

Effectivemanufacturingtechniquesalloweconomicalmanufactureofreliabledevices
containingbillionsoflogicelements
QuiescentCMOScircuitshavevirtuallyzeropowerdissipation
CMOSgatesarenaturallylenientcombinationaldevices.

KeyelementsoftheCMOSengineeringdisciplineinclude:

Theuseofcomplementarytransistortypes,NFETsandPFETs,withineachCMOSgate
EachCMOSoutputisacircuitnodeconnectedtoanNFETbasedpulldowncircuitaswell
asaPFETbasedpullupcircuit,whereforeverycombinationofinputseitherthepullup
connectstheoutputtoV orthepulldownconnectstheoutputtoground
dd

EachsingleCMOSgateisnaturallyinverting:positiveinputtransitionscancauseonly
negativeoutputtransitions,andviceversa.Hencecertainlogicfunctionscannotbe
implementedasasingleCMOSgateandrequiremultiplegateimplementations
Highgainintheactiveregionallowslargenoisemargins,hencegoodnoiseimmunity.
Transitionstaketime:pumpingchargeintooroutofanoutputnodeiswork(inthe
physicalsense)andcannothappeninstantaneously.Thisleadstofiniteriseandfalltimes,
whichweaccommodateinourt specifications.
pd

AlthoughsingleCMOSgatesarenaturallylenient,weobservethatacycliccircuitsofCMOSgates
arenotnecessarilylenient.IflenienceisrequiredofaCMOScircuit,itcanbeassuredbyan
appropriatedesigndiscipline.

Lastrevised2015043013:40:14ward
Copyright2016M.I.T.DepartmentofElectricalEngineeringandComputerScience
Youruseofthissiteandmaterialsissubjecttoourtermsofuse.

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