[Nov-13]

[EUREC-731]
B.Tech. Degree Examination
Electronics & Communication Engineering
VII SEMESTER
DIGITAL DESIGN THROUGH VERILOG
(Effective from the admitted batch 200708)
Time: 3 Hours Max.Marks: 60
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Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
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UNIT-I
1. a) Explain in detail about functional verification 6
b) Explain about the problem experienced at the time of debugging 6
OR
2. Explain the following term:
a) Programming Language interface (key functions)
b) Module 12
UNIT-II
3. a) Explain continuous assignments and strengths with example 6
b) Explain delays with continuous assignments 6
OR
4. Write a verilog behavioral description of a four bit adder module,
the adder should have three inputs a,b and c in, and two out puts
sum and c out. Ports c in and c out are one bit; the other ports are
four bits each 12
UNIT-III
5. a) Design a half adder module with time delay assignment
through parameter declaration 6
b) Write test bench, simulation results for the above 6
 OR
6. a) Design a D-flip flop using NAND gates 6
b) Write a verilog code for D flip flop using NAND gates 6
UNIT-IV
7. a) Explain the linked sate machine 6
b) Explain the linked SM charts to Dice game 6
OR
8. a) Explain Dice game using microprogramming 6
b) Design SM chart with Moore outputs and one test per state 6
UNIT-V
9. Explain UART design
a) Serial data transmission 6
b) Standard serial data format 6
OR
10. Design HDL module for UART transmitter 12

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