GATE Questions On MOSFET, CMOS & Introduction To VLSI (1987 To Till Date)

7/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET, CMOS &
amp; Introduction to VLSI (1987 to Till Date)
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Wednesday, October 29, 2014
GATE Questions on MOSFET, CMOS & Introduction

to VLSI (1987 to Till Date)
1988
1. In MOSFET devices, the N-channel type is better than the P-channel type in the
following respects
a. It has better noise immunity
b. It is faster
c. It is TTL compatible
d. It has better drive capability
Answer: B & D
Solution : https://www.youtube.com/watch?v=i0tBM4SR3ug
1989
1. In a MOSFET, the polarity of the inversion layer is the same as that of the
a. Charge on the gate electrode
b. Minority carriers in the drain
c. Majority carriers in the substrate
d. Majority carriers in the source
Answer: D
Solution : https://www.youtube.com/watch?v=EoJQBXa0NT0
1990
1. Which of the following effects can be caused by a rise in the temperature ?
a. Increase in MOSFET current
b. Increase in BJT current
c. Decrease in MOSFET current
d. Decrease in BJT current
Answer: B & C
Solution : https://www.youtube.com/watch?v=BoRoLQ2eN6o
Facebook 1991
1. In the figure shown, the n-channel MOSFETs are identical and their current voltage
GATEpaper.in characteristics are given by the following expressions.
Like Page 3.7k likes Find the current IDC as shown
Be the first of your friends to like this
Adsense
Answer: 1 mA
Solution : https://www.youtube.com/watch?v=VPgDjeUybI4
1992
http://www.gatepaper.in/2014/10/gate-questions-on-mosfet-cmos.html 1/18
7/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET, CMOS & Introduction to VLSI (1987 to Till Date)
1. An n-channel MOSFET having a threshold voltage of 2 volts is used in the circuit shown
in figure. Initially the transistor is OFF and is in steady state. At time t = 0, a step
voltage of magnitude of 4 volts is applied to the input so that the MOSFET turns ON
instantaneously.
Draw the equivalent circuit and calculate the time taken to the output Vo to fall to 5
volts.
The device constant of the MOSFET, K = 5 mA/ V2, CDS =0 and CDG = 0.
Answer: 138 nSec

Solution : https://www.youtube.com/watch?v=ccRFcF5_sQQ
1994
1. The threshold voltage of an n-channel MOSFET can be increased by
a. Increasing the channel dopant concentration
b. Reducing the channel dopant concentration
c. Reducing the gate oxide thickness
d. Reducing the channel length
Answer: A
Solution : https://www.youtube.com/watch?v=1C8CrsGguu0
2. The transit time of the current carriers through the channel of an FET decides its
. characteristics.
GATEpaper's Treasure
Answer: Switching
2016 (19)
Solution : https://www.youtube.com/watch?v=vQJjmHNsn3I
2015 (34)
2014 (143)
3. Channel current is reduced on application of a more positive voltage to the gate of a
December (14) depletion mode n-channel MOSFET. (TRUE / FALSE)
November (12) Answer: False
Solution : https://www.youtube.com/watch?v=W34kWifl15o
October (20)
GATE Practice Problems on JFET (Junction Field
Eff...
4. A typical CMOS inverter has the voltage transfer characteristic (VTC) curve as
GATE Questions on MOSFET, CMOS & shown in the figure. Evaluate the value of the inverter threshold VINV, which is
Introduction to V...
the value of the input at which Vo falls by Vo = VTn + VTp.
GATE Questions on Junction Field Effect
Transistor...
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(B...
GATE Questions on "Zener Diode" (1987 to Till
Date...
GATE Questions on "Special Purpose Diodes
(Tunnel ...
GATE Questions on "PN Junction (Diode)" (1987
to T...
GATE Questions on "Semiconductors (Intrinsic &
Ext...
GATE 1989 ECE Analog Circuits (Analog
Electronics)...
Electronics)...
Electronics)...
Answer: 2.5 Volts
Electronics)... Solution : https://www.youtube.com/watch?v=7om91pj90XE

1995
Electronics)...
GATE 1992 ECE Analog Circuits (Analog 1. Calculate the capacitance of a circular MOS capacitor, of 0.5 mm dia and having a SiO2
Electronics)... layer of 80 mm thickness, under strong accumulation. Assume the relative dielectric
GATE 1993 ECE Analog Circuits (Analog constant of SiO2, r = 4 and o = 8.854 X 10-14 F/cm. calculate the breakdown voltage
Electronics)...
of the capacitor if the dielectric strength of SiO2 film is 107 V/cm.
GATE 1994 ECE Analog Circuits (Analog Answer: 80 Volts
Electronics)... Solution : https://www.youtube.com/watch?v=tAtC_pW9Bcw
Electronics)...
GATE 1996 ECE Analog Circuits (Analog 1996
Electronics)...
GATE Pratice Questions on "Digital Circuits - 1"
1. The n-channel MOSFET shown in figure is used as a voltage variable resistor.
Determine the expression for the resistance and compute its value for Vi. Neglect body
GATE practice Problems on PN junction (Diode) effect.
Set ... MOSFET Data :
Threshold voltage, VT = 1 volt
September (7)
Channel Length Modulation parameter, = - 0.3 V-1
August (8) Transconductance parameter, KN(W/L) = 40 A/V2
July (5)
June (6)
May (20)
April (27)
March (24)
Answer: 25 k (without CLM), 7.5 k (with CLM)

Solution : https://www.youtube.com/watch?v=f5B96mqdE7I
2. A Silicon N-channel MOSFET has a threshold voltage of 1 volts and oxide thickness
of 400 Ao. [r (SiO2) = 3.9, o = 8.854 x 10-14 F/cm, q = 1.6 x 10-19]. The region
under the gate is ion implanted for threshold voltage tailoring. The doping and type of
the implant (assumed to be a sheet charge at the interface) required to shift the
threshold voltage to -1 volt are
a. 1.08 x 1012/cm3, P type

b. 1.08 x 1012/cm3, N -type
c. 5.4 x 1011/cm3, P -type
d. 5.4 x 1011/cm3, N -type
Answer:
Solution :
3. An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ poly silicon
gate and the threshold voltage was found to be 1 volt. Now if the gate is changed to P+
poly silicon, other things remaining the same, the new threshold voltage should
be..volts.
a. -0.1
b. 0
c. 1.0
d. 2.1
Answer: D
Solution : https://www.youtube.com/watch?v=JWuLWh-pz1c
1997
1. For a MOS capacitor fabricated on a P-type semiconductor, strong inversion occurs
when
a. Surface potential is equal to Fermi level
b. Surface potential is zero
c. Surface potential is negative is negative and equal to Fermi potential in
magnitude
d. Surface potential is positive and equal to twice the Fermi potential
Answer: D
Solution : https://www.youtube.com/watch?v=351K-p6NM-k
2. The gate delay of an NMOS inverter is dominated by charge time rather than
discharge time because
a. The driver transistor has larger threshold voltage than the load transistor
b. The driver transistor has larger leakage currents compared to the load
transistor
c. The load transistor has a smaller W/L ratio compared to the driver transistor
d. None of the above
Answer: C
Solution : https://www.youtube.com/watch?v=D2kfxsy-ypk
3. Given NMOS circuit as shown. The specifications of the circuit are :

VDD = 10 volts, = nCox(W/L) = 10-4 Amp/V2, VT = 1 volt and IDS = 0.5 mA.
Evaluate VDS and RD. Neglect body effect.
Answer: 4.15 Volts, 11.68 k

Solution : https://www.youtube.com/watch?v=Uc3EuOto9Pk
1998
1. The threshold voltage for each transistor in figure is 2 volts. For this circuit to work
as an inverter, Vi must take the values
a. -5 volts and 0 volts

b. -5 volts and 5 volts
c. 0 volts and 3 volts
d. 3 volts and 5 volts
Answer: A
Solution : https://www.youtube.com/watch?v=pHfKL4yw4Ko
1999
1. In the CMOS inverter circuit shown in figure, the input Vi makes a transition from
VOL (= 0 volts) to VOH (= 5 volts). Determine the High to Low propagation delay time
(tpHL) when it is driving a capacitive load (CL) of 20 pF.
Device data :
Answer: 0.156 Sec

Solution : https://www.youtube.com/watch?v=0t8YIeh7E_0
2001
1. MOSFET can be used as a

a. Current controlled capacitor
b. Voltage controlled capacitor
c. Current controlled inductor
d. Voltage controlled inductor
Answer: B
Solution : https://www.youtube.com/watch?v=DYvtwvbyh8Q
2. The effective channel length of a MOSFET in saturation decreases with increase in

a. Gate voltage
b. Drain voltage
c. Source voltage
d. Body voltage
Answer: B
Solution : https://www.youtube.com/watch?v=yySAOIv7hiw
2002
1. Consider the following statements in connection with the CMOS inverter in figure,
where both the MOSFETs are of enhancement type and both have a threshold voltage
of 2 volts.
S1: T1 conducts when VI 2 volts.

S2: T1 is always in saturation when Vo = 0 volts.
Which of the following is correct.
a. Only S1 is TRUE
b. Only S2 is TRUE
c. Both are TRUE
d. Both are FALSE
Answer: A
Solution : https://www.youtube.com/watch?v=lm9CG4kv7NU
2003
1. For an N channel type MOSFET, if the source is connected at a higher potential than
that of the bulk (i.e. VSB > 0 volts), the threshold voltage VT of the MOSFET will
a. Remain unchanged
b. Decrease
c. Change polarity
d. Increase
Answer: D
Solutoin : https://www.youtube.com/watch?v=NkWeND6-BxI
2. When the gate to source voltage (VGS) of a MOSFET with threshold voltage of 400 mV.
The drain current observed is 1 mA. Neglecting the channel length modulation effect,
and assuming that the MOSFET is operating at saturation, the drain current for an
applied VGS of 1400 mV is
a. 0.5 mA
b. 2.0 mA
c. 3.5 mA
d. 4.0 mA
Answer: D
Solutoin : https://www.youtube.com/watch?v=jvXncirhK9c
3. If P is passivation, Q is n-well implant, R is metallization and S is source/drain

diffusion, then the order in which they are carried out in a standard n-well CMOS
fabrication process is
a. P-Q-R-S
b. Q-S-R-P
c. R-P-S-Q
d. S-R-Q-P
Answer: B
Solutoin : https://www.youtube.com/watch?v=dS__KGppUig
2004
1. The given figure is the voltage transfer characteristic of
Answer: C
Solution : https://www.youtube.com/watch?v=lPY4XzAWeSg
2. Consider the following statements S1 and S2.

S1: the threshold voltage (VT) of a MOS capacitor decreases with increase in gate oxide
thickness
S2: the threshold voltage (VT) of a MOS capacitor decreases with increase in substrate
doping concentration.
Which of the following is correct?
a. S1 is FALSE and S2 is TRUE

b. Both S1 and S2 are TRUE
c. S1 is TRUE and S2 is FALSE
d. Both S1 and S2 are FALSE
Answer: D
Solution : https://www.youtube.com/watch?v=jmKFRCr0xa0
3. The drain of an N channel MOSFET is shorted to the gate so that VGS = VDS. The
threshold voltage (VT) of MOSFET is 1 volt. If the drain current (ID) is 1 mA for VGS =
2 volts, then for VGS = 3 volts, ID is
a. 2 mA
b. 3 mA
c. 9 mA
d. 4 mA
Answer: D
Solution : https://www.youtube.com/watch?v=F1cZOGLgZIA
2005
1. An N-channel MOSFET and its transfer curve is shown in figure, then the threshold
voltage is
Answer: C
Solution : https://www.youtube.com/watch?v=UYrsnu-QIlU
2. Both transistors T1 and T2 in figure have a threshold voltage of 1 volt. The device
parameters K1 and K2 of T1 and T2 are 36 A/v2 and 9 A/v2 respectively. The output
voltage Vo is
Answer: C
Solution : https://www.youtube.com/watch?v=6fIMwxzffIo
3. A MOS capacitor made using P type substrate is in the accumulation mode. The
dominant charge is due to the presence of
a. Holes
b. Electrons
c. Positively charged ions
d. Negatively charged ions
Answer: A
Solution : https://www.youtube.com/watch?v=jlQ_ny0L4C0
2006
1. An N-channel depletion MOSFET has the following two points on its ID verses VGS
curve are
(i) VGS = 0 at ID = 12 mA and
(ii) VGS = -6 volts at ID = 0 mA
Which of the following Q-points will give the highest Transconductance gain for small
signals?
a. VGS = -6 volts
b. VGS = -3 volts
c. VGS = 0 volts
d. VGS = 3 volts
Answer: D
Solution : https://www.youtube.com/watch?v=Kxd4IZqv1vU
2007
1. Group I lists four different semiconductor devices. Match each device in Group I with
its characteristic property in Group II.
Answer: C
Solution : https://www.youtube.com/watch?v=iwERJKn2hUU
2. In the CMOS inverter circuit shown, if the Transconductance parameters of the

NMOS and PMOS transistors are Kn = Kp = nCox(Wn/Ln) = pCox(Wp/Lp) = 40
A/V2 and their threshold voltages are VTn = |VTp| = 1 volt, the current I is
a. 0 Amp
b. 25 A
c. 45 A
d. 90 A
Answer: D
Solution : https://www.youtube.com/watch?v=wtboLpHXLOA
3. The figure shows the high frequency capacitance voltage (C V) characteristics of

MOS capacitor having an area of 1x10-4 cm2. Assume that the permittivity of silicon
and SiO2 are 1x10-12 and 3.5x10-13 F/cm respectively.
i. The gate oxide thickness in the MOS capacitor is

a. 50 nm
b. 143 nm
c. 350 nm
d. 1 m
Answer: A
ii. The maximum depletion layer width in silicon is
a. 0.143 m
b. 0.857 m
c. 1 m
d. 1.143 m
Answer: B
iii. Consider the following statements about the C V characteristics plot :
S1: The MOS capacitor has an N type substrate
S2: If the positive charges are introduced in the oxide, the C V plot will shift to
the left.
Then which one of the following is TRUE .
a. Both S1 and S2 are TRUE
b. S1 is TRUE and S2 is FALSE
c. S1 is FALSE and S2 is TRUE
d. Both S1 and S2 are FASLE
Answer: C
Solution : https://www.youtube.com/watch?v=IKyIj6hVTL8
2008
1. A silicon wafer has 100nm of oxide on it and is inserted in a furnace at a temperature

above 1000oC for further oxidation in dry oxygen. The oxidation rate
a. Is independent of current oxide thickness and temperature
b. Is independent of current oxide thickness but depends on temperature
c. Slows down as the oxide grows
d. Is zero as the existing oxide prevents further oxidation
Answer: A
Solution : https://www.youtube.com/watch?v=6yl7336P2kA
2. The drain current of a MOSFET in saturation is given by ID = K(VGS-VT)2, where K is

a constant. The magnitude of the Transconductance gm is
Answer: B
Solution : https://www.youtube.com/watch?v=pYDNlQanv2g
3. For the circuit shown in the following figure, transistors M1 and M2 are identical
NMOS transistors. Assume that M2 is in saturation and the output is unloaded. The IX
is related to Ibias as
Answer: B
Solution : https://www.youtube.com/watch?v=CBXqcvlx97A
4. The measured Transconductance gm of an NMOS transistor operating in the linear

region is plotted against the gate voltage VG at constant drain voltage VD. Which of the
following figures represents the expected dependence of gm on VG?
Answer: A
Solution : https://www.youtube.com/watch?v=KE_MLvt-M-4
5. Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is
chosen so that both transistors are in saturation. The equivalent gm of the pair is
defined to be dIout / dVi at constant Vout, is
a. The sum of individual gms of the transistors

b. The product of individual gms of the transistors
c. Nearly equal to the gm of M1
d. Nearly equal to gm1/gm2 of M2
Answer: C
Solution : https://www.youtube.com/watch?v=oySwKD3Vtjg
2009
1. The full forms of the abbreviations TTL and CMOS in reference to logic families are
a. Triple Transistor Logic and Chip Metal Oxide semiconductor
b. Tristate Transistor Logic and Chip Metal Oxide semiconductor
c. Transistor Transistor Logic and Complementary Metal Oxide semiconductor
d. Tristate Transistor Logic and Complementary Metal Oxide semiconductor
Answer: C
Solution : https://www.youtube.com/watch?v=v-0BYB0NkMI
2. Consider the following two statements about the internal conditions in an N channel
MOSFET operating in the active region.
S1: the inversion charge decreases from source to drain
S2: the channel potential increases from source to drain
Which of the following is correct?
a. Both are TRUE
b. Both are FALSE
c. Both are TRUE, but S2 is not a reason for S1
d. Both are TRUE, and S2 is a reason for S1.
Answer: D
Solution : https://www.youtube.com/watch?v=qbq2JXNCe_Q
3. Linked Questions:
Consider the CMOS circuit shown, where the gate voltage VG of the N channel
MOSFET is increased from zero, while the gate voltage of the P channel MOSFET is
kept constant at 3 volts. Assume that, for both transistors, the magnitude of the
threshold voltage is 1 volts and the product of the transconductance parameter and the
(W/L) ratio i.e. the quantity cox(W/L) is 1 mA/V2.
i. For small increase in VG beyond 1 volt, which of the following gives

the correct description of the region of operation of each MOSFET?
a. Both are in saturation region
b. Both are in triode region
c. NMOS is in triode region and PMOS is in saturation region
d. NMOS is in saturation region and PMOS is in triode region
Answer: D
ii. Estimate the output voltage, Vo for VG = 1.5 volts. (Hint: use the
appropriate current voltage equation for each MOSFET, based on the answer to above
question)
Answer: C
Solution : https://www.youtube.com/watch?v=_BU3wB8FoBA
2010
1. At room temperature, a possible value for the mobility of electrons in the inversion
layer of a silicon N channel MOSFET is (in cm2/volt-sec)
a. 450
b. 1350
c. 1800
d. 3600
Answer: B
Solution: https://www.youtube.com/watch?v=bXxmszDCh1U
2. The gate oxide in a CMOS process is preferably grown using

a. Wet oxidation
b. Dry oxidation
c. Epitaxial deposition
d. Ion implantation
Answer: B
Solution : https://www.youtube.com/watch?v=7bi7sXWZYEc
2011
1. In the circuit shown below, for the MOS transistors, ncox = 100 A/V2 and the
threshold voltage VT = 1 volt. The voltage VX at the source of the upper transistor is
a. 1 volt
b. 2 volts
c. 3 volts
d. 0.367 volts
Answer: C
Solution : https://www.youtube.com/watch?v=4J00rSwlU6U
2012
1. In the circuit shown below, the output expression Y is
Answer: A
Solution : https://www.youtube.com/watch?v=AOa8cOFX7WA
2. In the CMOS circuit shown, electron and hole motilities are equal, and M1 and M2
transistors are equally sized. The device M1 is in the linear region if
Answer: A
Solution : https://www.youtube.com/watch?v=Geh8HiqWIoU
3. In the three dimensional view of a silicon N channel MOS transistor shown below,
= 20 nm. The transistor is of width 1 m. The depletion width formed at every PN
junction is 10 nm. The relative permittivitys of Si and SiO2 are 11.7 and 3.9
respectively and 0 = 8.9 X 10-12 F/m.
i. The gate source overlap capacitance is approximately

a. 0.7 fF
b. 0.7 pF
c. 0.35 fF
d. 0.24 fF
Answer: A
ii. The source body capacitance approximately
a. 2 fF
b. 7 fF
c. 2 pF
d. 7 pF
Answer: B
Solution : https://www.youtube.com/watch?v=60X82BxUfd8
2013
1. In IC technology, Dry oxidation(using dry oxygen) as compared to Wet oxidation

(using stream or water vapor) produces..
a. Superior quality oxide with a higher growth rate
b. Inferior quality oxide with a higher growth rate
c. Inferior quality oxide with a lower growth rate
d. Superior quality oxide with a lower growth rate
Answer: D
Solution : https://www.youtube.com/watch?v=EEcf8aHius8
2. In MOSFET operating in saturation region, the channel length modulation effect

causes
a. An increase in gate source capacitance
b. A decrease in Transconductance
c. A decrease in unity gain bandwidth product
d. A decrease in output resistance
Answer: D
Solution : https://www.youtube.com/watch?v=9QAOSh8OjSY
2014
Set 1 (15th February 2014 (Forenoon))
1. If the fixed positive charges are present in the gate oxide of an N channel
enhancement type MOSFET, it will lead to
a. a decrease in the threshold voltage
b. channel length modulation
c. an increase in substrate leakage current
d. an increase in accumulation capacitance
Answer: A
Solution : https://www.youtube.com/watch?v=em0VvbA7po4
2. A depletion type N channel MOSFET is biased in its linear region for use as a voltage
controlled resistor. Assume threshold voltage VTH = -0.5 volts, VGS = 2.0 volts, VDS
= 5 volts, W/L = 100, Cox = 10-8 F/cm2 and n = 800 cm2/volt-sec. The value of the
voltage controlled resistor (in ) is ..
Answer: 500
Solution : https://www.youtube.com/watch?v=xzUDuBbZUXM
SET 2 (15th February 2014 (Afternoon))
1. In CMOS technology, shallow P well or N well regions can be formed using

a. low pressure chemical vapor deposition
b. low energy sputtering
c. low temperature dry oxidation
d. low energy ion implantation
Answer: D
Solution : https://www.youtube.com/watch?v=NA-HnsA124g
2. For the N channel MOS transistor shown in the figure, the threshold voltage VTH is
0.8 volts. Neglect channel length modulation effects. When the drain voltage VD = 1.6
volts, the drain current ID was found to be 0.5 mA. If VD is adjusted to be 2 volts by
changing the values of R and VDD, the new value of ID (in mA) is
a. 0.625
b. 0.75
c. 1.125
d. 1.5
Answer: C
Solution : https://www.youtube.com/watch?v=wsv90UUqYVY
3. For the MOSFETs shown in the figure, the threshold voltage |Vt| = 2 volts and K =
0.5cox(W/L) = 0.1 mA/V2. The value of ID (in mA) is
Answer: 0.9
Solution : https://www.youtube.com/watch?v=abv9XXV0jks
SET 3 (16th February 2014 (Forenoon))
1. In MOSFET fabrication, the channel length is defined during the process of

a. Isolation oxide growth
b. Channel stop implantation
c. Poly-silicon gate patterning
d. Lithography step leading to the contact pads
Answer: C
Solution : https://www.youtube.com/watch?v=QPQ5hOdbGjE
2. The slope of the ID vs. VGS curve of an N channel MOSFET in linear region is 10-3
-1 at V = 0.1 volts. For the same device, neglecting channel length modulation, the
DS
slope of the ID vs. VGS curve (in A/V) under saturation regime is
approximately.
Answer: 0.07
Solution : https://www.youtube.com/watch?v=rDjsCvkSUtk
3. An ideal MOS capacitor has boron doping concentration of 1015 cm-3 in the
substrate. When a gate voltage is applied, a depletion region of width 0.5 m is formed
with a surface (channel) potential of 0.2 volts. Given that o = 8.854 x 10-14 F/cm and
the relative permittivitys of silicon and silicon dioxide are 12 and 4 respectively. The
peak electric field (in V/m) in the oxide region is ..
Answer: 2.4
Solution : https://www.youtube.com/watch?v=K4aRAJxegSI
4. For the MOSFET M1 shown in the figure, assume W/L = 2, VDD = 2.0 volts, ncox =
100 A/V2 and VTH = 0.5 volts. The transistor M1 switches from saturation region to
linear region when Vin (in volts) is ..
Answer: 1.5
Solution : https://www.youtube.com/watch?v=AWdemWJenw4
2015
1. Which one of the following processes is preferred to form the gate dielectric (SiO2)
of MOSFET?
a. Sputtering
b. Molecular Beam Epitaxy
c. Wet Oxidation
d. Dry Oxidation
Answer: D
Solution : https://www.youtube.com/watch?v=aT-PUfpeyOY
2. In the circuit shown, the both the enhancement mode NMOS transistors have the
following characteristics: Kn = n.Cox(W/L) = 1 mA/V2, VTN = 1 volt.
Assume that the channel length modulation parameter is zero and body is shorted to
source. The minimum supply voltage VDD (in volts) needed to ensure that
transistor M1 operates in saturation mode of operation is ___________________
Answer: 3
Solution : https://www.youtube.com/watch?v=nAvaaApnnao
3. The current in an enhancement mode NMOS transistor biased in saturation mode

was measured to be 1 mA at a drain to source voltage of 5 volts. When the drain
source voltage was increased to 6 volts, while keeping gate-source voltage same,
the drain current increased to 1.02 mA. Assume that drain to source saturation
voltages is much smaller than the applied drain source voltage. The channel length
modulation parameter (in V-1) is __________
Answer: 0.02
Solution : https://www.youtube.com/watch?v=4AebD_Jv5C8
4. For the NMOSFET in the circuit shown, the threshold voltage is Vth greater than
zero. The source voltage VSS is varied from 0 to VDD. Neglecting the channel
length modulation, the drain current ID as a function of VSS is represented by
Answer: A
Solution : https://www.youtube.com/watch?v=qipvNgPQNDM
5. A MOSFET in saturation has a drain current of 1 mA for VDS = 0.5 volts. If the channel length
modulation coefficient is 0.05 V-1, the output resistance (in k) of the MOSFET is ________
Answer: 20
Solution : https://www.youtube.com/watch?v=uFmH59NNz6s
6. In MOS capacitor with an oxide layer thickness of 10 nm. The maximum depletion layer
thickness is 100 nm. The permittivitys of the semiconductor and the oxide layer are s and ox
respectively. Assuming s/ox = 3, the ratio of the maximum capacitance to the minimum
capacitance of this MOS capacitor is ____________
Answer: 4.33
Solution : https://www.youtube.com/watch?v=eIk6sCXiKbY
Posted by GATE paper at 10:54
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Labels: GATE Questions, MOSFET, VLSI
22 comments
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Top comments
Dipali Acharya 1 year ago - Shared publicly

Thank you sir...Loved your solution
+1 1 Reply
2
Deepak Chauhan 7 months ago - Shared publicly

Tq very much sir :)
shrikant Charthal 8 months ago - Shared publicly

sir pls add communication subject
1 Reply
gurpreet singh 1 year ago - Shared publicly

vinay ... in pmos there is rule we always consider magnitude of
Mr
vt..the eq is vsd<vsg-|vt| if this eqn satis ed then pmos will be in triode
or linear region
+1 1 Reply
2
gurmeet singh 1 year ago - Shared publicly

Really So helpful.Thank you sir
mayank sharma 6 months ago - Shared publicly

Shandaar
Govind Raju 7 months ago - Shared publicly

Tq so much sir
1 Reply
Bikash kumar 7 months ago - Shared publicly

sir please give solution of electromagnetics subjects
1 Reply
Sivaramakrishna Gorla 8 months ago - Shared publicly

than q sir
1 Reply
rohit kumar 10 months ago - Shared publicly

thank you sir , very good solution
1 Reply
Saif khan 10 months ago - Shared publicly

Very important necessary things u explain,,, thanks a lot
1 Reply
Sri Kanth 11 months ago - Shared publicly

very good explanation
1 Reply
sachin koparkar 1 year ago - Shared publicly

EXCELLENT SIR
1 Reply
Veena S 1 year ago - Shared publicly

Thank u sir.U r doing a gr8 job.I cleared GATE xam with the help of ur
solutions.
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shanmuk sandeep 1 year ago - Shared publicly

so blessed with ur crystal clear solutions :)
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Dilip Kumar 1 year ago - Shared publicly

I think in1996 question 2 .
answer will be option (a)
any body have other clues
1 Reply
Pramod S 5 months ago

its 4th option
vivek singh 1 year ago - Shared publicly

Thank u very much sir :-)
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aashik ali 1 year ago - Shared publicly

thax.,,,,,,,
1 Reply
Sindhu Gaddam 1 year ago - Shared publicly

tq very much sir :)
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sanjay kumar 1 year ago - Shared publicly

Thank u
1 Reply
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GATE Questions On MOSFET, CMOS & Introduction To VLSI (1987 To Till Date)

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7/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET, CMOS &

amp; Introduction to VLSI (1987 to Till Date)

Practice Problems GATE Exam Notes

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Wednesday, October 29, 2014

GATE Questions on MOSFET, CMOS & Introduction

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Answer: 138 nSec

GATE 1991 ECE Analog Circuits (Analog

Answer: 25 k (without CLM), 7.5 k (with CLM)

a. 1.08 x 1012/cm3, P type

3. Given NMOS circuit as shown. The specifications of the circuit are :

Answer: 4.15 Volts, 11.68 k

a. -5 volts and 0 volts

Answer: 0.156 Sec

1. MOSFET can be used as a

2. The effective channel length of a MOSFET in saturation decreases with increase in

S1: T1 conducts when VI 2 volts.

3. If P is passivation, Q is n-well implant, R is metallization and S is source/drain

1. The given figure is the voltage transfer characteristic of

2. Consider the following statements S1 and S2.

a. S1 is FALSE and S2 is TRUE

2. In the CMOS inverter circuit shown, if the Transconductance parameters of the

3. The figure shows the high frequency capacitance voltage (C V) characteristics of

i. The gate oxide thickness in the MOS capacitor is

1. A silicon wafer has 100nm of oxide on it and is inserted in a furnace at a temperature

2. The drain current of a MOSFET in saturation is given by ID = K(VGS-VT)2, where K is

4. The measured Transconductance gm of an NMOS transistor operating in the linear

a. The sum of individual gms of the transistors

i. For small increase in VG beyond 1 volt, which of the following gives

2. The gate oxide in a CMOS process is preferably grown using

1. In the circuit shown below, the output expression Y is

i. The gate source overlap capacitance is approximately

1. In IC technology, Dry oxidation(using dry oxygen) as compared to Wet oxidation

2. In MOSFET operating in saturation region, the channel length modulation effect

SET 2 (15th February 2014 (Afternoon))

1. In CMOS technology, shallow P well or N well regions can be formed using

SET 3 (16th February 2014 (Forenoon))

1. In MOSFET fabrication, the channel length is defined during the process of

3. The current in an enhancement mode NMOS transistor biased in saturation mode

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Labels: GATE Questions, MOSFET, VLSI

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