ap

Ch ter
4 Logic Gates

4.1 Introduction
Logic gates are the most fundamental digital circuit that can be constructed from
diodes, transistors and registers connected in such a way that circuit output is the
result of basic logic operation (OR, AND, NOT) performed on the inputs.
A logic gate is an electronic device with one output and one or more inputs
where the output always depends on the input combinations.
Logic symbols used to represent the logic gates are in accordance with ANSI/IEEE
standard 91-1984. This standard has been adopted by private industry and the mil-
itary for use in the internal documentation as well as published literature.
Note:
1. AND, OR, NOT gates are called Basic Gates.
2. NAND and NOR gates are called universal gates, because by using only
NAND gates or by using only NOR gates, we can realise any logic gate or
any basic logic circuit.
3. Special gates are EXCLUSIVE-OR (XOR) & EXCLUSIVE-NOR (X-NOR)
gate.

4.2 Types of Logic System

(a) Positive level logic system
(b) Negative level logic system
4.2 Digital Electronics, an easy approach to learn

Positive level logic system

In positive level logic system, the most positive voltage level represents the logic
1-state and the most negative voltage level represents the logic 0-state.
1 (High)

0 (Low)

Fig. 4.1 Positive level logic

For example,
Table 4.1 Table showing different logic levels
LOGIC 0 LOGIC 1
0V 5V
-2 V +3 V
-7 V -2 V
+2 V +7 V

Negative level logic system

In a negative level logic system the most positive voltage level represents the logic
0-state and the most negative voltage level represents the logic 1-state.
High 0

Low 1

Fig. 4.2 Negative level logic

For example,
Table 4.2 Table showing different logic levels
LOGIC 1 LOGIC 0
0V 5V
-2 V +3 V
-7 V -2 V
+2 V +7 V

The effect of changing from one logic designation to other is equivalent to

complementing the logic function. The best way of converting the logic designa-
tion is that all zeros are replaced by 1 and vice versa, in the truth table.
 Logic Gates 4.3

For example, the truth table for AND gate for both the logics is given below.
Truth table for positive Truth table for negative
logic AND gate logic AND gate

Table 4.3 Truth table Table 4.4 Truth table

Input Output Input Output
A B F=A.B A B F=A.B
0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0

Note: By looking at the Tables 4.3 and 4.4, it can be concluded that negative logic
AND gate is same as positive logic OR gate.

4.3 Not Gate (Inverter)

The NOT gate performs the basic logic functions called complementation or in-
version. It has one input and one output. Its output logic level is always opposite
to the logic level of the input.
In terms of binary bits, it changes a 1 to 0 and a 0 to 1.

Symbol
A F

Presence of small circle

called bubble always
A F denotes inversion

Fig. 4.3 Symbol of NOT gate

Truth table of NOT gate

Table 4.5 Truth table of NOT gate

FACT: Common emitter
Input Output
(BJT) amplifier is used to
A F
obtain the logical opera-
0 1
tion of inverter
1 0
4.4 Digital Electronics, an easy approach to learn

Timing diagram of NOT gate

Timing diagram: It is basically a graph that accurately displays the relationship
between input and output waveforms with respect to each other on a time scale.

Input waveform

Output waveform

Fig. 4.4 Timing diagram of NOT gate

Logic expression
If A is input, then output,
F = A0

4.4 AND Gate

The AND gate may have two or more input but has only a single output. An AND
gate produces a HIGH (logic 1) output only when, all the inputs are HIGH. The
output is LOW, when any of its input is LOW.

Symbol
A F
B

Fig. 4.5 2-input AND gate

Truth table of 2-input AND gate

Table 4.6 Truth table for AND gate

Input Output
A B F
0 0 0
0 1 0
1 0 0
1 1 1

Note: Boolean multiplication is same as AND operation

 Logic Gates 4.5

Timing diagram of 2-input AND gate

F
t

Fig. 4.6 Timing diagram of 2- input AND gate

Logic expression
For a 2-input AND gate having inputs A & B, the output, F is given

F = A.B

Similarly for 3 input AND gate with inputs A, B, & C the output is given as

F = A.B.C

4.5 OR Gate
The OR gate may have two or more inputs, but has only a single output.
The OR gate produces a HIGH output, when any of its input is HIGH. The
output is low when, all the inputs are LOW.

Symbol
A F
B

Fig. 4.7 2-input OR gate

Truth table of 2-input OR gate

Table 4.7 Truth table for 2-input OR gate

Input Output
A B F=A+B
0 0 0
0 1 1
1 0 1
1 1 1

Note: Boolean addition is same as OR operation

4.6 Digital Electronics, an easy approach to learn

Timing diagram of 2-input OR gate

A
B
F
t

Fig. 4.8 Timing diagram for 2-input OR gate

Logic expression
For a 2-input OR gate having inputs A & B, output F is given by

F =A+B

Similarly for 3-input OR gate with inputs A, B, & C, the output is given as

F =A+B+C

4.6 NAND Gate

The NAND gate produces LOW output only when all the inputs are HIGH. When
any of the input is LOW, the output is HIGH.
The term NAND is the contraction of NOT-AND and implies an AND gate
followed by a NOT gate.

Symbol
A F A F
B B

Fig. 4.9 2-input NAND gate

Truth table of 2-input NAND gate

Table 4.8 Truth table for 2-input NAND gate

Input Output
A B F = (A . B)
0 0 1
0 1 1
1 0 1
1 1 0
 Logic Gates 4.7

Timing diagram of 2-input NAND gate

Fig. 4.10 Timing diagram for 2-input NAND gate

Logic expression

For a 2-input NAND gate having inputs A & B, output F is given by

F = A.B

Similarly for 3-input NAND gate with inputs A, B, & C, the output is given as

F = A.B.C

Note: NAND gate are called universal gate as any logic circuit realisation is pos-
sible by using NAND gate alone and any logic gate can also be realised in
terms of NAND gate.

4.7 NOR Gate

The NOR gate may have two or more input but has only a single output.
The NOR gate produces LOW output only when any of the inputs is HIGH
and a HIGH output, only when all of its inputs are LOW.
The term NOR is the contraction of NOT-OR and implies an OR gate followed
by a NOT gate.

Symbol
A F A F
B B

Fig. 4.11 2-input NOR gate

4.8 Digital Electronics, an easy approach to learn

Truth table of 2-input NOR gate

Table 4.9 Truth table for 2-input NOR gate

Input Output
A B F = (A + B)
0 0 1
0 1 0
1 0 0
1 1 0

Timing diagram of 2-input NOR gate

B
F
t

Fig. 4.12 Timing diagram for 2-input NOR gate

Logic expression
For 2-input NOR gate having inputs A & B, output F is given by

F =A+B

Similarly for 3-input OR gate with inputs A, B, & C, the output is given as

F =A+B+C

Note: NOR gate is called universal gate as any logic circuit realisation is possible
by using NOR gate alone and any logic gate can also be realised in terms of
NOR gate.

4.8 XOR Gate (Exclusive-OR)

The XOR operation is not a basic operation. But it can be performed by using the
basic gates (AND, OR, NOT) or the universal gates (NAND, NOR).
An XOR gate produces HIGH output for odd numbers of logic HIGH inputs.
 Logic Gates 4.9

Symbol
A F
B

Fig. 4.13 2-input XOR gate

Truth table of 2-input XOR gate

Table 4.10 Truth table for 2-input XOR gate

Input Output
A B F=AB
0 0 0
0 1 1
1 0 1
1 1 0

Timing diagram of 2-input XOR gate

B
F
t

Fig. 4.14 Timing diagram for 2-input XOR gate

Logic expression
For 2-input XOR gate having inputs A & B, output F is given by
FACT:
1. XOR gate is also called stair
F = A B = AB + AB
case switch.
Symbol of XOR 2. It is mostly used in parity gen-
eration and detection.

Note: When one of the inputs of 2 input XOR gate is at logic 0 then, the XOR
gate acts as a buffer circuit for the other input.

2 Concept: The XOR gate gives logic 1 output for odd numbers of logic 1 inputs.
4.10 Digital Electronics, an easy approach to learn

For example,

Fig. 4.15 XOR gates

The XOR gate acts like an odd number of 1s detector.

4.9 X-NOR Gate

The XNOR operation is not a basic operation. But it can be performed by using
the basic gates (AND, OR, NOT) or the universal gates (NAND, NOR).
An XNOR gate produces HIGH output when both the inputs are same.

Symbol
A The bubble on the output of the
F XNOR symbol indicates that its
B output is complement of XOR
gate.

Fig. 4.16 2-input XNOR gates

Truth table of 2-input XNOR gate

Table 4.11 Truth table for 2-input XNOR gate

Input Output
A B F = (A B)
0 0 1
0 1 0
1 0 0
1 1 1

4.10 Buffer Gate

It is a simple gate which gives the same output as that of input. It is used for the
purpose of delay.

Symbol
F
A

Fig. 4.17 Buffer gate

 Logic Gates 4.11

Truth table
A F
0 0
1 1

Graphic symbol of gates

RECTANGULAR LOGIC TRUTH
NAME DISTINCTIVE SHAPE
SHAPE EXP. TABLE

F A 1 F A
F
NOT A F=A 0 1
1 0
A B F
A
F 0 0 0
A F &
AND B F = A.B 0 1 0
B 1 0 0
1 1 1
A B F
A 0 0 0
A F F
OR B B 1 F = A+B 0 1 1
1 0 1
1 1 1
A B F
A 0 0 1
A F F
NAND B & F = A.B 0 1 1
B
1 0 1
1 1 0
A B F
A 0 0 1
A F F
NOR B B 1 F = A+B 0 1 0
1 0 0
1 1 0
A B F
A
F 0 0 0
A F =1
XOR B F=AB 0 1 1
B
1 0 1
1 1 0
A B F
A 0 0 1
A F F
XNOR B =1 F=AB 0 1 0
B
1 0 0
1 1 1

A F F A
BUFFER A F 1 F=A 0 0
GATE
1 1

Relation between XOR and XNOR

XOR function is complement of XNOR and vice-versa.
4.12 Digital Electronics, an easy approach to learn

F1=AB F2=AB
F2 = A B F1 = A B
A F A F
B B

F1 = A B F1 = A B
F2 = F1 = A B F2 = F1 = A B
=A B =AB

Fig. 4.18 Comparison of gates

Note:
1. In XOR gate when one of the input is at logic 0 then the XOR gate acts as
a buffer for the other input.
A
A
0

Fig. 4.19 XOR gate as a buffer gate

2. In XOR gate when one of the input is at logic 1 then the XOR gate acts as
an inverter for the other input.
A
A
1

Fig. 4.20 XOR gate as an inverter

Example 4.1 Show that, A B = A  B

I Solution
L.H.S, A B = AB + AB
Let B=x
So, A B = Ax + A x
=Ax
=AB
= R.H.S (Hence Proved)

Example 4.2 Show that,

1. AB + A + B = A  B

2. (A + B)(AB) = A B
 Logic Gates 4.13

I Solution
1. Proof:
L.H.S, AB + A + B = AB + A B (De Morgans law)
= A  B = R.H.S (Hence Proved)

2. Proof:
L.H.S, (A + B)(AB) = (A + B)(A + B) (De Morgans law)
= AA + AB + BA + BB
= AB + A B
=AB
= R.H.S (Hence Proved)

Example 4.3 Show the output waveforms for the 2-input AND, OR, NAND,
NOR, XNOR gate, if the inputs are given as,

A
B

Fig. 4.21(a) Input waveforms

I Solution
The output waveforms can be drawn with the help of truth table or logic expression
for each gate as,
A
B

AND
OR
NAND

NOR
XOR
XNOR

Fig. 4.21(a) Input waveforms

Example 4.4 Show the output waveforms for the 2-input AND, OR, NAND,
NOR, XNOR gate, if the inputs are given as,
4.14 Digital Electronics, an easy approach to learn

Fig. 4.22(a) Input waveforms

I Solution
The output waveforms can be drawn with the help of truth table or logic expression
for each gate as,

AND 0

OR
NAND 1

NOR

XOR

XNOR

Fig. 4.22(b) Input waveforms

4.11 IC Gates

1 14 Vcc

2 13

3 IC 12
74LS08
4 11

10
5

6 9
8
GND 7

Fig. 4.23 Front view of IC

 Logic Gates 4.15

Practically logic gates are available in the forms of ICs (integrated circuits).
One IC may contain one or more than one number of gates. The kind of gates
that an IC contains is determined by an IC number written on the top of the IC.
For example,
74LS08 represents 2-input AND gate IC having 14 number of pins, and con-
tains 4 number of AND gate in a single chip.
IC number contain different information about the IC as shown below,
74 LS 08

Indicates the standard identifier digit used to

Indicates the types of logic identify the types of logic gates
device within the series Indicates the series

The table given below shows the IC numbers with their corresponding gates,
one can easily identify which IC contains what types of gate.
Table 4.12 Representation of IC number and corresponding gates
Sl. No IC number Types of gates
1 7400 Quad 2 input NAND
2 7402 Quad 2 input NOR
3 7404 Hex inverter
4 7408 Quad 2 input AND
5 7410 Triple 3 input NAND
6 7411 Triple 3 input AND
7 7420 Dual 4 input NAND
8 7421 Dual 4 input AND
9 7432 Quad 2 input OR
10 7486 Quad 2 input XOR

PIN configuration diagram for some common fixed function IC gates.

VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND
Fig.4.24 7400 Quad 2 input NAND Fig.4.25 7402 Quad 2 input NOR
4.16 Digital Electronics, an easy approach to learn

VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND

Fig.4.26 7404 hex inverter Fig.4.27 7408 Quad 2 input AND

VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND

Fig.4.28 7432 Quad 2 input OR Fig.4.29 7486 Quad 2 input XOR

4.12 Realisation of Boolean Expression using Basic Gates

(AND, OR, NOT)
The following steps must be followed to realise a given Boolean expression using
basic gates:
1. Solve the parenthesis
2. Perform negation operation if any (NOT gate)
3. Perform AND operation (AND gate) and then finally perform OR operation
(OR gate) for SOP expression. Or else do the reverse of 3rd step for POS
realisation.

Example 4.5 Realise the logic expression F = BC + AC + AB using basic

gates.

I Solution
There is neither parenthesis nor NOT operation. So, we 1st perform AND opera-
tion and then OR operation.
 Logic Gates 4.17

A
B AB+BC+AC
C

Fig. 4.30 Realisation of logic function using basic gates

Example 4.6 Realise the logic expression F = (A + B)(B + D) using basic

gates.

I Solution
In the given expression, there are two sum terms which can be implemented using
two input OR gates and their outputs are AND operated by a 2 input AND gate.
A NOT gate is used to invert the input D.
A
(A+B)(B+D)
B

Fig. 4.31 Realisation of logic function using basic gates

Example 4.7 Realise the logic expression F = AB + (B + C)D using basic

gates.

I Solution
In the given logic expression there are two sum terms and two product terms
which is implemented using two OR and two AND gates. As the result needs to
be inverted, we use an inverter for that purpose.
A
AB+(B+C)D
B

C
D

Fig. 4.32 Realisation of logic function using basic gates

4.18 Digital Electronics, an easy approach to learn

4.13 Realisation of Logic Function Using Universal Gates

4.13.1 Level of gates
The maximum number of gates cascaded in series between an input and output
is called level of gates. For example, a sum of product (SOP) expression can be
implemented using a two level gate network, i.e., AND gates in the first level and
a OR gate in the second level.

A
B o/p=sum of
product
C Level 2
D
Level 1

Fig. 4.33 SOP form of gates showing different level

Similarly, a 3-level gate network can also be drawn as,

Output

level 1 level 2 level 3

Fig. 4.34 Different gates arranged to form a 3-level gate network

4.13.2 NAND & NOR realisation of basic gates

Rules for converting basic gates to universal gates

1. NAND gate is equivalent to an OR gate with bubbles at its input.

A F A F
=
B B

F = A + B = AB F = AB = A + B

Fig. 4.35(a) Conversion of OR gate to NAND (universal) gate

2. NOR gate is equivalent to an AND gate with bubbles at its input.

 Logic Gates 4.19

A F A F
=
B B

F=A+B=A.B F=A.B =A+B

Fig. 4.35(b) Conversion of AND gate to NOR (universal) gate

3. NAND gate is equivalent to an AND gate with bubbles at its output.

A F A F
=
B B

F = A.B F = (AB) = AB

Fig. 4.35(c) Conversion of AND gate to NAND (universal) gate

4. NOR gate is equivalent to an OR gate with bubbles at its output.

A F A
=
B B

F=A+B F = (A +B) = A + B

Fig. 4.35(d) Conversion of OR gate to NOR (universal) gate

5. A NOT gate is equivalent to shorted inputs NAND or NOR gates.

A
A A A
=

A A
=

Fig. 4.35(e) Conversion of basic gate into universal gate

By keeping in mind the above 5 rules, any basic gate can be realised using the
universal gates.

AND-OR conversion to NAND-NAND

A
B
F

C
D

Fig. 4.36(a) Basic AND-OR gates

Step-1: Convert the OR gate into NAND by giving bubbles at its input terminals.
Step-2: Give a bubble to each of the outputs of AND gates to convert it into
NAND.
4.20 Digital Electronics, an easy approach to learn

A
B
NAND

C NAND
D
NAND

Fig. 4.36(b) Conversion process of basic gates to NAND gates

Step-3: Here all the four bubbles introduced in the logic network cancels out each
other so, there is no need of putting additional bubbles.
A
B

C
D

Fig. 4.36(c) Converted NAND-NAND form of Fig.4.36(a)

OR-AND conversion to NAND-NAND

A
B
F

C
D

Fig. 4.37(a) Basic OR-AND gates

Step-1: Convert the OR gate into NAND by giving bubbles at its input terminals.
Step-2: Give a bubble to the output of AND gate to convert it into NAND.

A
B
NAND F

C NAND
D
NAND

Fig. 4.37(b) Conversion process of basic gates to NAND gates

Step 3: For each bubble we need one inverter to cancel out the inversion effect of
the bubble in the logic circuit.
 Logic Gates 4.21

A
B
NAND F

C NAND
D
NAND

Fig. 4.37(c) Conversion process of basic gates to NAND gates

 Each square represents NAND gates with shorted inputs.
A
B

F
C
D

Fig. 4.37(d) Converted NAND-NAND form of Fig.4.37(a)

So, the logic circuit given in Fig.4.37(a) is realised in terms of only NAND
gates.

OR-AND conversion to NOR-NOR

A
B
F

C
D

Fig. 4.38(a) Basic OR-AND gates

Step-1: Convert the OR gate to NOR gate by giving bubbles at each of its output.
Step-2: Convert the AND gate to NOR gate by giving a bubble at its input.

A
B
NOR F

C NOR
D
NOR

Fig. 4.38(b) Conversion process of basic gates to NAND gates

Step-3: As all the four bubbles introduced in the logic network cancels out each
other, so there is a need of additional inversion (NOR gate).
4.22 Digital Electronics, an easy approach to learn

A
B
F

C
D

Fig. 4.38(c) - Converted NOR-NOR form of Fig.4.38(a)

AND-OR conversion to NAND-NAND

Fig. 4.39(a) Basic AND-OR gates

Step-1: Convert the OR gate to NOR gate by giving bubbles at each of its output.
Step-2: Convert the AND gate to NOR gate by giving a bubble at its inputs.

A
B
F

C
D

Fig. 4.39(b) Conversion process of basic gates to NAND gates

Step 3: For each bubble we need one inverter to cancel out the inversion effect of
the bubble in the logic circuit.

A
B
NOR F

C NOR
D

Fig. 4.39(c) Conversion process of basic gates to NAND gates

 Each square block represents NOR gates with shorted inputs.

So, the logic circuit given in Fig.4.39(a) is realised in terms of only NOR
gates.
 Logic Gates 4.23

B
F
C

Fig. 4.39(d) Converted NOR-NOR form of Fig.4.39(a)

Universal capability of NAND and NOR gates

Example 4.8 Realise the following logic expression

F = B(A + CD) + AC

as,
4.24 Digital Electronics, an easy approach to learn

(i) NAND-NAND gate network

(ii) NOR-NOR gate network.
I Solution
(i) NAND-NAND realisation:
Step-1: Implement the function using basic gates,

F = B(A + CD) + AC
B

C
D
A F
A
C

Fig. 4.40(a) Implementation of function using basic gates

Step-2: Convert each AND gate to NAND by giving bubble to its output,
and convert each OR gate to NAND by giving bubble to its input.
B

C
D
A F
A
C

Fig. 4.40(b) Putting appropriate bubble in Fig.4.40(a)

Step-3: All the bubbles are mutually cancelled and only the bubble in the
input of OR gate (A) is left. To cancel it, one additional NAND gate is
required.
B

C
D F = B(A+CD)+AC
A

A
C

Fig. 4.40(c) Converted NAND-NAND form of Fig.4.40(a)

The above implementation is the required NAND-NAND implementation.
 Logic Gates 4.25

(ii) NOR-NOR realisation:

Step-1: Implement the function using basic gates,

F = B(A + CD) + AC

C
D
A F
A
C

Fig. 4.41(a) Implementation of function using basic gates

Step-2: Convert each OR gate into NOR gate by giving bubble to its output,
and convert each AND gate to NOR gate, by giving bubble to its input.

C
D
F
A
A
C

Fig. 4.41(b) Putting appropriate bubble in Fig.4.41(a)

Step-3: Place additional bubble (wherever required) to cancel the inversion

effect on the circuit, by putting the bubble in Fig.4.41(b).

Fig. 4.41(c) Putting additional bubble in fig 4.41(b) to compensate inver-

sion effect
 Each small square block represents NOR gates with shorted inputs.
4.26 Digital Electronics, an easy approach to learn

F = B(A+CD)+AC

Fig. 4.41(d) Converted NOR-NOR form of Fig.4.41(a)

The above implementation is the required NOR-NOR implementation.

Example 4.9 Realise the following logic expression

F = ABC + DE as,
(i) NAND-NAND gate network (ii) NOR-NOR gate network.
I Solution
(i) NAND-NAND realisation
Step-1: Implement the function using basic gates,
F = ABC + DE
A
B
C F

D
E

Fig. 4.42(a) Implementation of function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its
output, and convert each OR gate to NAND gate by placing bubble at its
input.
Step-3: Place the additional bubble (if required) to cancel the effect of
bubble placed in step-2.
NAND
A
B
C F

D
E NAND

Fig. 4.42(b) Putting appropriate bubble in Fig.4.42(a)

 Logic Gates 4.27

A
B
C F
D
E

Fig. 4.42(c) Converted NAND-NAND form of Fig.4.42(a)

The above implementation is the required NAND-NAND implementation.
(ii) NOR-NOR realisation
Step-1: Implement the function using basic gates,
F = ABC + DE
A
B
F
C

D
E

Fig. 4.43(a) Implementation of function using basic gates

Step-2: Convert each OR gate into NOR gate by giving bubble to its output,
and convert each AND gate into NOR gate, by giving bubble to its input.
Step-3: Place the additional bubble (if required) to cancel the effect of
bubble placed in step-2.

NOR
A NOR
B
F
C

D NOR
E
NOR

Fig. 4.43(b) Putting appropriate bubble in Fig.4.43(a)

A
B

C
F
D
E

Fig. 4.43(c) Converted NOR-NOR form of Fig.4.43(a)

4.28 Digital Electronics, an easy approach to learn

 Each small square block represents NOR gates with shorted inputs.
The above implementation is the required NOR-NOR implementation.

4.14 Sensitive and Inhibitive Inputs

Sensitive inputs
For a particular input, if the output of a logic gate is fixed regardless of the other
inputs present, then the gate is said to be sensitive to that particular input.
As for example,
AND gate is sensitive to logic 0.
A 0
0

The inputs A, B, C does

A 0
B
not affect the output C
when one of the input 0
is 0

Fig. 4.44(a) AND gate with sensitive to logic 0 input

NAND gate is sensitive to logic 0.
A 1
0

Fig. 4.44(b) NAND gate with sensitive to logic 0 input

OR gate is sensitive to logic 1
A 1
1

Fig. 4.44(c) OR gate with sensitive to logic 1 input

NOR gate is sensitive to logic 1

Fig. 4.44(d) NOR gate with sensitive to logic 1 input

Inhibitive inputs
For a particular input, if the output of a logic gate does not depend on that partic-
ular input, the gate is said to be inhibitive to that particular input.
For example,
AND gate is inhibitive to logic 1.
 Logic Gates 4.29

A
A
1

Fig. 4.45(a) AND gate with inhibitive to logic 1 input

NAND gate is inhibitive to logic 1.

A
A
1

Fig. 4.45(b) NAND gate with inhibitive to logic 1 input

OR gate is inhibitive to logic 0.

A
A

Fig. 4.45(c) OR gate with inhibitive to logic 0 input

NOR gate is inhibitive to logic 0.

A A

Fig. 4.45(d) NOR gate with inhibitive to logic 0 input

4.15 Phantom or Wired Logic

Some NAND or NOR gates allow the possibility of a wire connection between
the outputs to provide a specific logic operation, this type of logic is called wired
logic. The wired AND and the wired OR are not the physical gates.

Wired AND logic (AND-OR-Invert)

A AB
B AB.CD

C
D CD

Fig. 4.46(a) Wired NAND gate

4.30 Digital Electronics, an easy approach to learn

Wired OR logic (OR-AND-INVERT)

A A+B
B (A+B) + (C+D)

C
D
C+D

Fig. 4.46(b) Wired NOR gate

Note:

1. The wired AND logic can be implemented when the outputs of the NAND
gates are tied together.
2. The wired OR logic can be implemented when the outputs of the NOR gates
are tied together.

Example 4.10 Realise the 2-input XOR gate using NAND gates only.

I Solution
Let the two inputs be A and B.
output, F = A B = AB + AB
Step-1: Implement the function using basic gates

A
B
F

A
B

Fig. 4.47(a) Implementation of XOR function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output,
and convert each OR gate to NAND gate by placing bubble at its input.
A
B
F

NAND
A
B

Fig. 4.47(b) Putting appropriate bubble in Fig.4.47(a)

 Logic Gates 4.31

 Each small square block represents NAND gates with shorted inputs.

A
B
F

A
B

Fig. 4.47(c) Implementation of XOR gate using only NAND gate

Here 5 NAND gates are used, but the XOR gate can also be implemented
using 4 numbers of NAND gates which is more efficient.

A
A.A.B = A+AB = A+B

A AB F = (A+B)(B+A)
B = (A+B)+(B+A)
= AB + AB
=AB
B B.B.B = B+AB = B+A

Fig. 4.47(d) Implementation of XOR gate using minimum number of NAND

gate

Example 4.11 Realise the 2-input XNOR gate using NAND gates only.

I Solution
Let the two inputs be A and B.
output, F = A  B = A B + AB
Step-1: Implement the function using basic gates

A
B
F
A
B

Fig. 4.48(a) Implementation of XNOR function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output,
and convert each OR gate to NAND gate by placing bubble at its input.
4.32 Digital Electronics, an easy approach to learn

A
B
F
A NAND
B

Fig. 4.48(b) Putting appropriate bubble in Fig.4.48(a)

 Each small square block represents NAND gates with shorted inputs.

A
B
F

A
B

Fig. 4.48(c) Implementation of XNOR gate using only NAND gate

The XNOR gate can also be realised by putting an inverter at the output of
XOR gate. Hence in Fig.4.47(d) by putting an additional NOT gate (shorted input
NAND) we can get XNOR gate.
A
A.A.B = A+AB = A+B
F = (A+B)(B+A)
A AB F = (A+B)(A+B)
B
= AB + AB
=A B
B B.B.B = B+AB = B+A

Fig. 4.48(d) Alternative implementation of XNOR gate using NAND gate

Example 4.12 Realise the 2-input XOR gate using NOR gates only.

I Solution
Let the two inputs be A and B.
output, F = A B = AB + AB
Step-1: Implement the function using basic gates
A
B
F

A
B

Fig. 4.49(a) Implementation of XOR function using basic gates

 Logic Gates 4.33

Step-2: Convert each AND gate to NOR gate by placing bubbles at its inputs, and
convert each OR gate to NOR gate by placing bubble at its output. Also place
additional bubbles (if required) to cancel the inversion effect.
NOR
A
B F

A NOR
B
NOR

Fig. 4.49(b) Putting appropriate bubble in Fig.4.49(a)

 Each small square block represents NOR gates with shorted inputs.
A
B

A
B

Fig. 4.49(c) Implementation of XOR gate using only NOR gate

Example 4.13 Realise the 2-input XNOR gate using NOR gates only.

I Solution
Let the two inputs be A and B.
output, F = A  B = A B + AB
Step-1: Implement the function using basic gates
A
B
F
A
B

Fig. 4.50(a) Implementation of XNOR function using basic gates

Step-2: Convert each AND gate to NOR gate by placing bubbles at its inputs, and
convert each OR gate to NOR gate by placing bubble at its output. Also place
additional bubbles (if required) to cancel the inversion effect.
4.34 Digital Electronics, an easy approach to learn

NOR
A
B F

A NOR
B
NOR

Fig. 4.50(b) Putting appropriate bubble in Fig.4.50(a)

 Each small square block represents NOR gates with shorted inputs.
A
B

Fig. 4.50(c) Implementation of XNOR gate using only NOR gate

Example 4.14 Use minimum number of NOR gate to implement XOR and
XNOR logic.
I Solution
Implementation of XNOR gate:
A A+(A+B) = A.(A+B)
= AB
A A+B AB + AB
=AeB
B

B (B+A+B) = B.(A+B)
= AB

Fig. 4.51(a) Implementation of XNOR gate using only NOR gate

Implementation of XOR gate:
A A+(A+B) = A.(A+B)
= AB
A AB + AB
A+B AB + AB
B =AB

B (B+A+B) = B.(A+B)
= AB

Fig. 4.51(b) Implementation of XOR gate using only NOR gate

 Logic Gates 4.35

Example 4.15 How many NAND gates are required to design an OR gate and a
NOR gate.
I Solution
OR gate implementation:

Fig. 4.52(a) OR gate

We know that, OR gate is converted to NAND by putting bubbles to its inputs.
To cancel the effect of bubble at inputs, we put additional two bubbles at input.

Fig. 4.52(b) Putting appropriate bubble in Fig.4.52(a)

 Each small square block represents NOR gates with shorted inputs.

Fig. 4.52(c) Implementation of OR gate using only NAND gate

So total three number of NAND gates are required to implement the OR gate.
NOR gate implementation:

Fig. 4.52(d) NOR gate

Fig. 4.52(e) Implementation of NOR gate using only NAND gate

We know that the OR gate can be converted to NOR gate by placing an addi-
tional NOT gate to its output.
4.36 Digital Electronics, an easy approach to learn

So, four number of NAND gates are required to implement the NOR gate.

Example 4.16 How many NAND gates are required to implement the Boolean
function,
F = AB + BC + AC
I Solution
F = AB + BC + AC
Step-1: Implement the above function using basic gates.
A
B

B
C F

A
C

Fig. 4.53(a) Implementation of the given function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output
and convert each OR gate to NAND gate by placing bubble at its input.
Step-3: Place additional bubble (if required) to cancel the inversion effect.
A
B NAND
NAND
B
C F

NAND
A
C

Fig. 4.53(b) Putting appropriate bubble in Fig.4.53(a)

A
B

B
C F

A
C

Fig. 4.53(c) Implementation of given function using only NAND gate

So, six number of NAND gates are required to implement the given function.
 Logic Gates 4.37

Example 4.17 How many NAND gates are required to implement the Boolean
function,
F (A, B, C, D) = A(CD + B) + BC
I Solution
F (A, B, C, D) = A(CD + B) + BC
Step-1: Implement the above function using basic gates.
C
D
B
F
A
B
C

Fig. 4.54(a) Implementation of the given function using basic gates

Step-2: Convert each AND gate to NAND gate by placing bubbles at its output
and convert each OR gate to NAND gate by placing bubble at its input. The input
of NAND gate is shorted to get NOT gate.
Step-3: Place additional bubble (if required) to cancel the inversion effect.
NAND
C
D
B
NAND NAND
A
B
C

Fig. 4.54(b) Putting appropriate bubble in Fig.4.54(a)

C
D

B
A F
C
B

Fig. 4.54(c) Implementation of given function using only NAND gate

So, seven number of NAND gates are required to implement the given func-
tion.
4.38 Digital Electronics, an easy approach to learn

Example 4.18 What is the minimum number of NAND gates required to imple-
ment the function
F = A + AB + ABC
I Solution
F = A + AB + A B C
= A(1 + B) + ABC
= A + ABC ( 1 + B = 1)
= A(1 + BC) ( 1 + BC = 1)
=A
Hence, no gate is required.

Example 4.19 What is the minimum number of 2 input NOR gates required to
implement the function
X
F (A, B, C, D) = m(0, 1, 2, 3, 8, 9, 10, 11)
I Solution
To implement a function using NOR gate we prefer POS(product of sum) form,
So, we first convert the given min term to corresponding max term as,
Y
F (A, B, C, D) = M (4, 5, 6, 7, 12, 13, 14, 15)
Drawing the K-map,
CD
00 01 11 10
AB
00 0 1 3 2
01 0 0 0 0
4 5 7 6
11 0 12 0 0 0
13 15 14

10 8 9 11 10

Fig. 4.55(a) K-map

F =B
So, only one NOR gate is required,
B
B

Fig. 4.55(b) Implementation of the given function using only NOR gate
 Logic Gates 4.39

4.16 Degenerated and Non Degenerated Forms

A two-level gate network is said to be degenerative, if it gives the same operation,
when degenerated to a single level.
For example, AND-AND is equivalent to AND

Fig. 4.56(a) Two AND gates degenerates to one AND gate

16 possible combination of two-levels forms, with four types of gates: AND,
OR, NAND & NOR. Out of these 16-combinations, 8 are non-degenerative forms
and 8 are degenerative forms
8 Non-Degenerative Forms:
SOP(Sum Of Product) POS(Product Of Sum)
AND OR OR AND
NAND NAND NOR NOR
NOR OR NAND AND
OR NAND AND NOR

Fig. 4.56(b) Non-Degenerative gates

It cannot be converted into a single level. So, Non-Degenerative. Similarly,
remaining seven can be verified
8 Degenerative Forms:
Two level gates Degenerates to single gate
AND AND AND
OR OR OR
OR NOR NOR
AND NAND NAND
NOR AND OR
NAND NOR AND
NOR AND AND
NAND OR OR
4.40 Digital Electronics, an easy approach to learn

A AB AB+C
B
C = A+B+C

A A+B+C
B
C

Fig. 4.56(c) Degenerative gates

The remaining seven combinations, can be verified in a similar manner.

Brain teasers
P
1. F (A, B, C) = m(1, 2, 3, 4, 5, 7). Assuming inverting inputs are al-
lowed, find out
(i) Minimum number of two input NAND gates that are required
(ii) Minimum number of NOR gates that are required
I Solution
P
(i) F (A, B, C) = m(1, 2, 3, 4, 5, 7)
To represent the above function in NAND-NAND realisation, we should
write the above function using SOP form.
Since, it is required to use minimum number of NAND gates we go
for K-map minimisation

Fig. 4.57(a) K-map

F (A, B, C) = AB + C + AB
Representing the above K-map function using basic gates, we get,
A
B
F
C
A
B

Fig. 4.57(b) Representation of logic function using basic gates

Converting the AND & OR gates to NAND by bubbling the outputs
and inputs respectively & using extra bubbles (if required) to cancel
the inversion effect in the logic circuit we get,
 Logic Gates 4.41

NAND NAND
A NAND
B F

C
A
B
NAND

Fig. 4.57(c) Putting appropriate bubble in Fig.4.57(b)

 Each small square block represents NAND gates with shorted

inputs.

A
B F

C
A
B

Fig. 4.57(d) Implementation of given function using only NAND gate

So a minimum of 5 numbers of two input NAND gates are required to

P
implement the Boolean function, F (A, B, C, ) = m(1, 2, 3, 4, 5, 7).
P
(ii) F (A, B, C, ) = m(1, 2, 3, 4, 5, 7)
To represent the above Boolean expression in NOR-NOR realisation,
we should write the expression in POS form that is F (A, B, C) =
Q
M (0, 6)
For minimisation, K-map must be drawn for POS form

L1
BC
A 00 01 11 10
0 0 0 1 3 2
1 0 6 L:2
4 5 7

Fig. 4.58(a) K-map

L1 (A + B + C)
L2 (A + B + C)
F (A, B, C) = (A + B + C)(A + B + C)
Representing the above reduced expression using basic gates, we get,
4.42 Digital Electronics, an easy approach to learn

A
B
F
C
A
B

Fig. 4.58(b) Representation of logic function using basic gates

Convert each AND gate to NOR gate by placing bubbles at its inputs,
and convert each OR gate to NOR gate by placing bubble at its output.
Also, place additional bubbles (if required) to cancel the inversion
effect.

NOR
A
B
F
C
A NOR
B NOR

Fig. 4.58(c) Putting appropriate bubble in Fig.4.58(b)

Representing the Fig.4.58(c) using NOR gate we get,

A
B
F
C
A
B

Fig. 4.58(d) Implementation of given function using only NOR gate

So a minimum of 3 NOR gates are required to implement the Boolean

P
function F = m(1, 2, 3, 4, 5, 7).

2. Simplify the given logic circuit and represent it using a NAND gate, assum-
ing inverted inputs are available.

Fig. 4.59(a) Logic gates

 Logic Gates 4.43

I Solution
The logic circuit given above can be simplified as,

Fig. 4.59(b) Simplification logic gates

So,
F =A+B+C

F = F = A + B + C = A.B.C
So, the simplified NAND representation is,

Fig. 4.59(c) Figure 4.59(a) is simplified to a single logic gate

3. Assuming that both the inverted and non-inverted inputs are available, find
out the minimum number of two input NOR gates required to implement a
two input XOR gate.

I Solution
A two input XOR gate needs to be implemented. So for NOR implementa-
tion we will go for POS form.
From truth table
Input Output
A B F=(AB)
0 0 0
0 1 1
1 0 1
1 1 0
X
F =AB = m(1, 2)
Y
= M (0, 3) (K-map minimisation)
= (A + B)(A + B)
4.44 Digital Electronics, an easy approach to learn

Implementing the above expression using basic gates

A
B
F

A
B

Fig. 4.60(a) Basic logic gates

Converting the above logic gates to NOR gate,we have
A
B
F

A NOR
B

A
B
F

A
B

Fig. 4.60(b) Converted form of basic gates to NOR gates

So, a minimum of three, 2-input NOR gates are required to implement a
2-input XOR gate when inverted inputs are allowed.

4.

Fig. 4.61(a) Cascaded XOR gates

I Solution

Fig. 4.61(b) Cascaded XOR gates

 Logic Gates 4.45

Level 1 gives x x = 0
Level 2 gives x 0 = x
Now F = x x = 0
F =0

5. Remodel the logic circuit using only basic logic gates

Fig. 4.62(a) NAND gates

I Solution

Fig. 4.62(b) Converted form of Fig.4.62(a) into basic gates only

6. How many two input NAND gates are required to implement

A 3-bit even parity generator

A 4-bit even parity checker
4.46 Digital Electronics, an easy approach to learn

I Solution
We know that,
In even parity for even number of 1s in input, we get output as 0
So for 3-bit, parity generator, the truth table can be drawn as,
Table 4.13 Truth table of parity generator
A B C Pe
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Pe = A BC + A B C + A B C + ABC
= A(B C + B C) + A(B C + BC)
(Let X = BC + BC = B C)
= AX + AX
=AX
Pe = A B C

Pe Even parity generated bit. For each XOR operation we need four
NAND gates. So total number of NAND gates required for a 3-bit even
parity generation = 4 + 4 = 8.
Notes:
XOR operation is used for even parity generation.
XNOR operation is used for odd parity generation.
For 4-bit even parity checker, we need to check four bits by using XOR
operation (In a similar way as that of parity generation)

Pc = P e A B C

Pc Parity checker
 Logic Gates 4.47

For 1 XOR operation we need 4-NAND gates.

Hence, total number of gates required = 4+4+4 = 12

7. The figure shows the internal schematic of a TTL (Transistor Transistor

logic) AOI (AND-OR-INVERT) gate, for the inputs shown in Fig.4.63(a).
The output Y is,
A
B Y

Inputs are floating

Fig. 4.63(a) Gates with floating inputs

I Solution
We know that for TTL circuit when the inputs are floating for AND gate we
take the inputs as 1.
So,

A AB
B Y
1

Fig. 4.63(b) Logic gates where floating input is replaced by logic 1

Y = (AB + 1)
=1
Y =0

8. If the input of the digital circuit consisting of cascade of 20 XOR gates is

X, then the output Y is equal to,
1
Y

Fig. 4.64(a) Cascaded XOR gates

4.48 Digital Electronics, an easy approach to learn

I Solution

The number of XOR gates = 20

1X=X
1 1X=1
Y

1X =X
X X =1

At the end of 2-XOR gate operation,

We get output = 1
So, final output, Y=1 (as 2 is multiple of 20)

Objective Questions
1. If a 3-input NOR gate has eight input possibilities, how many of those pos-
sibilities will result in a HIGH output?

A. 1 B. 2 C. 7 D. 8

2. The output of an AND gate with three inputs, A, B, and C is HIGH, when
.

A. A = 1, B = 1, C = 0 C. A = 1, B = 1, C = 1
B. A = 0, B = 0, C = 0 D. A = 1, B = 0, C = 1

3. The output of an OR gate with three inputs, A, B, and C is LOW, when

.

A. A = 0, B = 0, C = 0 C. A = 0, B = 1, C = 1
B. A = 0, B = 0, C = 1 D. all of the above
 Logic Gates 4.49

4. The output of a NOR gate is HIGH, if .

A. all inputs are HIGH C. any input is LOW

B. any input is HIGH D. all inputs are LOW

5. The Boolean expression for a 3-input AND gate is .

A. X = AB C. X = A + B + C
B. X = ABC D. X = AB + C

6. What are the pin numbers of the outputs of the gates in a 7432 IC?

A. 3, 6, 10 and 13 C. 3, 6, 8 and 11
B. 1, 4, 10 and 13 D. 1, 4, 8 and 11

7. How many inputs of a four-input AND gate must be HIGH in order for the
output of the logic gate to go HIGH?

A. any one of the inputs C. any three of the inputs

B. any two of the inputs D. all four inputs

8. If the output of a three-input AND gate must be a logic LOW, what must
the condition of the inputs be?

A. All inputs must be LOW.

B. All inputs must be HIGH.
C. At least one input must be LOW.
D. At least one input must be HIGH.
9. Logically, the output of a NOR gate would have the same Boolean expres-
sion as a(n):

A. NAND gate immediately followed by an inverter

B. OR gate immediately followed by an inverter
C. AND gate immediately followed by an inverter
D. NOR gate immediately followed by an inverter
4.50 Digital Electronics, an easy approach to learn

10. What is the difference between a 7400 and a 7411 IC?

A. 7400 has two four-input NAND gates; 7411 has three three-input
AND gates
B. 7400 has four two-input NAND gates; 7411 has three three-input
AND gates
C. 7400 has two four-input AND gates; 7411 has three three-input NAND
gates
D. 7400 has four two-input AND gates; 7411 has three three-input NAND
gates

11. A 2-input NOR gate is equivalent to a .

A. negative-OR gate C. negative-NAND gate

B. negative-AND gate D. none of the above

12. How many input combinations would a truth table have for a six-input AND
gate?

A. 32 B. 48 C. 64 D. 128

13. What is the circuit number of the IC that contains four two-input AND gates
in standard TTL?

A. 7402 B. 7404 C. 7408 D. 7432

14. With regard to an AND gate, which statement is true?

A. An AND gate has two inputs and one output.

B. An AND gate has two or more inputs and two outputs.
C. If one input to a 2-input AND gate is HIGH, the output reflects the
other input.
D. A 2-input AND gate has eight input possibilities.

15. The term hex inverter refers to:

A. an inverter that has six inputs

B. six inverters in a single package
 Logic Gates 4.51

C. a six-input symbolic logic device

D. an inverter that has a history of failure

16. The 8-input XOR circuit shown has an output of Y = 1. Which input com-
bination below (ordered A - H) is correct?

A. 10111100 C. 11100111
B. 10111000 D. 00011101

17. Implementing the expression AB + CDE using NAND logic, we get:

A A
B B

C C
D D
A. E C. E
A A
B B
C C

D D
B. E D. E

18. How many gates the expression X = AB(CD +EF ) would require before
a SOP implementation
A. 1 B. 2 C. 4 D. 5

19. The following waveform pattern is for a(n) .

A

X
4.52 Digital Electronics, an easy approach to learn

A. 2-input AND gate C. Exclusive-OR gate

B. 2-input OR gate D. None of the above

20. To implement the expression BCD + ABCD + ABCD, it takes one OR

gate and .

A. three AND gates and three inverters

B. three AND gates and four inverters
C. three AND gates
D. one AND gate
21. One positive pulse with tw = 75 s is applied to one of the inputs of an
exclusive-OR circuit. A second positive pulse with tw = 15 s is applied
to the other input beginning 20 s after the leading edge of the first pulse.
Which statement describes the output in relation to the inputs?

A. The exclusive-OR output is a 20 s pulse followed by a 40 s pulse,

with a separation of 15 s between the pulses.
B. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse,
with a separation of 40 s between the pulses.
C. The exclusive-OR output is a 15 s pulse followed by a 40 s pulse.
D. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse,
followed by a 40 s pulse.
22. How many AND gates are required to implement the Boolean expression,
X = ABC + ABC + ABC?

A. 1 B. 2 C. 3 D. 4

23. With how many NAND gates the inverter can be produced?

A. 1 B. 2 C. 3 D. 4

24. The following waveform pattern is for a(n) .

A

X
 Logic Gates 4.53

A. 2-input AND gate C. Exclusive-OR gate

B. 2-input OR gate D. None of the above

25. How many 2-input NOR gates does it take to produce a 2-input NAND
gate?

A. 1 B. 2 C. 3 D. 4

26. A logic circuit with an output, X = ABC + AB consists of .

A. two AND gates, two OR gates, two inverters

B. three AND gates, two OR gates, one inverter
C. two AND gates, one OR gate, two inverters
D. two AND gates, one OR gate

Answers for objectives

1. C 2. C 3. A 4. D 5. B 6. C
7. D 8. C 9. B 10. B 11. B 12. C
13. C 14. C 15. B 16. A 17. A 18. D
19. B 20. A 21. D 22. C 23. A 24. A
25. D 26. C

Exercises
4.1 A pulse is applied to each input of a 2-input NAND gate. One pulse goes
HIGH at t = 0 and goes back LOW at t = 1ms. The other pulse goes HIGH at
t = 0.8ms and goes back LOW at t = 3ms. The output pulse can be described
as follows

a) It goes LOW at t = 0 and back HIGH at t = 3ms

b) It goes LOW at t = 0.8ms and back HIGH at t = 3ms
c) It goes LOW at t = 0.8ms and back HIGH at t = 1ms
d) It goes LOW at t = 0.8ms and back LOW at t = 1ms
4.2 Determine the output waveforms for a

1) Two input AND gate

4.54 Digital Electronics, an easy approach to learn

2) Two input OR gate

3) Two input NAND gate
4) Two input NOR gate
5) Two input XOR gate
6) Two input XNOR gate

By showing a proper relationship of output to input with a timing diagram

Fig. 4.65

4.3 Determine the output waveforms for a four input AND and four input XOR
gate, when the input waveforms are as shown below.

A
B

Fig. 4.66

4.4 Implement the following function using basic logic gates

X X
F (A, B, C, D) = m(5, 6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15)

4.5 Implement the following

1) AB + CD using NAND gate only.

2) (A + B)(C + D) using NOR gate only

4.6 Implement the following

1) A(B + C) + AC, using NAND gate only

2) A(B + C) + AC, using NAND gate only assuming inverted inputs are
available.
 Logic Gates 4.55

4.7 Check which of the following is degenerative or non-degenerative

1) AND-OR 3) OR-NOR
2) OR-AND 4) NAND-OR

4.8 Find the outputs of the following logic circuits

1) A
B
F

A
B

Fig. 4.67(a)

2) A
A
F

B
B

Fig. 4.67(b)

4.9 Find the output of the following logic circuits

1) A
B
C Y
D
E
F

Fig. 4.68(a)

2) A
B
F

A
B

Fig. 4.68(b)

4.10 The truth table is given below.

Implement the truth table using minimum number of gates.

4.56 Digital Electronics, an easy approach to learn

Table 4.14
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Answers for exercises

4.1 C

4.2

XOR

4.3
A

B
C
D
logic 0
AND

XOR

4.4
A
B F(A,B,C,D)
C

B
D

4.5 1)
 Logic Gates 4.57

A
B
F

C
D

2)

4.6 1)
B
C F

A
A
C

2)
A F

B
C

A
C

4.7 (i) and (ii) are Non-degenarative

(iii) and (iv) are degenarative

4.8 i) A + B
ii) 0

4.9 i) Y = F (E + (A + B + D)(B + C + D))

ii) A  B

4.10 F = A B C
A
B