FAST PWM MODE

FAST PWM MODE

Ilbay Vicua Alexis Fernando
e-mail: alejoj.95@hotmail.com

SUMARY: In the following writing is presented or
described how to work in a timer0 FAST PWM mode by
introducing timer0 and an example in the AVR and
PROTEUS software where the brightness control of a led
is made and the speed of a motor applying FAST PWM
for this example.
KEY-WORDS: Converter, signals, PWM, timer0.
1 INTRODUCTION
Pre-scaler 10 bits (allows to divide the
frequency).
Two sources of interruption: overflow and
equality in comparison (TOV0 and OCF0).
The registers that intervene for the configuration of timer
0 are:
TCCR0: This record is in charge of setting the
timer.

With a timer we can make applications such as the

speed control of an engine, the operation of a keyboard,
a scan of 7 segments, obtaining samples through the
Figure 2.- TCCR0
ADC, etc.
The general operation of a timer is to save a
These bits configure the four different working
maximum value in a special storage register to which a
modes of the timer.
counter will arrive, when the value in the counter is equal
to the stored register a comparator can perform the
following actions:
The timer output flag is triggered thus initiating
an interrupt.
We program an event in which on the output pin
the previous level is switched, set low or set
high and thus generate a PWM signal at a
certain frequency. Table 1.- Timer0 Modes

For each working mode these bits configure the

mode of generation of the digital signal but what we are
interested in this research is basically Fast PWM.

Table 2.- Compare Output Mode

Figure 1.- Timer0 Scheme

TIMSK: In this log we enable the way in which the
Among the blocks, we can highlight are the TCCRn interrupt will be generated.
which is the register that configures the timer in its mode
of operation, Tn is where the clock signal is injected for
the external event counter mode, OCn is the pin by
which it is generated the digital signal.
Figure 3.- TIMSK
TIMER0 CHARACTERISTICS
8-bit timer. OCIE0 is the enable of the interrupt by equality in
Counter with a comparison unit. the output comparison and TOIE0 is the enable of the
Counter clear mode in the CTC interrupt by overflow.
comparison (Auto-recharge). TIFR: In this register are the flags of the interrupts.
Phase pulse (PWM) modulator is correct
and glitch-free.
Frequency generator.

1
 FAST PWM MODE
.

same. The work cycle is written to the OCR0

register.

Figure 4.- TIFR

2 FAST PWM MODE Figure 6.- OCR0

The resolution of the timer is 8 bits, so the resolution EXAMPLE AVR

of the PWM signal will also be 8 bits, (0 to 255), ie the
signal can take 256 values (including 0), in the case of a .INCLUDE "M16DEF.INC"
Led, 256 levels of brightness, 0 being the brightness .EQU OCR_INICIAL=128
(minimum led off) and 255 the maximum brightness .ORG $00
(LED fully lit). If the signal was used to control an engine, JMP PROGRAMA //Interrupcion
it would have 256 levels of speed. Reset
.ORG $02
In this mode, the timer counts from 0 to 255 at a JMP INTER0 //Interrupcion 0
Ftimer frequency, and at each increment of the timer, the .ORG $04
value of the count is compared to the value of the OCR0
JMP INTER1 //Interrupcion 1
register, which is the value (0 to 255) of our output
Signal, that when the timer value matches the value of
PROGRAMA:
the OCR0 register, the OC0 pin changes state (1 or 0) LDI R16,HIGH(RAMEND)
depending on the desired configuration. When the timer0 OUT SPH,R16
is overflowed (from 255 to 0), the corresponding OC0 LDI R16,LOW(RAMEND)
output is activated again. OUT SPL,R16
LDI R16,0B00001000
In other words, at the start of the timer, output OC0 is OUT DDRB,R16 //Habilito
set to 1 (turns on the LED), and at each increment of the salida OC0
timer compares the OCR0 register, if this register is LDI R17,OCR_INICIAL
equal to the timer value, output OC0 goes to 0 (Turns off OUT OCR0,R17 //Coloco la
the led), and turns it on again until the timer overflows seal al 50% ciclo de trabajo
and starts the count again from 0. LDI R16,0B01101101
OUT TCCR0,R16 //No invertido
This mode allows the generation of a high frequency
OC0 - Fast PWM - CLK/1024
PWM signal with a low square wave precision, Phase
Correct PWM mode offers better signal quality but LDI R16,0B00001010
without working at such high frequencies. OUT MCUCR,R16 //INT0 e INT1
Flanco de Bajada
The OCR0 pin associated with the timer0 and which LDI R16,0B11000000
is the output of the PWM signal is in the PORTB (PB3). OUT GICR,R16 //INT0 e INT1
All the pins to be used as PWM must be configured as Habilitada
output. SEI
BUCLE: RJMP BUCLE
INTER0:
CALL RETARDO
CPI R17,0
BREQ Salir0
DEC R17
OUT OCR0,R17
Salir0:
RETI
INTER1:
CALL RETARDO
Figure 5.- Pin pwm in PB3 CPI R17,255
BREQ Salir1
As seen in the introduction we can configure our INC R17
ATmega to work as PWM and later we will see an OUT OCR0,R17
example of how to configure to work as PWM. Salir1:
RETI
With this we have already configured our PWM, now only RETARDO:
need to program the duty cycle (Duty Cycle), which for LDI R25,31
this example with an LED, means the brightness of the Bucle_Externo:

2
 FAST PWM MODE
.

LDI R24,255
Bucle_Interno:
NOP
NOP
NOP
NOP
NOP
DEC R24
BRNE Bucle_Interno
DEC R25
BRNE Bucle_Externo
RET Figure 9.- Duty Cycle greater than 50%

EXAMPLE PROTEUS
3 CONCLUSIONS

The timer0 has 4 different working modes which are

normal mode, PWM phase correct mode, CTC mode and
FAST PWM mode.

The FAST PWM mode has the feature of working

with 8 bits which tells us that it has 256 values (0-255).

The working settings for the timer0 modes are

made in the TCCR0 register.

Figure 6.- Simulated Circuit
EXAMPLES AVR AND PROTEUS FUNCTIONING
The operation of the circuit is that it will vary the pulse
width depending on the external interrupts INT0 to raise
the PWM and INT1 to lower the PWM.
4 REFERENCES
[1] Mikel Etxebarria Isuskiza, Microcontroladores PIC: Teoria y
Practica 2011, Creaciones copyright.
[2] Muhamad Ali MAzidi, Sarmad Naimi, and Sepher Naimi,
The AVR microcontroller and embedded system using
assembly and C, Pearson.

Figure 7.- Circuit Running

Figure 8.- Duty Cycle less than 50%