Chapter 1

Electronics III
Instructor: Omid Shoaei

Room # : 318
Phone # : 82089762
Email: oshoaei@ut.ac.ir
Class Hours: Sun. & Tue. 10:30-12:00
Teacher Assistants:
1
Omid Shoaei, Univ. of Tehran
Course Outline
Models for
Integrated-Circuit Active Devices
2
Course Outline
MOS Transistor Models and physics
MOSFET and Junction FET
MOS capacitor
MOS threshold
MOS regions (linear & saturation ) characteristic
Small-Signal Model
Examples of small-signal Analysis
Transconductance Amp
Diode
Source Follower
Capacitance
Higher order models
References:
Razavis IC Book, L&S
3
Course Outline
Bipolar Transistor Models
Hybrid-small-signal model (for BJT)
model elements
Common-Emitter (current drive, voltage drive)
Common-Collector
Common - Base
Ohmic Resistance
Lateral PNP transistors
Other Components
Base diffusion resistor
Other resistor
Capacitor References:
Inductor Gray & Mayers IC Book, L&S
4
Course Outline
Single- Stage Amplifiers
Basic Concepts
Common-Source Stage
Common-Source Stage with Resistive Load
CS Stage with Diode-Connected Load
CS Stage with Current-Source Load
CS Stage with Triode Load
CS Stage with Source Degeneration
Source follower
Common-Gate Stage
Cascode stage
Folded Cascode
Choice of Device Models
Reference:
Razavis IC Book
5
Course Outline
Differential Amplifiers
Single-Ended and Differential operation
Basic Differential Pair
Qualitative Analysis
Quantitative Analysis
Common mode Response
Differential Pair with MOS Loads
Gilbert Cell
Reference:
Razavis IC Book
6
Course Outline
Frequency Response of Integrated circuits
Single-Stage Amplifier frequency response
Differential Amp frequency response
Common-Mode (CM) gain in diff pair
Emitter-follower freq response
Common-Base freq response
multistage Amp freq response
Dominant Pole Approximation
Zero-value Time constant Analysis References:
Common-Emitter cascade freq response Razavi,
Cascode freq response Gray & Mayers
IC Book
7
Course Outline
Elementary Transistor stages
MOS single Transistor Amplifying stages
Biasing, Gain , Bandwidth, high frequency performance ,
Unity- Gain freq & GBW product
Source & Emitter Followers
DC level shift, high freq Gain, Output Impedance
Cascode Transistors
MOS cascode (Low freq Analysis, high freq performance).
Bipolar cascode
Cascode stages
BW of cascode w/ low and w/Active load, High voltage cascode,
cascode w/Bipolar, Feedforward in cascode Amp
8
Course Outline
Differential Stage
MOS differential stages (DC characteristic, small-signal
behavior, low freq analysis, GBW product, Slew-rate)
Current mirrors
Simple MOS current Mirror
Other current mirror
Bipolar current mirror
Gain factor mismatch
Body factor mismatch
Offset voltage
Mismatch effects on Current mirror
Differential stage w/ Active load
CMRR
Design for low offset and drift
Power Supply Rejection Ratio (PSRR)
9
Course Outline
Design options :
Design for optimum GBW or SR
Compensation of the Positive Zero
Reference: L&S
10
Course Outline
Frequency Response stability of feedback Amplifiers
The Stability Problem
References:
Gray& Mayer IC book,
Sedra & Smith
11
Course Outline
Operational Amplifier Design
Design of a simple CMOS OTA
Gain
GBW and M
Design plan : optimization for Maximum GBW
The Miller CMOS OTA
Operation
Gain
GBW and M
Design plan : Determine Compensation Cap Cc Determine size and I
12
Course Outline
Full set of characteristic of Miller OTA
CM input vs. supply
Output voltage range vs. Supply
Max output current (sink and source)
AC analysis :low freq.
GBW vs.. I BIAS
Slew-rate vs. load cap
Output voltage range vs. Frequency
Settling time
Output Impedance
temperature effects
Matching characteristics Reference:
transistor Mismatch model
Threshold voltage Mismatch VT L&S
13
Course Outline
And Special Issues

14
References
Design of Analog CMOS Integrated Circuit, Behzad
Razavi, McGraw-Hill 2001
Analysis and design of Analog Integrated Circuits, Gray

Hurst-Lewis- Mayer, Forth Edition John Wiley & SONS
INC. 2004
Design of Analog Integrated circuit & systems, Kenneth R.

Laker, Willy M.C. Sansen, McGraw-Hill 1994
Microelectronic Circuit, Adel S. Sedra, Kenneth C. Smith,

Saunders College publishing 1991
Analog Integrated Circuit Design, David A. Johns ,Ken

Martin, John Wiley & Sons Inc,1997 15
Grading, Exams
Assignment : 10%
Project : 20%
Quiz :10%
Mid term :20%
Final term :40%
Midterm Exam: Aban 16th (Nov. 7th), Thursday

(8:30am-11:30am)
16
Field Effect Transistors (FET)
Fig 1.1 a
n-channel MOSFET (nMOST)
17
Junction Field Effect Transistors (JFET)
MOSFET (MOST): Metal-Oxide Semiconductor FET
JFET: Junction FET
CGC
CBC
Fig 1.1 b
p-channel JFET
18
Channel is sandwiched between two depletion layers which isolate
channel from two conducting layer: Gate (p+ in n-channel JFET)
and Substrate (p in n-channel JFET).
These depletion layers form junction capacitances between the
channel to the top gate C GC and to the bottom layer C BC .
The voltage across each capacitance controls the widths of the
depletion layer and hence, the widths of the residual channel
between both depletion layers.
The voltage across CGC and C BC control the conductivity of the
channel as well as its charge, so the current. Either C GC or C BC
can independently control the current through channel.
19
The channel is isolated from the top gate G , by a depletion layer
with width h. The channel is also isolated from the substrate or
bulk B, by another depletion layer.
Both depletion layers modulate the channel conductivity or pinch-off
(no I D current, I D = 0 ) the channel entirely.
This (pinch-off) can be done by reverse biasing the voltage across
these depletion layers (respect to the source).
Note: usually the bulk is at a constant negative voltage or connected
to source so only the top gate (like CMOS) is used to control the
transistor current.
The depletion layer of the top gate G can fully pinch off the channel,
provided its thickness hc is made equal to the thickness of the
channel a c .
The voltage VGS requested to fully pinch-off the channel (for zero
VDS ) is called pinch-off voltage V P.
20
Junction Field Effect Transistors
(JFET)
Consider a PN Junction (Fig 1.2)
xp xn
(tsi=xp)
Fig 1.2
PN Junction
21
Junction Field Effect Transistors
(JFET)
J&M:
22
In the p+ side a large number of free positive carriers are available,
whereas in the n side, many free negative carriers are available.
The hole, in the p+ side tend to diffuse in to the n side, whereas the
free electrons in the n side tend to diffuse to the p+ side.
This diffusion lowers the concentration of free carriers in the region
between the two sides.
As the two types of carriers diffuse together, they recombine. Every
electron that diffuse from n-side to the p-side leaves behind a
bound positive charge close to the transition region. Similarly,
every hole that diffuse from the p-side leaves behind a bound
electron near transition region.
The diffusion of free carriers create a depletion region at the
junction of the either side in which no free carriers exist.
23
The total amount of bound charge on the two sides of junction
must be equal for charge neutrality.
This requirement causes the depletion region to extend further into
the more lightly doped n-side than into the p+ side.
As these bound charges are exposed, an electric field develops going
from the n-side to the p-side. This electric field is often called the
built-in potential of the junction. It opposes the diffusion of free
carriers until there is no movement of charge under open-circuit
condition.
24
Recall for a one-sided abrupt junction, the thickness of the depletion layer is:
2 si ( j VBC ) or ( + V ) Where VR = VBC is the

t si = j R
reverse bias voltage across
qN SUB (1-1) p-n junction
The larger reverse bias is the thicker
depletion layer becomes
VBC is the reverse bias voltage
j is the gate-channel junction built-in voltage
kT N c N Gate
j = Ln 2
ni = 1.5 1010 cm 3 @ 27 c (1-2)
q ni
Nc is the channel doping (referred
to NA here for being p-type)
Note that always VSB 0 for nmos
25
Substituting V BC by V P and t si by a c :
2
qN A ac dopping in p+ in channel
VP = j (1-3)
2 si
This JFET is depletion type, meaning the conducting channel already
exists for VGS = 0 . Its V P must be positive.
By means of Ion-implementation technology,
thinner channels (< 0.2 m ) can be realized.
For n+ (gate) doping of 1019/cm3 & p+ (channel) NA doping of 1017/cm3
VP = 1V ac 0.16 m
j = 0.932V
VP = 0V ac 0.11m 26
Fig 1.3
V
The forward bias VGS are shown by dashed lines in Fig 1.3.
Higher than the diode voltage large forward current starts to
flow through gate. Forward bias gate must be avoided due to
gate leakage current.
27
JFET DC model in Saturation:

Analogy with MOSFET (seen later) :
Qm = CGS (vGS VP ) (C/m2)
RDS sq =
1
(Ohms/square) nCox: (uA/V2)
Qm
L 1
RDS = RDS sq =
W (vGS VP )
W
= CGS
L
Without proof (analogy with MOSFET; seen later) :

vGS 2
iDsat = (vGS VP ) 2 = VP2 (1 )
2 2 VP
si 0 8.854 1012 F/m
=
where CGS =
ac = si K=
S 0 where K S 11.8
28
MOST
Fig 1.4 a
nMOST
29
MOST
Fig 1.4 b
nMOST layout
30
MOST
Channel is sandwiched between an oxide layer and a depletion
layer. These oxide and depletion layers isolate channel from two
conductive layers (Gate) and (Substrate).
These isolation layers again form caps: C GC and C BC .
C GC is an oxide cap but C BC is a depletion cap.
Oxide cap is less efficient:
ox = 0.34 pF Cm si = 1.06 pF Cm
si 3 ox
31
MOST
Oxide cap is independent of the applied voltage!
The applied voltage on C GC and C BC control the charge in residual
channel and so the current.
Current establishes if VGS > VT (threshold voltage) for VDS > 0 .
32
MOST
pmos and nmos need substrate material of opposite type
Fig 1.5
N-well CMOS technology
33
MOS Capacitance (Oxide)
ox
C GC = WLC ox C ox = (1-4)
t ox
Examples:
For 0.25m technology =

tox 4=
nm 40 A
Cox = 8.5 fF m 2 Very efficient capacitance
t ox = 50nm Cox = 6.8 10 8 F cm 2 = 0.68 fF m 2

Very old
technology WL = (50 5) m 2 C GC = 0.17 pF = 170 fF
For modern technologies: C GC = 2.125 pF (WL = 250 m 2 )

34
MOS Capacitance (Junction)
si
C BC = WLC j Cj = (1-5)
t si
Where t si is the thickness of depletion layer between channel and bulk.

t si depends on the voltage across the depletion layer V and on the
BC
N
doping level SUB of the substrate.
For and abrupt junction: si = 1.06 pF Cm

2 si ( j VBC ) j =
kT
Ln
N c N SUB
t si = q ni
2
qN SUB
ni = 1.5 1010 cm 3 @ 27 c
j is the reverse bias voltage (some times referred to as 0 )
is the bulk-channel junction built-in voltage 35
Normally VBC = VBS (channel and source potential the same at the source side)
kT N
Note: As F = Ln SUB if N C = N SUB j = 2 F
q ni
It shows the case where the created channel
Note: V R t si C j carrier concentration NC is equal to that of NSUB!
Note: j VBC = j VB + Vch

For Vch = VD since VD > VS (as in nmos p-sub is grounded
so VD VSUB is more reversed biased) so t si is thicker in
Drain side!
36
for N SUB = 3 1014 cm 3 ; n + , N C = 2 1017 cm 3 :
Cox = 0.68 fF m 2
Old technology:
j = 0.68V Almost 1/10 of C ox =
0.68 1015
108
F / cm=
2
6.8 108 F / cm 2
C j = 0.67 10 8 F cm 2
for VBS = 0 : t si = 1.73m
C BC = 15 fF
Note: The depletion layer thickness (1730 nm) >> Oxide

thickness (50nm) so always:
C BC << C GC
37
Model MOST-JFET
MOST is actually a parallel connection of a MOST and a JFET
(parasitic) which is usually common for all MOST (single
substrate). Note that JFET is always off.
Gate control is seen as a MOST(CMOS) and the bulk control is
regarded by JFET in this model!
The effect of parasitic JFET in a MOST is shown in VT value by
(gamma) factor. This is so called body factor.
Fig 1.6
MOSFET-JFET Model
38
Model MOST-JFET
2 si qN SUB
= V 1 / 2dimension (1-6)
C ox
By the expressions of C BC and C GC we can write:
si si qN SUB
C BC = WLC j = WL = WL
2 si ( j V BS ) 2( j VBS )

qN SUB
C = WLC
GC ox
C BC si qN SUB 1 2 si qN SUB 1
= . = .
C GC C ox 2( j VBS ) C ox 2 ( j VBS )
C BC C
= 2 j VBS = BC 2 j + VSB (1-7)
C GC C GC
39
Model MOST-JFET
The depletion charge QD contributing to threshold voltage is
function of VBS . This charge depends on the depletion thickness
t si as given by QD = qN Bulk t si so:
QD qN Bulk 2 si ( j VBS )
= (1-8)
C ox C ox qN Bulk t si

QD 2qN Bulk si
= 2 | F | VBS (1-9)
Cox Cox *
The minimum voltage needed on surface to push down the depletion
region under channel is j = 2 | F | , or the voltage to just create
mobile electrons (charges). kT N SUB
Recall: F = Ln for N C = N SUB
q ni
j = 2 F 40
Model MOST-JFET
Q
equation (*) for 1) VBS = 0 is --->C D = 2 | F |
2) VBS < 0 is -------------->
ox Q
= 2 | | V
D
F BS
C
so defining VT 0 for VT when VBS = 0 , it is obvious that VT is
ox
greater than VT 0 for VBS < 0 as follows:
VT = VT 0 + ( 2 | F | VBS 2 | F | ) (1-10)
In other words, say in NMOS, when VBS < 0 or source/channel

voltage is higher respect to bulk there are positive charges on the
top plate of C CB (due to charge in depletion region). Therefore in
order to cancel these extra charges the more positive voltage than
VT 0 must be applied on top plate of C so that its bottom plate
GC
(i.e. channel) produces more negative charges to account for
depleted positive charges on the surface.
41
Model MOST-JFET
So body factor is directly proportional to the ratio of controlling
caps C BC and C GC .
C BC
Note: The proportionality factor C is due to the voltage dependence of
the bulk junction capacitance C BC and so in (1-7) it can be seen that
GC
is voltage independent.
C
A Definition: = n 1 = BC = >0 (1-11)
CGC 2 j VBS
Note: n depends on the applied voltageVBS , whereas does not.

Parameters and n are the first two parameters of the MOST
model that depends on N SUB and C ox values.
42
Model MOST-JFET
Example:
For:
Cox = 6.8 10 8 F cm 2 , nsub = 3 1014 cm 3
= 0.15V 1/ 2 for : VBS = 0 n = 1.09
But for:
nsub = 1016 cm 3 = 0.86V 1/ 2 , n = 1.49
Note: GAMMA ( ), is a constant SPICE model parameter

not n. It is obvious that n is bias dependent.
43
MOST Threshold Voltage
VT 0 is obtained from semiconductor physics for VBS = 0 :
Qox QD
VT 0 = GB + 2 F (1-12)
C ox C ox
With + for nMOST and for pMOST. It is independent of the voltage

applied.
44
Bulk Semiconductor Potential, F
qF Ei (bulk ) EF
p-type Si: Ec
kT
F = ln( N A / ni ) > 0 qF
Ei
q EF
Ev
n-type Si: Ec
EF
kT |qF|
F = ln( N D / ni ) < 0 Ei
q Ev
In a band structure picture, the Fermi level can be considered to be a hypothetical
energy level of an electron, such that at thermodynamic equilibrium this energy
level would have a 50% probability of being occupied at any given time.
45
VT 0 terms:
1) GB is the difference in the work function between the gate

material and the bulk material.
With n+ polysilicon with N G doping for gate &
for p-bulk doping of N B (nMOST):
kT N kT N kT N N N B [3 1014 1016 ] cm 3
GB =
Ln G Ln B =
Ln G 2 B
q ni q ni q ni N G 2 1019 cm 3 (1-13)
for a pMOST having n-bulk doping N B :
N kT N N
GB =
kT
Ln G Ln B =
kT
Ln G N B [3 1014 1016 ] cm 3 (1-14)
q ni q ni q NB
46
2) Charge Qox represents the positive charges (in C cm ) at the silicon-
2
oxide interface. New technology tries to minimize them to avoid VT 0

drift. In SPICE Qox is represents by NSS .
Flat Band Voltage:
Qox
VFB = GB (1-15)
C ox
It is the gate-source potential that causes no band bending in the silicon.
47
3) The surface potential at the source side of the channel under strong
inversion is 2 F (PHI in SPICE).
Its value is obtained from the distance between the Fermi level (in the
bulk) and the middle of the energy bandgap of the semiconductor
material. It also represents the band bending in strong inversion:
kT N sub
F = Ln (1-16)
q ni
+ for nMOST and for pMOST.

So F is a measure of the doping level, as well as conductivity.
48
4) The depletion charge QD which depends on the depletion layer thickness t si :
2 si ( j VBS ) 2 si qN B ( j V BS )
QD = qN B t si
QD
=
qN B
= (1-17)
C ox C ox qN B C ox
QD
= ( j VBS ) 2 | F | Note: built-in junction potential
Cox
for (VBS = 0) j 2 | F |
QD
= 2 | F | VBS (1-18)
C ox
Note: VBS is negative such that VBS and 2 | F | add up!

VT is then as follows:
VT = VT 0 ( (2 | F | VBS ) 2 | F | ) (1-19)
in VT represents the body effect (or the effect of parasitic JFET)

49
Derivation of I/V Characteristics
Consider a semiconductor bar carrying a current I . If the charge density
along the direction of current is Qd coulombs per meter and the velocity
of charge is meters per second then:
I = Qd v (1-20)
Recall:
(Q/m) (m/s) I = Q/t
Fig 1.7
Semiconductor bar
50
Now consider an NFET whose source and drain are connected to ground
(Fig1.8a).The inversion charge density produced by the gate oxide cap. is
proportional to VGS VT . For VGS VT , any charge placed on the gate must
be mirrored by the charge in the channel, yielding a uniform channel
charge density equal to:
Oxide capacitance
per unit area Qd = WC ox (VGS VT ) (1-21)
Fig 1.8a
Channel charge (equal source and drain voltage)
51
Now suppose that the drain voltage is greater than zero (Fig 1.8b). The
local voltage difference between gate and channel varies from VG to VG VD
Thus the charge density at a point x along the channel is:
Qd ( x) = WC ox (VGS V ( x) VT ) (1-22)
Where V (x) is the channel potential at x.
Fig 1.8 b
Channel charge (unequal source and drain voltage)
52
From (1-20) the current is given by:
I D = WC ox (VGS V ( x) VT ).v (1-23)

dV ( x)
v = n (1-24)
dx
dV ( x) (1-25)
I D = WC ox (VGS V ( x) VT ) n
dx
Considering the boundary conditions V (0) = 0; V ( L) = VDS we obtain:
L VDS
I D dx = WC ox n (VGS V ( x) VT )dV
(1-26)
Note: L
x =0 V =0 is the
W 1 effective
I D = n C ox [(VGS VT )VDS VDS ]
2
(1-27) cannel
L 2 length 53
Regarding (1-27)
Fig 1.9
Drain current versus Drain-source voltage 54
If in (1-27), VDS << 2(VGS VT ) then:
W
I D n C ox (VGS VT )VDS
L (1-28)
1
Ron = (1-29)
W
n C ox (VGS VT )
L
Fig 1.10
Linear operation in deep triode region 55
In reality the drain current does not follow the parabolic behavior
for VDS > VGS VT (Fig 1.11), and becomes relatively constant
(saturation region)
Fig 1.11
Linear operation in deep triode region 56
The density of inversion layer charge is proportional to VGS V ( x) VT
So if V (x) approaches VGS VT , then Qd drops to zero (Pinch-off).
As VDS increases further the point at which Qd equals zero gradually
moves toward the source (Fig 1.12). Now reconsidering (1-26) with
x = 0 to x = L pinch off and V ( x) = 0 to V ( x) = VGS VT we come to:
1 W 1 W
ID = n C ox (VGS VT ) 2 n C ox (VGS VT ) 2 (1-30)
2 L pinch off 2 L
Almost
independent
of drain-
source
voltage
Fig 1.12
Pinch-off behavior 57
I DS
VBS = 0
Fig 1.14
Plot of I DS versus VGS & V BS
VBS high
VGS
VT 0 VT
Reduce IDS by adding n as a correction factor:
kp W
kp W 2n L (VDS sat ) 2
for VDS sat = VGS VT
I DS sat = (VGS VT ) =
2
2n L kp n W V VT
(VDS sat ) 2 for VDS sat = GS seen later!
2 L n (1-31)
In actualityVDS sat is always smaller than VGS VT as seen in Spice, so justifying n
58
I DSFrom (1-34)
Linear Saturation Slope :
The dashed
VGS * plot shows
I DS sat * I D sat
against
V BS = 0 VDS = VDS sat
= VGS VT !
VDS sat * V DS which is a
W
RDS : I D n Cox (VGS VT )VDS Fig 1.15 parabola.
L
Plot of I DS versus VGS & V DS
Correction of Linear region eqn: making use of n as a correction factor:

Needs
W 1 W n
I D = nCox [(VGS VT )VDS VDS ] I D = nCox [(VGS VT )VDS VDS ]
2 2
correction!
L 2 L 2
(1-32)
V V
VDS sat = GS T
n 59
Channel Length Modulation
As VDS increases beyond VDS sat as a result of the extension of the
depletion layer charge at the drain into the channel toward the source
(Fig 1.16) over a distance L , the I D current is slightly increased.
The voltage drop over L is about VDS VDS sat , so the channel is
reduced over a distance L from L to Lsat . This can be represented
as follows:
1 1 1 1 L
Note : = = (1 + )
Leff L L L(1 L ) L L
L Unit: 1 V
kp W
I DS sat = (VGS VT ) 2 (1 + (VDS VDS sat )) (1-33)
2n L
Parameter depends on L (inversely), derived later.
LAMBDA in SPICE
60
Channel Length Modulation
VGS V DS V DS sat
t ox
Lsat L
LD LD
Leff
Lm
Fig 1.16
Channel length modulation
61
Effective channel length & width
Effective channel length and width (not due to channel length
modulation)
The effective channel length Leff is given by
Leff = Lm 2 LD DL (1-34)
Where Lm is the channel length drawn in the layout (on mask)

LD is the under diffusion and
DL is a reduction because of photolithography and etching
Similarly
Weff = Wm + DW (1-35)
62
Small signal parameters
Note: g mb represents the transconductance from the bulk input-
node voltage Vbs to the output current I ds . It is actually the
transconductance of the parasitic JFET.
Fig 1.17
Small signal model 63
Small signal parameters in saturation
Since a MOSFET operating in saturation produces a current in response to
its gate-source overdrive voltage, we can define Transconductance to
define how well the device converts voltage to current. Transconductance
is denoted by g m and expressed as:
I D
gm = |VDS =cte
VGS
W
= n C ox (VGS VT ) (1-36)
L
Transconductance represents the sensitivity of the device. it can be shown
that:
W
g m = 2 n C ox I D (1-37)
L
2I D
= (1-38)
VGS VT 64
Remember from (1-36):

I D
gm = |V =cte
VGS DS
W kp W
= n C ox (VGS VT ) = 2 (VGS VT )
L 2n L
W kp W
= 2 n C ox I D = 2 ID
L 2n L
2I D
=
VGS VT
65
Fig 1.13 shows g m behavior
W W
g m = nCox (VGS Vth ) g m = 2 nCox ID 2I D
L L gm =
Veff
Fig 1.13
MOS transconductance as a function of overdrive and drain current
66
Bulk transconductance g mb
From (1-30) and (1-19):

kp W kp W
I DS = (VGS VT ) =
2
(VGS [VT 0 + ( 2 | F | VBS 2 | F | )]) 2
2n L 2n L
I DS I DS VT
g mb = = .
VBS VT VBS
Recall
2 si qN SUB
=
C ox so is independent of VBS and
1 si qN sub
n is dependent on VBS
n 1 = =
2 j V BS C ox 2( j VBS )
67
kp W VT
g mb = 2 (VGS VT ).
2n L VBS
VT 1 1
= gm . = g m ( . )
VBS 2 2 | F | VBS

= .g m (1-39)
2 2 | F | VBS
C BSQ
From (1-11) g mb = g m = (n 1) g m (1-40)
C ox
g mb (1-41)
n = 1+
gm
68
Output Resistance ro
It is the result of the channel-shortening effect by VDS (channel length
modulation).
I DS
go = I Dsat (1-42)
VDS
1
ro (1-43)
I Dsat
69
1 W
I DS = n C ox (VGS VT ) 2
2 L
Using Taylor approximation:
I D Leff
I DS = I DS sat + [ . ]VDS
Leff V DS
n C oxW Leff
I DS = I DS sat + { (VGS VT ) }.{
2
}.(VDS Veff )
2 Leff
2
VDS
2k si 0
Leff = L L = L 0 + VDS Veff = L K DS . 0 + VDS Veff
qN SUB
Leff K DS
=
VDS 2 0 + VDS Veff

= I DS sat 1 + .(VDS Veff )
K
I DS DS (1-44)
2 L 0 + VDS Veff
70
I DS = I DS sat (1 + (VDS Veff )) (1-45)
where :
K DS
=
2 L 0 + VDS Veff
1 2 L 0 + V DS Veff 2L qN A (1-46)
ro = = = ( 0 + VDS Veff )
I DS K DS I DS I DS 2 si
Note: ro ( L, VDS )
71
Channel length
ro modulation and DIBL
Impact
Ionization
Channel length
modulation VDS
Fig 1.18
72
Parameter depends on the channel length L, yet assumed to be
constant in spice. Therefore another parameter is chosen, taking into
account the dependence on channel length L:
Equation (1-42) can be rewritten as follows:
1 VE .L
ro = = (1-47)
g ds I Dsat
Comparing (1-42) and (1-46) : Seen in a moment!
1 VA 1
VE = = = (V/m) (1-48)
L L dX d / dVDS
2 (VDS Veff + 0 )
VE = (1-49)
K DS
73
VE is the Early voltage per unit-channel length in analogy with the
Early voltage of a Bipolar transistor. It is different for nMOST and
pMOST for the difference in substrate doping level: 2k si 0
K = DS
qN SUB
Note: Early voltage Recall :
2 (VDS Veff + 0 )
is independent of L VE =
K DS
The more doping level, the less extension of the depletion layer
into the channel the larger substrate doping, the larger the
Early voltage.
Example:
N-well CMOS process: VEn = 4V mL ,VEp = 7 V mL
For the same channel length the output resistance of the
nMOST is thus smaller than that of the pMOST, in an n-well
CMOS process.
It is opposite for a p-well CMOS process: VEp = 4V mL ,VEn = 7 V mL
74
Another point of view:
k' W
ID = (VGS VT ) 2 Leff = L X d
2 L
k' W
ID = (VGS VT ) 2
2 Leff
I D k' W dLeff I D dX d
= (V V ) 2
. = . (1-50)
VDS 2 GS T
2 Leff dVDS Leff dVDS
So Early voltage is defined analogous to BJT

dX d
( )
ID dX d 1 1 dVDS
VA = = Leff ( ) = = (1-51)
I dVDS Leff
( D )
VDS
75
1 1
VE = = (1-52)
Leff ( dX d )
dVDS
2k s 0 (1-53)
Xd = ( 0 + VDS Veff )
qN A
dX d K DS
=
dVDS 2 0 + VDS Veff
dX d
( )
dVDS K DS (1-54)
= =
L 2 L 0 + VDS Veff
1 2 0 + VDS Veff
VE = = (1-55)
L K DS
76
1 I D I D dX d ID K DS
ro = = = (1-56)
VDS Leff dVDS Leff 2 0 + VDS Veff
ID
ID
VDS
VA
Fig 1.19
Early Voltage
77
Small signal analysis examples
Example 1
VT 0 = 0.7V
I DS = 0.86V 1/ 2
ids
n = 1.49 (VBS = 0)
k ' = 30 A V 2 = k p 2n
W 50
VIN for VIN = 1.4V , = , vin = 10mVrms
vin L 5
I DS , ids , g m , g mb , ro = ?
78
kp W 50
(1-30) I out = (VGS VT ) = 30 (1.4 0.7) 2 = 0.147 mA
2
2n L 5
kp W 50
(1-31) g m = 2( ) (VGS VT ) = 2 30 (1.4 0.7) = 0.42 mS ( Simens)
2n L 5
0.86
g mb = gm = 0.42 = 0.206 mS
(1-38) 2 2 F VBSQ 2 2 F
Note that 2 F = 0.684V
for vin = 10mVrms I out = g m vin = 4.2 Arms 4.2 2 = 5.94 A

for n-well process: V En = 4 V mL V En .L = (4 V mL) 5m = 20V
VEn .L 20
ro = = = 136k
I out 0.147 mA
79
Example 2: Amp with active load
VT 0 = 0.7V
= 0.86V 1/ 2
Vout n = 1.49(VBS = 0)
M1
RL
k ' = 30 A V 2
V DD = 8V
Rs
Vin if
+vin Vdd
RL , Av = ? for Vout = 8 / 2 = 4V
80
Vout 4
RL = = = 27.2 k
I DS 0.147 mA
RL = RL || ro = 27.2 || 136 = 22.7k
'
Av = g m RL = 0.42mS 22.7 k = 9.5V V

'
from (1-33) and (1-46)

2 I DS VEn L 2VEn L
Av = g m ro = . = (1-57)
VGS VT I DS VGS VT
The voltage gain is set by VGS and L only (in strong inversion)
For high gainVGS VT must be chosen smallest possible (0.2 V)and L
as large as possible.
2 4 V mL 10
L = 10 m | Av |= = 400V / V 52dB
0.2 81
Determine W: The larger W, The larger I DS and g m but the smaller ro .
For W = 5m
I DS = 6 A, g m = 60mS

ro = 6.7 M
Note: Do not increase I DS than necessary (for power consideration)
82
Example of MOST Diode
VGS = VDS VDS > VGS VT
Always in saturation I IN
There is no conduction for negative v iin
values so it is said to be a diode.
I D sat
for source grounded: VGS = VT +
k'W L
v gmv iin
Used for DC-shifter in MOS.
Voltage set by I and W/L.
AC voltage: iin g m
AC resistance is 1 g m (normally k ) shunted by ro
(still 1 g m ) 83
Making use of a voltage source; a) no body effect, b) w body effect:
if source is not grounded VBS must be

included for VT calculation (1-10), so I IN
increasing VGS . But g m is not changed iin
since I DS is constant, (1-30), (1-31) and
VSS = 3V
(1-32)!
(b)
I IN
For p-well process iin
VSS = 3V
(a) 84
Example (No Body Effect)
VT 0 = 0.7V , = 0.86V 1/ 2 , n = 1.49(VBS = 0)
W
k = 30 A V , = 50
' 2
L
VDS = VGS = ? for I in = 0.2mA, AC swing : 10%
0.2mA
V = VDS = VGS = 0.7 + 6
= 0.7 + 0.667 1.52V
30 10 10
2 I DSQ W
gm = = 2 k' I DSQ = 2 30 10 6 10 0.2mA = 0.49mS
VGS VT L
1 I D sat
= 2.04k Veff = VGS VT 0 = = 0.667
gm k'W L
85
10% AC current:
I AC = 0.10 (0.2mA) = 0.02mA
0.02mA
= g m vin vin = = 40.8mVP = 29mVrms
0.049mS
Example (With Body Effect)
for VS = 3V VT = 0.7 + 0.86( 0.6 + 3 0.6 ) = 1.66V
V = VGS = VT + Veff = 1.66 + 0.667 = 2.48V
Note: Veff not changed since IDS is not.
86
Examples of Source follower
I SS is constant so VGS must be constant too:
P-well
Vin Vout = VGS AC + DC
Vout
VIN
vin
1 I SS
Gate is @ AC ground Rout = = 2.04k
gm Rout =
1
gm
87
For ground bulk:
I SS
Vout = Vin VT 0 ( 2 | F | +Vout 2 | F |)
k'W L
In the above eqn the channel-length modulation (rds) is ignored. (1-58)
Taking it into account:
I Bias
Vout =Vin Vtn 0 ( Vout + | 2F | | 2F |)
nCox (W / L) (1 + (VDD Vout VDS sat ) )
1
2
As it can be seen from (1-58)

the gain is not unity! This is
the result of the bulk effect or Vout
parasitic JFET. V IN
vin
I SS
88
We can draw the parasitic JFET explicitly (drain and source are common
with MOST but its gate i.e. bulk is grounded.). 1
g mb 1 1
Av = = =
1 1 g n
Vdd + 1 + mb
g m g mb gm (1-59)
1 1
gm g mb
VIN
vin
I SS
Fig 1.20a,b
Parasitic JFET 89
Or using MOS small-signal model directly:
M1
Vout
V IN
vin
M2 I SS
ro = rds1 || rds 2 || 1 / g s1 || 1 / g m1
1
vout Gs1 g m1 ( vin vout ) =0 where Rs1 = =rds1 || rds 2 ||1/ g s1
Gs1
vout g m1 g m1
=Av = = ; Note: g s1 =g mb1
vin g m1 + Gs1 g m1 + g s1 + g ds1 + g ds 2
90
Description: Consider the MOS T-Model (Fig 1.21)
Note that since is = g m v gs passes through rs = 1 , so the current into
gm
gate (G terminal) is zero, thereby input impedance is infinity!

D
i s = g m v gs
G
So the AC small signal model of
rds
the circuit is really as shown in is
Fig 1.20b (see next page). Also
the model is shown in Fig 1.22 S
(without rds )
Fig 1.21
MOS T-Model 91
Note: If Vin = 0 V gs = 0 .
For Vin 0 we can calculate Vs = Vout as
a voltage divider of 1 g m and 1 g mb , or
is = g m v gs
according to T-Model we know that in vs = vo
any case i S is as follows (Fig 1.21): iin = 0
i = g m v gs
i S = g m v gs
g m v gs g m (vin vo )
vo = v s = = (1-60)
g mb g mb
gm g m vin
vo (1 + )= Fig 1.22
g mb g mb
1
g mb 1 1 (1-61)
Av = = = As shown
1 1 g n
+ 1 + mb before in
g m g mb gm
See (1-40) (1.59) 92
1 1
Rout =
g m + g mb + g 0 g m + g mb (1-62)
So bulk effect reduces gain and increases the VGS too!

It should be noted although we draw both Vin voltage source, and g m vgs
current source.
In the T-Model in Fig 1.22 the current going through 1 g m is always
equal to g m vgs = is as shown in Fig 1.21.
93
MOS Capacitances
VG
VS VD
C GS C ox C GD
n+ n+
VG C BC
C jDBt
C jSBt
L eff
p sub L ov L ov
94
MOS Capacitances
C oxt = C ox W L eff
ox t stands for
C ox = , Oxide (isolation) Cap.
t ox total
C BCt = C jBC W L eff
Cj Depletion Region Cap.
C jBC = ,
VBC
mj
(junction Cap.)
1
j

NA ND
j = 0 = VT ln 2

ni
j is the built-in potential of an open circuit pn junction. (PB)
95
MOS Capacitances
C jSBt = AS C jSB + PS C jswSB
Cj C jswSB
C jSB = mj
, C jswSB = m jsw
VBS VBS
1 1

j jsw
C jDBt = AD C jDB + PD C jswDB

Cj C jswDB
C jDB = mj
, C jswDB = m jsw
VBD
1 1 VBD
j
jsw
1/ 2
q NB
C jsw = si = si , t si = Thickness of Depletion Layer
t si 2 jsw

m j = m jsw = 1 / 3,...,1 / 2
AS is the Source area, and PS is the Source perimeter.
AD is the Drain area, and PD is the Drain perimeter.
96
MOS Capacitances (Saturation)
In Saturation Region Overlap Capacitance between Gate and Source
CGS = CGSov+ 2/3 Coxt Overlap Capacitance between Gate and Drain
CGD = CGDov
CSB = CjSBt+ 2/3 CBCt
CDB = CjDBt Channel-Bulk junction Capacitance
Source-Bulk junction Capacitance

D
C GD C DB Drain-Bulk junction Capacitance

G B
C GS CSB
S
97
MOS Capacitances (Triode)
In Triode (linear) Region D
CGS = CGDov+ 1/2 Coxt C GD C DB

CGD = CGDov+ 1/2 Coxt G B
CSB = CjSBt+ 1/2 CBCt
CDB = CjDBt+ 1/2 CBCt C GS CSB
98
MOS Capacitances (OFF)
No channel is existent. Gate-to-source and gate-to-drain

caps are only due to overlap/fringing caps:
C gs = C gd = WLov Cox
Source-to-bulk and drain-to-bulk caps are smaller when
no channel is existent:
Csb 0 = As C j 0 + Ps C j sw0

Cdb 0 = Ad C j 0 + Pd C j sw0
99
Example of MOST as a switch
Resistive Load
Vout RL
=
Vin RL + RDS
VG = 10V VG = 10V
VOUT
VOUT vout
vout
VIN VIN
RL = 10k vin RL = 10k
vin
Fig 1.23a,b
MOST as switch with resistive load
100
Device is in Triode region:
1
RDS = (1-63)
W
nCox (VGS VT VDS )
L
From (1-10):
1
RDS = (1-64)
[VG Vout VT 0 ( 2 | F | +Vout 2 | F | )]
W
where = n C ox
L
Since VG is large (i.e. VG >> Vin ) RDS is small, so Vout Vin .
101
Vout
100 VT
10
W
=1 VT 0 = 0.7V
L
Vin Vin
Fig 1.24a,b
102
The larger the transistor, the smaller the resistance.
The lower the input voltage (so the output voltage), the smaller the
resistance
The value of the threshold voltage increases with input voltage as
shown in Fig 1.24b (for VBS 0 due to body effect)
103
Capacitive Load
Used in switched capacitor and CMOS logics.
VG
VG
Vout Vout
Vin Vin CL
CL
Fig 1.24a,b
MOST as switch with capacitive load
104
MOS Transistor as a switch
Symbol
Bulk
A B
(S/D) (D/S)
A B
C(G)
On Characteristics of a MOS Switch

Assume operation in Triode region (VDS < VGS VTH ) and VDS is small.
Thus:
VDS 1
R ON = =
iD W
C ox ( )(VGS VTH )
L
OFF Characteristics of a MOS Switch

If VGS < VTH, then iD=IOFF=0 when VDS0.
If VDS > 0, then: 1 1
R ON = =
iD I OFF
105
Switched-Capacitor Resistor
Equivalent
106
Equivalent
107
Equivalent Example
108
MOS Switch Voltage Range
If a MOS switch is used to connect two circuits that can have analog signal
that vary from 0 to 5V, what must be the value of the bulk and gate voltages
for the switch to work properly?
Bulk
(0 to 5V) (0 to 5V)
(S/D) (D/S)
Circuit Circuit
2 1
To ensure that the bulk-source and bulk-drain pn junction are

reverse biased, the bulk voltage must be less than the minimum
analog signal for a NMOS switch.
To ensure that the switch is ON, the gate voltage must be greater
than the analog signal plus the threshold for a NMOS switch.
Therefore: VBulk 0V
and VG > 5V+VTH
Also, VG(OFF) 0V
Unfortunately, the large value of reverse bias bulk voltage causes
the threshold voltage to increase.
109
Influence of the ON Resistance on MOS Switches
Finite ON Resistance:
vC(0)=0 vC
+ - + -
C G C
Vin= 2.5V Vin > 0 RON
Example:
Initially assume the capacitor is uncharged. If VG(ON) is 5V and
is high for 0.1s, find the W/L of the MOSFET switch that will
charge a capacitance of 10pF in five time constants
( K n = nCox = 110 A/V 2 and Vtn = 0.7 V )
110
Influence of the ON Resistance on MOS Switches
Solution:
The time constant must be equal to 100 ns
= 20 ns . Therefore
20 ns 5
RON must be less than = 2 k .
10pF
The ON resistance of the MOSFET (for small VDS) is:
1 W 1 1
RON = = = = 1.06
K N (W / L)(VGS VTH ) L RON K N (VGS VTH ) 2 k 110 A / V 2 4.3
Comments:
It is relatively easy to charge on-chip capacitors with minimum
size switches.
Switch resistance is really not constant during switching and the
problem is more complex than above.
111
Including The Influence of the Varying ON Resistance
Gate-Source Constant:
W W vC(0)=0
g ON (t ) = K ( ) [(VGS (t ) VTH ) VDS (t )] = K ( ) [(VGD (t ) VTH )]
L L + -
1 g (0) + g ON ()
g ON avg = = ON C VG
rON avg 2
Vin`
VDS (0) = VIN , VDS () = 0, VGS (0) = VGS () = VGS = VDD
K W K W K W
g ON avg =( )(VGS VTH ) ( )VDS (0) + ( )(VGS VTH )
2 L 2 L 2 L
W K W
= K ( )(VGS VTH ) ( )VDS (0)
L 2 L
W K W (1-65)
= K ( )(VDD VTH ) ( )VIN
L 2 L
112
Including The Influence of the Varying ON Resistance
Gate-Source Varying: VG
W
g ON (t ) = K ( ) [(VGS (t ) VTH ) VDS (t )] +
L VGS
1 g (0) + g ON () -
g ON avg = = ON
rON avg 2 +
K W K W Vin vC(0)=0
g ON avg = ( )(VGS (0) VTH VDS (0)) + ( )(VGS () VDS () VTH ) -
2 L 2 L
Note : VGS (0) = VDD , VDS (0) = VIN , VGS () = VDD VIN , VDS () = 0
K W K W W
g ON avg = ( )(VDD VIN VTH ) + ( )(VDD VIN VTH ) = K ( )(VDD VIN VTH )
2 L 2 L L
113
Switch ON Resistance Example
Assume that at t=0, the gate of the switch shown is taken to 5V. Design
the W/L value of the switch to discharge the C1 capacitor to within 1% of its
initial charge in 10ns. Use the MOSFET parameter for previous example.
5V C2=10pF
0V 0V
+ -
- vOut(t)
+
5V 10pF +
- C1
Solution:
Note that the source of the NMOS is on the right and is always at
ground potential so there is no bulk effect as long as the voltage
across C1 is positive. The voltage across C1 can be expressed as:
t
v C1 = 5 exp( )
R ON C1
114
Switch ON Resistance Example
At 10ns, VC1 is 5/100V (0.05V), therefore:
10 8 103
0.05 = 5 exp
11
= 5 exp exp(GON 103 ) = 100
RON 10 RON
ln(100)
GON = = 0.0046 S
103
Note that the ON resistance is time variant :
VGD (0) = VDD 5V = 0

GON = K [VGD (t ) VTH ] ,
W
L V () = V 0V = 5
GD DD
g (0) + g ON ()
g ON avg = ON ; VGS (t ) = VGS (0) = VGS () = 5V, VDS (0) = 5V, VDS () = 0V
2
Use equation for constant gate-source voltage (1-65):
W K W 110 10 6 5 W
0.0046 = K (VGS VTH ) VDS (0) = 110 10 6 4.3
L 2 L 2 L
W W 0.0046
= 198 10 6 = = 23.2 23
L L 198 10 6
115
Influence of The OFF State ON Switches
The OFF state influence is primarily in any current that flows from
the switch to ground.
An example might be:
vin
- vOut(t)
+
RBulk CH vCH +
-
Typically, no problems occur unless capacitance voltages are held for

a long time. For example:
[
v out ( t ) = v CH 1 e t /( R Bulk C H ) ]
If R Bulk 109 and C H = 10 pF, the time constant is 109 10 11 = 0.01s.
116

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Electronics III

Instructor: Omid Shoaei

And Special Issues

Analysis and design of Analog Integrated Circuits, Gray

Design of Analog Integrated circuit & systems, Kenneth R.

Microelectronic Circuit, Adel S. Sedra, Kenneth C. Smith,

Analog Integrated Circuit Design, David A. Johns ,Ken

Midterm Exam: Aban 16th (Nov. 7th), Thursday

2 si ( j VBC ) or ( + V ) Where VR = VBC is the

JFET DC model in Saturation:

Without proof (analogy with MOSFET; seen later) :

For 0.25m technology =

t ox = 50nm Cox = 6.8 10 8 F cm 2 = 0.68 fF m 2

For modern technologies: C GC = 2.125 pF (WL = 250 m 2 )

Where t si is the thickness of depletion layer between channel and bulk.

For and abrupt junction: si = 1.06 pF Cm

Note: j VBC = j VB + Vch

Note: The depletion layer thickness (1730 nm) >> Oxide

greater than VT 0 for VBS < 0 as follows:

In other words, say in NMOS, when VBS < 0 or source/channel

Note: n depends on the applied voltageVBS , whereas does not.

Note: GAMMA ( ), is a constant SPICE model parameter

With + for nMOST and for pMOST. It is independent of the voltage

1) GB is the difference in the work function between the gate

for a pMOST having n-bulk doping N B :

oxide interface. New technology tries to minimize them to avoid VT 0

Flat Band Voltage:

+ for nMOST and for pMOST.

Note: VBS is negative such that VBS and 2 | F | add up!

in VT represents the body effect (or the effect of parasitic JFET)

Where V (x) is the channel potential at x.

I D = WC ox (VGS V ( x) VT ).v (1-23)

Correction of Linear region eqn: making use of n as a correction factor:

Where Lm is the channel length drawn in the layout (on mask)

Remember from (1-36):

From (1-30) and (1-19):

Equation (1-42) can be rewritten as follows:

So Early voltage is defined analogous to BJT

Note that 2 F = 0.684V

for vin = 10mVrms I out = g m vin = 4.2 Arms 4.2 2 = 5.94 A

Av = g m RL = 0.42mS 22.7 k = 9.5V V

from (1-33) and (1-46)

Note: Do not increase I DS than necessary (for power consideration)

if source is not grounded VBS must be

for VS = 3V VT = 0.7 + 0.86( 0.6 + 3 0.6 ) = 1.66V

V = VGS = VT + Veff = 1.66 + 0.667 = 2.48V

Note: Veff not changed since IDS is not.

As it can be seen from (1-58)

gate (G terminal) is zero, thereby input impedance is infinity!

So bulk effect reduces gain and increases the VGS too!

C jDBt = AD C jDB + PD C jswDB

Source-Bulk junction Capacitance

C GD C DB Drain-Bulk junction Capacitance

In Triode (linear) Region D

CGS = CGDov+ 1/2 Coxt C GD C DB

No channel is existent. Gate-to-source and gate-to-drain

On Characteristics of a MOS Switch

OFF Characteristics of a MOS Switch

To ensure that the bulk-source and bulk-drain pn junction are

Typically, no problems occur unless capacitance voltages are held for

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