FPGA IMPLEMENTATION OF HARD ERROR CORRECTION

TECHNIQUE USING PARALLEL ARCHITECTURE

MRS. SWETHA K
PG student, Dept. of ECE, DBIT, Bangalore, Karnataka, India
swethaachar221@gmail.com

MR. MURUGESH K
Asst. Professor, Dept. of ECE, DBIT, Bangalore, Karnataka, India
muru.dbit@gmail.com

ABSTRACT: In communication systems and signal processing system digital filters are used
widely. For some cases, the reliability of these systems is vital, to reduce this fault tolerant filter
execution are necessary. Many techniques have been proposed to exploit the filters structure and
properties for achieving fault tolerance. As technology is scaling it enables many filters to
incorporate in complex system. In these complex systems some of the filters are operated in
parallel, for example, by giving the same filter to various input signals. A simple method that
exploits presence of filters given in parallel for achieving fault tolerance has been presented
recently. With this brief, an idea applied here is that error correction codes (ECCs) are used to
protect parallel filters. In ECC each parallel filter is equal to that of a bit. Here the new scheme
allows more efficient protections when the number of parallel filters count are large. The technique
is assessed based on the study of parallel filters finite impulse response showing the effectiveness
in terms of cost and protection.

KEYWORDS: soft error,Error correction codes,Hard error and Filters.

INTRODUCTION

The reliability, efficiency and maintenance of Electronic circuits are a challenging task and to
some extend its critical with increasingly present in the field of automotive, medical, and space
applications. In those applications, the circuits provide some degree of fault tolerance. The
challenges also increased further in intrinsic reliability of advanced CMOS technologies e.g., soft
errors manufacturing variations. A number of techniques have been proposed to protect a circuit
from errors. Many techniques which are used to reduce the manufacturing errors in the circuits as
well as trying to reduce the error by adding redundancy logic without affecting the functionality of
system M.Nicolaids (2005). Another method known as Triple Modular Redundancy (TMR) can
also be used to add redundancy. Commonly a TMR that will triplicate the given design and voting
logic is added to correct errors. In some applications however, it triplicates the power and area of
the design, which may not be acceptable.

Digital filters are one of the most widely used signals processing circuits and many methods have
been given to protect them from error occurrence. Many methods are related to the finite impulse
(FIR) filters and they have used those in the method. In Z.Gao (2012), the relationship between the
input sequence and memory elements of an FIR filter were used to detect errors. Other schemes
like FIR properties at a word level are exploited to also achieve fault tolerance P.Reviriego (2012).
The usage of residue number systems S.Ponterelli (2008) and arithmetic codes A.Reddy (1990)
been proposed to protect fir filters. Finally, the usage of variety implementation structure of the
FIR filters only one redundant module was used to correct errors was proposed by P.Reviriego
(2011). The techniques that are mentioned so far are used in protection of a single filter. That idea
is explored in P.Reviriego(2012), where two parallel filters with the same response that processed
different input signals are considered. It can be shown that with only one redundant copy, single
error correction can be implemented. As a result a significant cost reduction compared with TMR
is obtained.

With this brief, a general scheme to protect parallel filters is presented. As in P.Reviriego(2012),
parallel filters that process different input signals with the same response are considered. The new
approach is based on the application of Error Correction Codes (ECCs) that uses the filter outputs
as the equivalent of a bit in and ECC code word. This is a generalization of the scheme in S.Lin
(2004) and it enables more efficient implementations with the number of parallel filters are large.
There are many other systems which were designed previously to avoid this kind of error but they
were not as much efficient as the proposed method.

The proposed scheme is more efficient in correcting multiple bit error in multiple module. The
remaining detail of this summary introducing the new method for the parallel filters shown in
Section II. In Section III, the proposed Method. Section IV deals a study to illustrate how
efficiently the method works.In section v the conclusion of the proposed method is discussed.

FILTERS WIT INPUTS as SAME RESPONSE

A discrete time filter implements the following equation:

[ ]

= [

]. h [ ] (1.1)

Where a[n] is input provided, the output is given as y[n], the impulse response for the filter is
given by h[l]. When we consider the h[l] for sequence then it is non zero for finite samples, this
type of filter is called as a FIR filter, in other case it is called as infinite impulse response (IIR)
filter. Several structures are there to implement both FIR and IIR filters. These parallel filters are
shown in below Fig. 1.

The filter is found use several channels work in parallel and they are used in communication
systems. Here we are taking the input bits as the a1, a2, a3, a4 etc. The inputs are provided to filter
to the filter block and the outputs are given to the single fault correction block. The inputs are
provided the block were the inputs are calculated with the redundancy bits and they are xored with
all the bits. The bits are added for all the bits and bits are calculated according to input bits which
are given and the variables are calculated and the bits are given to the single fault correction were
the parity bit flag is raised when the output bit is miss matched. That bit has to be corrected
according to the encoded input bits. The concerning property of the parallel filters bi [n] can be
obtaining by the sum of any of the output combination can be obtained by adding the
corresponding inputs ai[n] and resulting with the same filter h[l].

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 Figure 1: Parallel filters with the same response

For example

b [n] + b [n] = (a [ n l] + a [n

l]). h[l] ( 1.2)

This simple observation is used for the development of the proposed fault tolerant implementation.

PROPOSED METHODOLOGY

The new technique used here is related ECCs. Here the operation is based on ECC which takes a
set of k bits and gives a set of n bits by adding together nk as parity check bits are given. The
parity bits are the XOR combinations of the k given bits. The proper designing for these
combinations it is made possible to correct and detect errors. Consider an example, Hamming code
is considered with n=7 and k=4. In this case, the three parity check bits R1, R2, R3 are calculated
as a work as the data bits E1, E2, E3, E4 as follows:

R1 = E1 E2 E3

R2 = E1 E2 E4

R3 = E1 E3 E4
(1.3)

The parity and data bits will be stored and retained back whenever necessary or when any error bit
is found in any one bit also. It will be checked and detected with the data stored and correction will
be done. In the above example considered, an error on E1 will affect three parity bits; on error E2
only in R1 and R2; an error on E3 in R1 and R3; and finally an error on E4 in R2 and R3. As a
result the location of data bits are located and calculated and the correction can be done. The
method can be commonly formulated in terms of the generating GE and parity check HC matrix.

For example considered above, Encoding is done by computing y = x GE and s = y HT is

calculated for the error detection, where the operator is based on module for multiplication and
addition.

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To calculate the error in each bit the syndrome is calculated. The table shows the s bits to their
corresponding error locations are found.

Table 1. Error bit location in the hamming code

S1S2 S3 Error Bit Location Action
000 No error None
101 d3 correct d3
011 d4 correct d4
111 d1 correct d1
110 d2 correct d2
001 P3 correct p3
010 p2 correct p2
100 P1 correct p1

Figure 2: Proposed scheme for a Hamming code and four filters

Each bit can be obtained by using the matrix which is already present and it remains constant. In
case of the present filters y1, y2, y3, y4, the parity check matrix will be

C [ n] = (a [n l ] + a [n l] + xa [n l]). h[l]

c [n] = (a [n l] + a [n l] + a [n l]). h[l]

c [ n] = (ax [n l] + a [n l] + a [n l]). h[l] (1.6)

and the testing and checking of the matrix is done if

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 c [n] = b [n] + b [n] + b [n]
c [n] = b [n] + b [n] + b [n]
c [n] = b [n] + b [n] + b [n] (1.7)

The check errors are calculated by giving z1,z2 and z3. The filters are given with the input and the
filter operation happened inside the block. The inputs are provided with the four and the filter
operation is done were the parity bits are calculated were the syndrome calculation is done were
the transpose of matrix is done .
y [n]
= c [n] b [n]
b [n] (1.8)

The error for each bit is calculated by using the table above were the parity bits will be affected
and the syndrome should be calculated for each matrix. The error bit is calculated by using yc1
and the bit correction can be done by inverting the bit.

1 1 1 1 1 0 0
HC= 1 1 0 1 0 1 0 (1.9)
1T 0 1 1 0 1 1
s = yH is calculated to detect errors. Hamming code is used as it supports the double bit detection
and single bit correction is done. The below table shows the effectiveness of the system when
compared to the previous technique.

Table 2. Resource comparison for four parallel fir filters

Resource types Unprotected TMR Method in [7] Proposed
Slices 2943 9021 7739 6408
Flip-flops 1223 3983 3979 2940
LUTs 5691 17255 13641 12031

Table 3. Resource comparison for eleven parallel fir filters

Resource types Unprotected TMR Method in [7] Proposed
Slices 8095 24804 21284 14421
Flip-flops 3365 10955 10944 6477
LUTs 15652 47453 37510 28330

CASE STUDY

To find the effectiveness of the proposed scheme evaluation of a case study is done. A parallel FIR
filters with a set of 16 bits are taken. A little threshold will be used to compare the errors if is
smaller than the threshold are not considered as errors. As said in Section III, there is no separate
logic sharing for computing decoder and encoder logic to avoid errors .there are 2 considerations
here are the n=7 and k=4 and the other is that n=15 and k=11.these two can be carried out on the
HDL and put into Xilinx and the comparison of previous technique is done as TMR. The tables
above shown will give the comparison of previous technique where the proposed technique is
more effective when compared to previous method in compared to the slices used, flip flops and
error correction. The comparison with the TMR technique is taken into consideration.

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CONCLUSION

A novel technique is used to protect the parallel filters. The ECC is best technique to detect and
correct the errors. The proposed technique is more effective when compared to the size, area, cost
etc when compared to previous methods. This method can also be applied to the IIR filters.

Future work will considered to develop Pipeline Technique and show the method is more
effective. The method can be extended to 128 bits parallel filters input and with the different
impulse outcome for future scope. Here in this work error detection is done for the 128 bits and the
correction is also done for the same as shown in the simulation below. The designing for 128 bits
as well as the comparison of the previous technique can also be done here and the FPGA output
can be obtained. the new filter designing is done to reduce still more area and other parameters.

SIMULATION RESULTS

Figure 3: Encoder with calculation of redundant Figure 4: Encoder with calculation of parity bits
bits

Figure 5: Decoder with input data Figure 6: Decoder with error bit calculation

TL SCHMATIC

Figure 7:RTL schematic for decoder Figure 8:RTL schematic for encoder

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Figure 9: Encoder with calculation of 128 bits Figure 10: Decoder with calculation of error bits

Figure 11: Filter calculation Figure 12: RTL schematic of Encoder & Decoder

Figure 13: output showing the syndrome calculation

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