Submitted Paper

Electric Power Components and Systems
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Modified Synchronous Vector control Design of Multilevel

Inverters for AC Grid Applications
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Journal: Electric Power Components and Systems

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Manuscript ID UEMP-2015-1006.R1
Manuscript Type: Original Article
Date Submitted by the Author: 22-Jan-2016

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Complete List of Authors: MATSA, AMARENDRA; VNIT, ELECTRICAL ENGINEERING

Chaudhari, Madhuri A.; VNIT, Electrical Engineering
Suryawanshi, Hiralal M.; VNIT, Electrical Engineering
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cascaded multilevel inverter, space vector pulse width modulation(svpwm),

Keywords:
power electronics
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URL: http://mc.manuscriptcentral.com/uemp Email: dan.m.ionel@gmail.com

Page 1 of 36 Electric Power Components and Systems
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4 Electric Power Components and Systems, 00:000000, 2015
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6 Copyright
c 1915 Taylor & Francis
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0731-356X / 15 $12.00 + .00
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Modified Synchronous Vector control Design of
13 Multilevel Inverters for AC Grid Applications
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17 AMARENDRA MATSA
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19 M. A. CHAUDHARI
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22 H. M. SURYAWANSHI
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Department of Electrical Engineering,
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26 Visvasvarayya National Institute Of Technology, Nagpur, India.
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29 This article presents a modified synchronous vector control design of a five-
30 level cascaded H-Bridge inverter for integration of distributed generation (DG)
resources to the power grid.The presented control strategy explores the limita-
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31 tions in the conventional synchronous vector control algorithm of grid con-

32 nected converter.The Dynamic Reference point (DRP) approach is considered
33 to improve the performance of grid connected converter. Compared with con-
34 ventional control algorithm, DRP based control algorithm exhibits several spe-
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35 cific advantages, such as increased reliability of the grid interfaced converter,

more active and reactive power injection capacity of the converter and reduced
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cost of the converter. The objectives of control technique of the Distributed
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Generation (DG) interface system are also employed to enhance the standard
38 of the power grid. The Optimized Space vector pulse width modulation (OS-
39 VPWM) control technique is used for grid integration. The simulation and
40 experimental results are presented in order to validate the proposed functional-
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41 ities of the grid interfaced DG system. The effectiveness of the proposed control
scheme is validated with better utilization of DG system, faster dynamics with
42 reduced total harmonic distortion, better power factor, compensated load reac-
43 tive power and fault withstanding capability.
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47 Index Terms-Distributed Generation, Optimized SVPWM, Cascaded H-Bridge
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49 Inverter.
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Address correspondence to :amarmeetsyou@gmail.com
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Electric Power Components and Systems Page 2 of 36
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3 2 Amarendra and Chaudhari
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5 1 Introduction
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8 The increasing demand for clean, reliable and renewable energy is driving society
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10 towards distributed generation (DG) systems. DG technology is of apprehension
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12 due to supplying the loads in remote and rural places [1, 2, 3], where application of
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14 this technology can reduce the necessity to build new transmission lines. In addi-
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16 tion, application of DG resources based on renewable energy such as solar and wind
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18 leads to decrease the carbon emission and emission of other air pollutants arisen
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20 from the conventional coal fired power plants. Generally, power electronic devices
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22 are extensively used for the power regulation of DG sources and injection to the
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24 grid. Application of these devices organizes an opportunity to control different as-
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26 pects of the system such as active and reactive power shared between the grid and
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28 DG link, creating the sinusoidal voltage at the point of common coupling (PCC),
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and increase the power quality indices of the utility grid.
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The DG concept emerged as a way to integrate different power plants, increasing
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the DG owners security and reliability, and providing additional power quality ben-
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37 efits of the power grid. As a consequence, the control of the DG unit should be
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39 enhanced to meet the requirements for the power grid. Therefore, the design of a
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41 control technique, which considers different objectives in the power grid, becomes an
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43 issue of high attention in DG technology. In [4], a multi-task control strategy based
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45 on conservative power theory had presented. This methodology allows voltage level
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47 regulation. In [5], the mechanism of harmonic current injection from single-phase
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49 grid-connected converter is comprehensively investigated. The measurable impacts
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51 from grid voltage, converter commutation, power factor, PWM modulation and
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53 control strategy are demonstrated on the harmonic current injection. Direct power
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3 Modified Synchronous Vector control Design of Multilevel Inverters for AC Grid Applications
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5 control of a Pulse width modulation rectifier using space vector modulation under
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7 unbalanced grid voltages was presented in [6]. in this control algorithm Compared
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to the conventional DPC-SVM, the control structure remains unchanged except
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the original pq theory is replaced by an extended pq theory.In [7], a simple digital
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current control strategy is developed for single phase grid connected converters to
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16 enhance (Grid Connected Converter) GCC performance, which has adopted simple
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18 proportional controller in its structure and can be directly implemented on avail-
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20 able DSP processors. In [8], an improved control strategy for the three phase grid
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22 connected inverter is presented with enhanced dynamic behavior by considering de-
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24 coupling changes. A three-phase active harmonic current compensation to enhance
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26 power quality in the distribution system besides of non-linear loads is presented in
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28 [9]. In [10], a deep investigation had done on the model, control and implementation
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30 of multifunction grid-interfaced inverter without LCL-filter, which can provide high
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32 performance active power current and compensates the existent harmonics simul-
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34 taneously in a distributed networks. In [11], author has investigated the suitability
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36 of selective harmonic elimination (SHE) for low loss multi watt grid connected DG
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38 inverter and also presented a new implementation technique for (selective harmonic
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40 elimination) SHE that utilize the third harmonic to spread the switching angle over
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42 90 . This increase the simplicity in implementation and flexibility in PWM wave-
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44 form. The major problems with the existing control strategies are: (1) The reliability
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46 of the DG converter is less due to fixed reference values of the D and q components
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48 to supply power to load. (2) the q-component supplied by the designed inverter is
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limited. If load reactive q-component crosses its maximum limit the DG converter
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input current increases to more than its maximum limit. DG converter may gets
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damaged by this current. (3) The designed rating of DG converter needed to be
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5 very high. This will increase the cost of the inverter and reduces the utilization fac-
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7 tor of the inverter. These problems are addressed in this paper. The contributions
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of this paper include: (a) Determination of the stable region of the proposed DG
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system by using Synchronous Space curve (SSC). (b) Implementation of Dynamic
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Reference Point (DRP) control algorithm. (c) Development of Optimized SVPWM
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16 control strategy in the nested-loop of grid connected configuration.
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18 In this paper, the synchronous reference frame PLL is used, which is the most
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20 widely used linear closed-loop PLL. Under the condition of an ideal three-phase
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22 equilibrium voltage, the frequency, amplitude and phase of the grid voltage can be
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24 detected quickly and accurately by the SRF-PLL [12]. The rest of the paper is or-
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26 ganized into seven sections. Following the introduction, general schematic diagram
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28 of the proposed DG model and modeling of the proposed system is given in Section
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30 2. An OSVPWM technique in Section 3. Synchronous Space Curve (SSC) approach
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32 to represent the area of active and reactive power for the proposed DG model is
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34 discussed in Section 4. Moreover, simulation results are presented to demonstrate
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36 the efficiency and applicability of the developed control strategy in Section 5. Ex-
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38 perimental results are presented in Section 6. Finally, some conclusions are drawn
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40 in Section 7.
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46 2 Modelling of the proposed system

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Fig.1 shows schematic diagram of grid connected DG interface system. To design an
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51 effective plan to control the interface of DG systems to the power grid, a complete
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53 modeling of the proposed DG system is required. Initially state space equations of
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55 the proposed model are derived by applying Kirchhoff Voltage law to (Fig.1) model.
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29 Figure 1. Schematic Diagram of grid connected DG interface system
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31 diIN x
32 LIN + RIN iIN x + VP CCx + Vxo = 0 (1)
dt
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34 where Vxo = 2VDC fx (SxM ), x = a, b, c, No. of switches/leg, M = 1, 2, 3..8.
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andf (SxM ) is the switching function of Five-level cascaded H-Bridge inverter.
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By applying the Kirchhoff Current Law (KCL) to DC side of inverter
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dVDC
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41 CIN xequ = IDCequ f (SxM )iINx (2)

42 dt
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44 Based on equation (2), the equivalent switching state function of interfaced con-
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46 verter can be expressed as,

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48 Sequx = 2fx (SxM ) (3)
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51 Eq. (2) to (3) shows that the value of equivalent voltage depends on the switching
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53 function of the interfaced converter.
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Figure 2. Proposed DRP control algorithm flow Chart

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5 The dynamic equations in matrix form can be expressed as,
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iINa RIN 0 0 iINa fa (SxM ) Vpcca
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d
9 LIN dt iINb
=
0 RIN 0 iINb fb (SxM ) 2VDC
Vpccb
(4)
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11 iINc 0 0 RIN iINc fc (SxM ) Vpccc
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13 In order to evaluate the performance of control strategy, the model in equation (4)
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15 can be transformed to synchronous orthogonal frame rotating at the grid angular
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17 velocity. All AC variables in main frequency become DC value.
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19 By using park transformation matrix, the dynamic equations of model can be trans-
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21 formed to D-q frame as,
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23 d iIN RIN 0 iIND 0 LIN
24 LIN D =
25 dt
iINq 0 RIN iINq LIN 0
26 (5)
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iIND fD (SxM ) VpccD

28
2V
DC

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30 iINq fq (SxM ) Vpccq
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Eq.(5) can be represented in vector form as
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34 LINDq IINDq + RINDq IINDq + Dq IINDq + SeqiDq VDC + JDq = 0 (6)
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RIN 0 iIN 0 LIN
37 , IIN = D , Dq =
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where RINDq = Dq
, Seqi =
Dq
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0 RIN iINq LIN 0
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41 fD (SxM ) VpccD
, JDq =
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43 fq (SxM ) Vpccq
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2.1 Steady state switching function of the proposed DG model

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48 The instantaneous angle of the reference voltage at PCC is obtained by using a
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50 SRF phase locked loop (PLL).The DG system supplied apparent power components
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52 of load is a function of the instantaneous voltage and current components.
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S = V I = Pload + jQload =

(VD + jVq ) ilD ilq (7)
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5 3
6 PLoad = VD ilD + Vq ilq (8)
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QLoad = Vq ilD VD ilq (9)
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11 Taking into consideration of the power balance at the output of the converter,
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13 supplied power from DG converter to grid is obtained by:
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16 PIN = VD iIND + Vq iINq = 3Re (VIN IIN ) (10)
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18 3
QIN = Vq iIND VD iINq = 3Im (VIN IIN ) (11)
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21 Where iIND and iINq are the Dq-current components of the DG converter to control
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23 active and reactive power transfer to the grid. In this regard determination of stable
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25 reference current components (IrefD , Irefq ) are required for effective control.
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28 2.1.1 Calculation of Reference current based on Dynamic Reference Points (DRP)
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30 to Supply Load Power: The proposed current loop controller is designed based on
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32 equation (6). The reference limit values are important in the control procedure.
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34 These reference limit values prevent the output signals of the controller crossing
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36 the tolerable level of the device in the system. In order to increase the reliability of
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38 the DG converter, a Dynamic Reference Point programming strategy is developed.

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40 The basic principle of this strategy is that, within the capacity of DG converter
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42 and linear modulation constraints, the interfacing system should minimize the dif-
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ference between the load reactive power and actual reactive power delivered to the
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load. The first objective of the strategy is to deliver the reactive power required by
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the load within the maximum capacity of DG converter, then the second objective
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51 is to inject as much as possible available active power as given in the flow chart
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53 shown in Fig. 2.
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5 The DRP strategy can be written as follows.
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q
Minimize: |QL QIN | then PIN = 2
SIN Q2L if QL < QIN else
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q
PIN = SIN 2 Q2IN
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The dynamic reference point currents of the proposed DG system can be defined
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as,
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16 iqref = f (iqref max , ilq ), iDref = f (iDref max , ilD )
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18 The resultant reference value of DG control Loop at D-q axis can be obtained as,
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20 KI
IIN = MDq (Kp + ) (12)
21 Dq
S
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where MD = iIND IrefD and Mq = iINq Irefq
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The equivalent switching state function of interfaced converter can be obtained
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from eq. (6)
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29 1
30 SeqiD(ss) = (RIND IIN + IIN JD ) (13)
VDC D q
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32 1
33 Seqiq(ss) = (RINq IIN IIN ) (14)
VDC q D
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37 2.2 Dynamic state function of the proposed DG model
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39 Dynamic abnormality is generated due to the inherent uncertainty of the variable
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41 parameters and any sudden changes of steady conditions. So, the developed control
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43 technique is to compensate uncertainties and to improve the dynamic response of
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the system. The following function is given to determine the dynamic stability of
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the DG model.
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49 1 2 1
50 kL (MD + Mq ) = LIN MD + LIN Mq2 (15)
2 2
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53 This function represents the total energy of complete system in the controlled
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55 region, which can be consumed to maintain system stability. Where the DC input
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1
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5 voltage is assumed to be constant. The function variables are defined as:
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8 MD = iIND IrefD (16)
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11 Mq = iINq Irefq (17)
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13 d dMD dMq
kL (MD + Mq ) = LIN + LIN (18)
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16 In the above equation initial condition is assumed to be zero.
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18 By considering the dynamic function, to generate a stable operation of the system
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20 the switching function of the converter can be defined as,
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SeqiD = SeqD(ss) + SeqD(Ds) (19)
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Seqiq = Seqq(ss) + Seqq(Ds) (20)
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28 From the Eq.(18) the dynamic part of switching state function can be derived as.
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SeqD(ss) = VDC (iinD IrefD ) (21)
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Seqq(ss) = VDC (iinq Irefq ) (22)
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36 Where, andare constant coefficients of a switching state function during dynamic
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38 conditions.
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42 3 OPTIMIZED SVPWM TECHNIQUE
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The space vector pulse with modulation (SVPWM) provides superior harmonics
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capacity, and permits to solve the problem of unbalanced capacitor voltages by
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using the redundant states in the space voltage vector plane. Many methods have
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51 been developed to implement the SVPWM for driving VSI [13, 14, 15, 16, 17]. Gen-
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53 erally, the SVPWM implementation involves Sector identification, switching vector
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55 determination and optimum switching sequence selection for inverter [18, 19]. With
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5 the new optimized technique for the Space Vector Modulation (SSVPWM) tech-
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7 nique the complexity and effort involved in the Space Vector Diagram (SVD) of
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five level CHB inverter is reduced. For Five-level inverter, based on the geometri-
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cal simplification of SVD the proposed method reduces the number of two level
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hexagons to be considered from conventional 36 to 24(18 outer + 6 inner).Fig. 3
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16 show the selection of inner and outer region of five level hexagon.
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Figure 3. Selection of inner and outer hexagons
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40 The presented OSVPWM is relying on the idea of partitioning of a five-
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42 level SVD [Fig. 3] into inner and outer regions. The selectivity of the inner and
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outer regions depends on the magnitude of Vref. If Vref magnitude is less than
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2E (E = VDC ), then the inner region is selected; otherwise, outer region is selected.
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The two-level hexagons within the outer or inner region square measure elite sup-
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51 ported the angle of the first reference voltage. Selecting a particular hexagon in
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53 the outer region depends on angle .
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55 When an outer hexagon is chosen, a brand new reference vectorVref o2 is generated;
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1
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5 which originates from the center of the outer two-level hexagons. The tip of this
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described in Table I.
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When the inner two-level hexagons (IH) are selected, reference vector Vref 5 is
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mapped to the inner two-level hexagon center reference vector Vref i2 . The appro-
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16 priate selection of IH depends on angle 5 and the mapping of all Vref i2 hexagons is
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18 described in Table II.
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20 The dwell time calculation and switching sequence generation for the selected two-
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22 level hexagon can be performed as in the conventional two-level SVPWM technique.
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24 Each two-level hexagon is divided into six sectors [20, 21].
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26 The volt-second-balancing equation for this sector is then given by,
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29 Vref TS = V1 Ta + V2 Tb + V0 T0 (23)
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32 Where TS is the sampling interval; and Ta , Tb , T0 are the respective dwell times for
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34 the vectors V1 , V2 and V0 . The values of Ta , Tb and T0 are given by,
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Ta = TS Ma sin( ) (24)
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45 T0 = TS Ta Tb (26)
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48 where Ma is the modulation index defined as,
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51 Vref
Ma = 3 (27)
52 VDC
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Table 1. MAPPING OF VREF O2 FROM VREF 5
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7 Hexagon VO2 VO2
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9 OHn V5 2.598076211E cos (n 1) 9 V5 2.598076211E sin (n 1) 9
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11 OHn V5 3E cos (n 1) 9 V5 3E sin (n 1) 9
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13 n = 1, 4, 7, 10, 13, 16. n = 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18
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16 Table 2. MAPPING OF VREF I2 FROM VREF 5
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Hexagon VI2 VI2 Hexagon number
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IHn V5 E cos (n 1) 3 V5 E sin (n 1) 3 n = 1.2..6
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24 4 SYNCHRONOUS SPACE CURVE (SSC) FOR DG MODEL
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27 Due to closed loop control, it is expected that the variables of DG reach to their
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29 reference values after the transient time. The steady state analysis of the grid
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31 connected DG model defines an acceptable area for the reference currents of DG

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33 control loop and injected active and reactive power from the DG link to the grid.
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35 Considering that during the steady state condition, voltages at PCC are balanced
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37 and sinusoidal, and injected current from the DG is equal to the reference values
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39 [22].
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RIN IIN
IIN + SeqD VDC + JD = 0 (28)
D D
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43

44 RIN IINq
+ IINq
+ Seqq VDC + Jq = 0 (29)
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47 SeqD IIND
+ Seqq IINq
+ IDC = 0 (30)
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50 Where VeqiD and Veqiq are the state function of interfaced converter in a stable
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52 region then from eq.(28), (29) and (30) we can expressed as,
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54 JD 2 VDC IDC JD 2
(IIN + ) + (IIN )2 = +( ) (31)
55 D
2RIN D
RIN 2RIN
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1
2
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5
q
JD
Eq. (31) represents a circle of radius VDC IDC JD 2
+ ( 2R ) and center( 2R , 0) Each
6 RIN IN IN
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DG model has its own SSC which depends on the different parameters.Fig. 4 shows
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10 the as consumption area for the active and reactive power of two grid connected
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14 As shown in fig. 4, the DG can supply all the active and reactive power components
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16 of load1, which is inside the area of the SSC . But after the connection of load2
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18 to the grid, requested power by the load is more than the maximum capacity of
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20 DG; then, the DG cant supply all the active and reactive power demanded by the
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22 loads. In the other words the DG can only provide the load power available inside
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24 the SSC which is considered as the stable region for the DG operating condition
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26 and is designed based on the maximum capacity of interfacing system.
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I load2q
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( ,0)
44 2RIN
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I load1D I*IND I load2D

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47 V*DCIDC J
( D )2
48 RIN 2RIN
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Figure 4. Synchronous Space curves at different loads
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5 5 SIMULATION RESULTS
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8 Simulation of the fixed reference point and proposed system is carried with MAT-
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10 LAB/SIMULINK to investigate the enhanced performance of designed control al-
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12 gorithm under different loading conditions. The key simulation parameters are de-
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14 tailed in Table 3. First, capability of DG and adaptability of proposed control strat-
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16 egy for management of integrated VSC in providing active, reactive and harmonic
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18 current components under normal and abnormal loading conditions are studied.
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22 Table 3. SIMULATION PARAMETERS
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24 Nominal Grid Voltage(Ph) 110 V
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26 Rated output power of Inverter 3 KW
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28 DC Source Voltage 80 V
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30 Grid frequency 50 Hz
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32 Switching frequency 2 KHz
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53 Figure 5. Grid current, Load current and DG current under different loding con-
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55 ditions
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5 The DC link voltage is assumed constant in this mode in order to evaluate the
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7 adaptability of the proposed control strategy for accurate power tracking. The ca-
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pabilities of control method on reactive power tracking with effective active power
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injection at fundamental frequency are considered. In addition, these results are
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analysed to give Total Harmonic Distortion (THD) of the utility grid current.
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16 Fig. 5. Shows the fixed reference point control algorithm operation with the cur-
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18 rents of Grid, load and DG system at different loading conditions. Where the grid
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20 connected VSC is rated with 4.5 KVA and the Pref of the DG inverter is consid-
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22 ered as 3KW. At the t = 0 sec. to t = 0.1 sec.with the DG connection to the grid
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24 with resistive load of 1 KW and inductive load of 100 VAR are connected at PCC.
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26 In this mode a reverse power flow takes place at grid due to Pref > Pl . Hence
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28 the grid current is in anti-phase with the DG current. At t = 0.1 Sec., the load is
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30 increased to 3 KW and 600 VAR, which is equal to the DG capacity. In this mode,
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32 the grid current becomes zero and all the active and reactive current components
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34 are provided by DG link. At t = 0.2 Sec., the load is further increased to 5 KW
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36 and 1.1 KVAR. Since the load power is greater than the maximum power capacity
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38 Pref of the inverter, the grid also shares positive power to load.
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40 At t = 0.3 Sec., a non-linear load of 6 KW and 600 VAR is connected to the PCC.
On
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42 The harmonic components make grid current highly polluted. The non-linear part
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44 of the load current is supplied by the DG inverter. Therefore grid current becomes
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46 sinusoidal. The grid current is inphase with grid voltage, which indicates an im-
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48 provement in the input power factor. At t=0.4 Sec., entire DG is disconnected,
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so the total power is supplied by the grid only as shown in Fig. 6. Fig. 7 shows
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the waveforms and THD analysis with non-liner load for grid circuit. This shows
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that due to interfacing of DG, THD of the grid current is improved from 22.92% to
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5 2.67%, which is within the permissible limits if IEEE standards. With the fixed ref-
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7 erence point algorithm the reliability of the grid connected VSC is limited, because
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the installed capacity of the DG system is only limited portion of the capacity of
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the VSC. The active power and reactive power capacity supplied by the inverter is
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bounded to lesser part of the inverter capacity, which is not depends upon the load
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16 requirement. which can be defined by the SSC curve.When the load reactive power
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Figure 6. Active and Reactive Powers by considering load changes with fixed
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reference point control
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53 Fig. 8 shows the performance of proposed DRP controlled grid, load and DG
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55 currents at different loading conditions with 4.5 KVA DG inverter capacity. With
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5 the proposed DRP control algorithm the installed capacity of the DG system can
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7 be improved. The active and reactive power supplied by the inverter follows the
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load requirement and the reliability, utilization of the VSC is improved.
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Figure 7. Grid and Load current spectra after connection of nonlinear load to the
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38 With the DRP control algorithm the required capacity and cost of the DG
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40 inverter drastically reduces. The operating point of the DG system always lies in
On
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42 the stable region and DG injecting current is always within the limit. Active and
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reactive power control of the DG system follows the load requirement as shown in
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Fig. 9. It can be observed that the maximum active and reactive power injection
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capacities of the DG system are increased to rated capacity of the inverter with
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51 DRP control algorithm based on load requirement.At t = 0 sec., the reactive power
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53 required by the load is very less therefore there is a maximum injection of active
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55 power to grid. At t = 0.2 sec., the load requires more reactive power therefore
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4
5 the DG inverter compensates total reactive power required by the load up to it
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7 capacity by compromising active power injection. Therefore, the reliability of the
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grid connected inverter increases so that effective power injection takes place to
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load.
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28 Figure 8. Grid current,Load current and DG current under different loding con-
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51 Figure 9. DG current,Active powers and Reactive powers with DRP control algo-
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53 rithm at different loading conditions
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17 Figure 10. Grid and Load current spectra after connection of nonlinear load to
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22 Fig. 10 indicates the improvement of THD of the grid with nonlinear load. The
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24 harmonic components of the load is supplied by the DG inverter. The THD of the
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26 grid current is reduced from 17% to 2.53% which is as per IEEE standards. Fig.
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28 11 shows the PCC voltage, load, grid and DG currents, when phase C of the grid
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30 fails at t = 0.05 sec. From this fig, it is observed that the DG inverter compensates
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32 the failed grid phase voltage and maintains the load currents balanced. Fig. 11
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34 also shows the dynamic stability condition of the DG system with unbalanced grid
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36 conditions. The DG system is observed to be stable in less than two cycles.
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Figure 11. PCC voltage, Load, grid and DG current before and after the failure
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of the one phase
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4
5 6 EXPERIMENTAL RESULTS
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8 A grid interfaced multi-level converter prototype was built and tested in the lab-
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10 oratory as shown in Fig. 12. The proposed DRP control strategy is implemented
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12 with dSPACE 1104 controller and the key parameters of the prototype are detailed
13
14 in Table 4.
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17 Table 4. EXPERIMENTAL PARAMETERS
18
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19 Nominal Grid Voltage(Ph) 110 V
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21 DC Source Voltage 80 V
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Grid frequency 500 VA
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25 DG unit capacity 50 Hz
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27 Load R=110 ohms,L=40 mH

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29 L filter inductance 4 mH
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31 Switching frequency 2 KHz

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40 Five level H-
dSpace R&D
Controller(ds1104)
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Bridge Inverter
41 L-Filter
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44 Sensor Circuit
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Figure 12. Experimental setup
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55 During the experimental process, a constant DC voltage of 80 V supply to five-level
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5 H-Bridge has been considered as a DG source. This assumption makes it attainable
6
7 to evaluate the aptitude of the control strategy to trace the fast change in the active
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and reactive power; independent of each other. Fig. 13(a) shows the performance
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of the SRF PLL operation to track the angle of the reference voltage.
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27 Figure 13. (a)Grid voltage and SRF PLL output angle (b)Grid voltage and In-
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29 verter output phase voltage with OSVPWM
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34 Fig. 13(b) demonstrates the synchronization between the grid phase voltage and
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36 DG inverter phase voltage with OSVPWM. In the proposed control algorithm, the
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38 system frequency is dictated by the grid and the regulation and tracking of DG
39
40 system are examined in the grid connected condition. Prior to the interface of DG
On
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42 system to AC grid, a load with resistance 110 and 40 mH inductor in each phase
43
44
is supplied by the utility grid. The dynamic conditions of the currents are recorded
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with dSPACE control desk next generation tool.
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After the DG link is connected,the DG unit supplies required load reactive power
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51 of 8VAR and injects permissable active power of 499 watts. In case the load limit
52
53 is within the maximum capacity of the DG converter then, total load components
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55 are supplied by DG source only (iload = igrid + iIN ) as shown in Fig. 14.
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17 Figure 14. Grid, Load and DG current before and after DG connection with DRP
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19 control algorithm..
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26 As shown in Fig. 15, before the connection of additional load to grid, DG link
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28 supplies both active reactive components of load current therefore the grid current
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is almost zero. But after the connection of additional load, the total load demand is
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more than the reference DG power. Hence, the excess amount of power is supplied
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by grid.
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52 Figure 15. Grid, Load and DG current before and after DG connection with DRP
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54 control algorithm..
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17 Figure 16. Grid, Load and DG current before and after failure of one of the grid
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19 phase.
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23 The tolerance ability of the proposed interface system under abnormal con-
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25 dition is verified with considering failure of one of the utility phase. Fig. 16 shows
26
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27 that, before the failure of utility phase voltage the load current is partially shared
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29 by the DG and grid. At the failure of one phase condition, the grid supplies the
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31 load partially with only two phases where as failed phase is supplied by the DG
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converter only and keeps the load current balanced.
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48 Figure 17. (a)Grid voltage and grid current (b) THD of Grid Current.
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53 Furthermore, Fig. 17(a) shows after dynamic change the grid voltage and
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55 grid current are in phase and the grid does not require to supply any reactive
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5 components. Fig. 17(b) indicates the effectiveness of the proposed system with an
6
7 improved THD value of the grid current.
8
9
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11 7 CONCLUSION
12
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14 A control strategy based on Dynamic Reference point (DRP) Based control strat-
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16 egy for the five-level cascaded H-bridge inverter was presented to enhance reliability,
17
18 effective utilization and improves the maximum capacities of active, reactive power
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20 injection of grid connected inverter. Proposed control strategy also improves the
21
22 grid interfaced performance, which has adopted typical optimized modulation prin-
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24 ciples, i.e., an optimized space vector pulse modulation with reduced complexity
25
26 for five-level cascaded H-bridge has been implemented. The proposed DG model
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28 can provide the continuous injection of active power in the main frequency, and all
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30 the reactive power and harmonic current components of grid-connected nonlinear
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32 loads, with a fast dynamic response, through the integration of DG resources into
33
34 the power grid. The proposed control strategy can be used for the integration of
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different types of DG resources specially based on renewable energy, as a power
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38
quality enhancement device in a custom power distribution network. The proposed
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40
system can also be an alternative to synchronous condensers and capacitor banks
On
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43 in medium scale industries along with an active power injection.
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45
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47 References
48
49 [1] Luiz Antonio Maccari, Claudio Luiz do Amaral Santini, Humberto penheiro,Recardo
50
51 C.L.F de oliveira,Robust optimal current control for grid connected three-phase
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53 pulse-width modulated converters,IET Power Electronics, Vol. 8, No. 8, May 2015,
54
55 pp. 1490-99.
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5 [2] Ma J, Wang X, Zhang Y, Yang Q, Phadke AG,A novel adaptive current protection
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7 scheme for distribution systems with distributed generation,Int J Electr Power
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9 Energy System, Vol. 43, No. 1,sep. 2012, pp. 146066.
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11 [3] W. Bohrer, M. Carpita, T. Ghiara, L. Puglisi, A flexible control strategy to interface
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13 solar system with privileged load and utility line. Electrotechnical Conference
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15 Proceedings. Integrating Research, Industry and Education in Energy and Com-
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17 munication Engineering,MELECON 89, Mediterranean 11-13, 1989, pp. 2530.
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[4] Fernando pinhabel marafao, Danilo lglesias brandao, Alessandro costabeber,Multi-
rP
19
20 task control for grid tied inverters based on the conservative power theory,IET
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22 Renewable Power Generation, Vol. 9, No. 2,sep. 2014, pp. 154165.
ee
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24 [5] Keliang Zhou1, Zhipeng Qiu2, Neville R. Watson1, Yonghe Liu1, Mechanism and elim-
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26 ination of harmonic current injection from single-phase grid-connected PWM con-
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27
28 verters,IET Power Electron.,Vol. 6, No. 1,Jan. 2013, pp. 88-95.
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30 [6] Yong chang Zhang, Changqi Qu,Direct power control of a pulse width modulation
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32 Rectifier using Space vector modulation Under unbalanced Grid voltages,IEEE
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Transactions on Power Electronics, Vol. 30, No. 10,Aug. 2015, pp. 5892-5901.
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ie
35 [7] Majid Sanatkr-chayjani, Mohammad monfard,Simplified Digital current control strat-

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egy for single phase grid connected converters, IET Power Electronics,Vol. 8,
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39 No. 2, June 2014, pp. 245-54.
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41 [8] Zhilei Yao, Lan xiao, Josep M.Guerrero,Improved Control strategy for the three- phase
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43 Grid-connected inverter,, IET Renewable Power Generation,Vol. 9,No. 6,March 2015,
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45 pp. 587-92.
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47 [9] P.Karuppanan, Kamala Kanta Mahapatra,Active harmonic current compensation to
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enhance power quality,Electrical Power and Energy Systems,Vol. 62,June 2014,
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pp. 144-51.
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52 [10] Zhixiang Zou, Zheng Wang, and Ming Cheng,Modeling, Analysis, and Design of Mul-
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54 tifunction Grid-Interfaced Inverters With Output LCL Filter,IEEE Transactions
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5 on Power Electronics, Vol. 29, No. 7,Aug. 2014, pp. 3830-3839.
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7 [11] Syahrul Ashikin Azmi, Grain Philip Adam, Khaled H. Ahmed, Stephen J. Finney,
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9 and Barry W. Williams, Grid Interfacing of Multimegawatt Photovoltaic Invert-
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11 ers,IEEE Transactions on Power Electronics, Vol. 28, No. 6,June. 2014, pp. 2770-
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13 2784.
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15 [12] G.C. Hsieh and J.C. Hung,Phase-locked loop techniques a survey,IEEE Trans. On
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17 Industrial Electronics,Vol. 43,No. 6,June 1996,pp. 609615.
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[13] Emanuel serban, Helmine Serban, A control strategy for a Distributed power gen-
rP
19
20 eration microgrid application with voltage and current controlled source con-
21
22 verter,IEEE Transactions on Electronics,Vol. 25,No. 12,May 2010pp. 2981-2992.
ee
23
24 [14] Mukhtiar Singh, vinod khadkikar,ambrish Chandra,Rajiv K Varma, Grid Intercon-
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26 nection of Renewable Energy Sources at the Distribution level with power quality
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27
28 improvement features, IEEE Transactions on Power Delivery,Vol. 26,No. 1,Aug.
29
30 2011,pp. 307-315.
ev
31
32 [15] J. Holtz,Pulse-width-modulationA survey,IEEE Trans. Ind. Electron., Vol. 39, No. 5,
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Dec. 1992,pp. 410419.
34
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35 [16] M. M. Renge, H. M. Suryawanshi, Five-level diode clamped inverter to eliminate

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common mode voltage and reduce dv/dt in medium voltage rating induction motor
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39 drives,IEEE Trans. Ind. Electron.,Vol. 23,No. 4,Jul. 2008,pp. 15981607.
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41 [17] V. Blasko,Analysis of a hybrid PWM based on modifiedspace-vector and triangle-

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43 comparison methods, IEEE Trans.Ind.Appl.,Vol. 33,No. 3,May/Jun. 1997 pp. 756
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45 764.
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47 [18] J. H. Seo, C. H. Cho, and D. S. Hyun, A new simplified space-vector PWM Method for
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three-level Inverters,IEEE Trans.Power Electron.,Vol. 16,No. 4,Jul. 2001,pp. 545
49
50
550.
51
52 [19] A. S. A. Mohamed, A. Gopinath, and M. R. Baiju, A simple space vector PWM gen-
53
54 eration scheme for any general n-level inverter,IEEE Trans. Ind. Electron.,Vol. 56,
55
56
57
58
59
60
1
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4
5 No. 5,May 2009, pp. 16491656.
6
7 [20] Amarendra Matsa, Irfan Ahmed, and Madhuri A. Chaudhari, Optimized Space Vec-
8
9 tor Pulse-width ModulationTechnique for a Five-level Cascaded H-Bridge In-
10
11 verter,Journal of power electronics, Vol. 14,No. 5, September 2014, pp. 937945.
12
13 [21] Irfan Ahmed,V.B Borghate, Amarendra Matsa, H. M. Suryawanshi,and Madhuri A.
14
Fo
15 Chaudhari, Simplified Space Vector Modulation Techniques for Multilevel Invert-
16
17 ers, IEEE Trans.Power Electronics, DOI:10.1109/TPEL.2016.2520078.
18
[22] Amarendra Matsa, and Madhuri A. Chaudhari, Synchronous vector control design of
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20 multilevel inverters for AC grid applications, TENCON 2015 - 2015 IEEE Region
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22 10 Conference, Nov 2015, DOI=10.1109/TENCON.2015.7372807.
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24
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26 Acknowledgment
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The authors gratefully acknowledges the MHRD, INDIA for the financial support
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receiving under the T EQIP II scheme,because of which the work reported in
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33 the paper was possible.
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Authors Response to Decision letter for (UEMP-2015-1006)
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6 Modified Synchronous Vector control Design of Multilevel Inverters for AC Grid
7 Applications
8
9
10 We are very excited to have been given the opportunity to revise our manuscript. We have tried
11 our best to improve the quality of the paper, the details of which are given below. We want to
12
13 extend our appreciation for taking the time and effort necessary to provide such insightful
14 guidance.
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17 RESPONSES TO THE EDITORS COMMENTS
18 The authors are required to fully address the reviewers concerns.
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20 Thank you for your advice and support. All the reviewers recommendations have been carefully
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22
addressed.
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In particular, the improvements of the proposed methods over current State-of-Art are not sufficiently
24
25 demonstrated. While both simulation and experimental results are included, the performance of the
26 improved methods should be compared with current SoA approach both in simulation and experiments,
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27 and show the improvements.

28
29 Thank you, as per suggestion proposed DRP method is compared with conventional fixed reference point
30 method in simulation results shown in Fig. 8, 9, 10 and 11. Corresponding proposed method experimental
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31 results are presented in Fig.14, 15, 16 for validity.

32
33
Improvements of proposed DRP control strategy given briefly:
34 Improved dynamic performance of currents under different loading conditions shown in Fig. 8
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35 Improvement of maximum capacities of active (3 KW to 4.3 KW) and reactive powers (3.2
36 KVAR to 4.3 KVAR) of grid connected inverter shown in Fig. 9 compared to fixed reference
37
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38 point algorithm shown in Fig. 6.

39 Improvement of reliability and reduced cost of grid connected inverter based on load requirement.
40 Better THD performance under nonlinear load conditions shown in Fig.10.
On
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44 CLOSING COMMENTS TO THE EDITOR:
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47 Again, we appreciate the opportunity to revise our manuscript for consideration for publication in EPCS.
48 With your suggestions and revisions we hope that the paper now deem it worthy of publication in EPCS.
49 We next detail our responses to each reviewers concerns and comments.
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5 RESPONSES TO THE REVIEWERS COMMENTS
6
7 Thank you for all of your detailed comments and suggestions. We found them quite useful as we
8
9 approached our revision.
10
11 Reviewer: 1
12
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14 The results can be included for non linear load in simulation part.
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16 Authors Response: Thank you. Per your suggestion, we have included modifications in Fig.8, 9 & 10.
17
18
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19 Reviewer: 2
20
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22 1. The texts inside figures can hardly be read.
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24 Authors Response: Thank you, suggested modifications are done in figures.
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26
2. There are some parts that are not necessary. For example, derivation of the circuit equations in dq
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28 domain or the space vector modulation.
29 Authors Response: Thank you, the derivation of Equ. (6) is important to calculate steady state, Dynamic
30 state switching functions and which is also useful to build SSC curve. Optimized space vector is
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implemented with less complexity. We can minimize the content of these parts at final paper formatting.
32
33
34 3. M_d and M_q are not clear, why are there two different M_d and M_q from DRP generator block in
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35 Fig. 1?
36
Authors Response: Thank you.
37
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38 Where =
, =
are current Error signals.
39
40 iIN Dq
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41 M D = iIND irefD
42 M q = iINq irefq
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KI
I * IN Dq = M Dq ( K P + )
46 SeqD( Ds ) = Vdc ( iIND irefD ) S
47 Seqq( Ds ) = Vdc ( iINq irefq ) SeqD( ss ) =
1
( RIN D I * IN D + I * IN q J D )
48 V * DC
49 1
Seqq( ss ) = ( RIN q I * IN q I * IN D )
V * DC
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52 SeqD = SeqD( ss ) + SeqD( Ds )
53 Seqq = Seqq( ss ) + Seqq( Ds )
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1
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3 These error signals are generated due to steady change in the load and also transient change in the load.
4
5 Therefore & signals are used to generate steady state switching and dynamic state switching
6 function as modifications are included in Fig. 2.
7
8 4. In eq. (2) the dc side current of the inverter has been introduced. but the inverter is a 5-level inverter,
9 which has 2 isolated dc sources per phase. Please give an explanation with provision of the inverter
10
11 topology.
12
13 Authors Response: Thank you, There are two currents for five-level CHB. The average current of both is
14 considered as input DC current. Therefore we mentioned that as equivalent DC current (IDC equ) in eq. (2).
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16 5. Please use a unique style for the references.
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18 Authors Response: Thank you, suggested modifications are done in references.
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Reviewer: 3
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25 1. Where is the meaning of optimization in this context? In the section, the choice of the selected vectors
26 depends only on the outer reference when there is no variation in the voltage. If optimization technique is
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27 used then explain with the reference and advantages.

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29
Authors Response:
30
Thank you. The relative comparison of steps to be followed by the processor for the SVM of a
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32 Five - level inverter in the presented technique and existing technique are given below:
33
34 S.No OSVPWM[20] Previously reported SVPWM[18,19]
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35 1 Read values of Va , Vb and Vc . Read values of Va , Vb and Vc .

36 Convert from a - b - c to - plane to generate V and Convert from a - b - c to - plane to
2
37 V . generate V and V .
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38 3 Find magnitude of Vref and angle of Vref Find angle of Vref.

39 4 Is magnitude of Vref greater than or less than 2E. Select three -level hexagon from .
40 Select two -level hexagon from magnitude of Vref and Generate three -level reference vector Vref3 .
On
41 5
angle of Vref based on internal and external region.
42 6 Generate two -level reference vector Vref2 . Find angle 3 of Vref3 .
43 Find angle 2 of Vref2 . Select two -level hexagon from angle 3 of
44 7
Vref3 .
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Generate dwell times Ta, Tb and To and select sector of Generate two -level reference vector Vref2 .
46 8
two -level hexagon Sn .
47 9 Generate seven -segment timings. Find angle 2 of Vref2 .
48 Generate time number Tn Generate dwell times Ta, Tb and To and
49 10
select sector of two -level hexagon Sn .
50 11 Using Tn and Sn, call appropriate look -up table. Generate seven -segment timings.
51 Send look -up table bits at the output ports to be used as Generate time number Tn
52 12
gate pulses for the switching devices.
53 Using Tn and Sn, call appropriate look -up
54 13
table.
55 Send look -up table bits at the output ports
56 14 to be used as gate pulses for the switching
57 devices.
58
59
60
1
2
3
4
5
As can be seen, the proposed technique reduces the number of functions to be performed by the processor
6
7 by two. However, there is considerable saving in the human effort. Using earlier reported techniques, the
8 designer would have to prepare 36 (hexagons) x 6 (sectors) = 216 look-up tables. Whereas in the
9 presented OSVPWM technique, only 24 x 6 = 144 look-up tables. Therefore, there is considerable saving
10
in effort as compared to reported technique. The reduction in look-up tables does lead to appreciable
11
12 reduction in the memory requirements.
13
14 2. Optimized space vector control PWMIs it reported in the literature for five level inverter with two
Fo
15 region operation. How do you claim that it is optimized?. This is not proved and neither it is compared as
16 such in the paper.
17
18 Authors Response:
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19
20 Thank you. Optimized SVPWM is a geometrical simplification method of space vector diagram,
21 which reduces the complexity and memory required for implementation of SVPWM [20,21].
22
ee
23
[20] Amarendra Matsa, Irfan Ahmed, and Madhuri A. Chaudhari, Optimized Space Vector Pulse-width
24
25
Modulation Technique for a Five-level Cascaded H-Bridge Inverter, Journal of power electronics, Vol.
26 14,No.5,September2014,pp.937-945.
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27
28 [21] Irfan Ahmed,V.B Borghate, Amarendra Matsa,H. M. Suryawanshi,and Madhuri A. Chaudhari,
29 Simpli_ed Space Vector Modulation Techniques for Multilevel Inverters, IEEE Trans.Power Electron,
30 DOI:10.1109/TPEL.2016.2520078.
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31
32 3. Fig 1 shows the two times output of MD and Mq . These seems to be same. Also Vxo is not shown.
33
Vpcca,b,c are the same as that of Va,Vb,Vc. (Why more no of variables are indicated).
34
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35
36
Authors Response:
37 Thank you.
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38 (a) Where =

, =
are current Error signals.
39
40
On
iIN Dq
41 M D = iIND irefD
42 M q = iINq irefq
43
44
45
ly
KI
46 SeqD( Ds ) = Vdc ( iIND irefD )
I * IN Dq = M Dq ( K P +
S
)
47 1
Seqq( Ds ) = Vdc ( iINq irefq ) SeqD( ss ) = ( RIN D I * IN D + I * IN q J D )
48 V * DC
49 1
Seqq( ss ) = ( RIN q I * IN q I * IN D )
50 V * DC
51
52 SeqD = SeqD( ss ) + SeqD( Ds )
53 Seqq = Seqq( ss ) + Seqq( Ds )
54
55
56
57
58
59
60
1
2
3 These error signals are generated due to steady change in the load and also transient change in the load.
4
5 Therefore & signals are used to generate steady state switching and dynamic state switching
6 function as modifications are included in Fig. 2.
7
8 (b) Phase voltage of inverter ( V ) = 2V f S ) x = a, b, c and No. of switches/leg n = 1,2,3. .8.
9 Shown in the below fig.
10
11
12
13
14
Fo
15
16
17
18
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19
20 Vxo
21
22
ee
23
24
25
26
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27
28
29
30
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31 (c)Vpcca,b,c are the voltage at the point of common coupling (PCC) terminals and Va,Vb,Vc are the
32 voltages at grid terminals. Modified in Fig.1.
33
34
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35
36 4. Limitations of the standard synchronous vector control are mentioned as it is suggested that the
37 proposed algorithm is going to overcome them. It is very obvious that the improvements in the proposed
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38 should have been highlighted in the performance through the simulation and practical results.
39
40 Authors response:
On
41
42 Thank you, as per suggestion proposed DRP method is compared with conventional fixed reference point
43
44 method in simulation results shown in Fig.8, 9, 10 and 11. Corresponding experimental results are
45 presented in Fig.14, 15, 16 for validity.
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46 Improvements of proposed DRP control strategy given briefly:

47 Improved dynamic performance of currents under different loading conditions shown in Fig.8
48
49 Improvement of maximum capacities of active (3 KW to 4.3 KW) and reactive powers (3.2
50 KVAR to 4.3 KVAR) of grid connected inverter shown in Fig.9 compared to fixed reference
51 point algorithm shown in Fig. 6.
52
Improvement of reliability and reduced cost of grid connected inverter based on load requirement.
53
54 Better THD performance under nonlinear load conditions shown in Fig.10.
55
56 5. Dynamic reference point programming strategy proposed is discrete. The relevance of this is in
57
58 calculation of the q component Ratio factor X=0.1,0.2,.,1. This seems to be normalization and applying
59
60
1
2
3 condition has to be related to the value of demanded Ilq. This merely a selection which referred to the
4
5 limits set in the fig 3. As such there is no limitation of this current by any of the inverter.
6
7 Authors response:
8
9 Thank you. In the Dynamic reference point approach of control algorithm the reference points of inverter
10 reactive and real powers limits are dynamic in nature. However these variations are bounded to maximum
11 limits of DG inverter rating as shown in Fig.2. As per the Fig.3 each designed DG unit having its specific
12
13 SSC circle. The operating point of the DG unit is always lies inside the SSC circle.
14
Fo
15
16 6. Performance demonstrated of this scheme really does not get an idea of the interfaced DG dynamics
17 and the loading pattern. This point is mentioned by the authors in the modelling of the DG ( Refer
18 equation 15) .The DG input is constant. It is doubtful that this may be only considered to be a battery
rP
19
20 instead of the solar panels.
21
ee
23 Thank you. In this control approach dynamic are considered only on load side. In the simulation and
24 Experimental process the DC battery is considered as input.
25
26
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27
28 7. What is Special reference frame?
29
Thank you. Special reference frame is nothing but synchronous reference frame. Modification
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31
32 done as synchronous reference frame.
33
34
ie
35
36
8. Fault testing by one phase is open circuit. Refer figure 7 and 11. In real time situation, it is to be
37 after the (L-G) short circuit fault and then circuit breaker gets open circuit. This action is not addressed
w
38 with the your controller.

39
On
41 Thank you. This is very interesting question. Regarding our experimentation and simulation only open-
42
43 circuit fault is considered. We are continuing our research on all other faulted conditions.
44
45 9. These figure7 & 11 does not really indicate the compensating current by the DG injection. In
ly
46 simulation and hardware it is not matching as simulation and hardware parameters seems to be same.
47
49 Thank you. When one of the grid phase fails, the required load current of particular phase is compensated
50
51 by DG inverter within the limit of inverter. In Fig. 7(Changed to Fig.11) DG current is very high whereas
52 grid current is very small. Therefore we unable find out the change. In Fig. 11 (changed to fig.16) DG
53 current and grid current are almost equal. Therefore we are observing finite change in DG current after
54 fault condition.
55
56 10. Figures does needs more detailing. In Fig 1. The block directions are not shown. Similarly in Fig 3
57 also needs more detailing as each of the curve should be defined.
58
59
60
1
2
3 Authors Response:
4
5 Thank you. As per your suggestions detailed modifications are included in Fig. 1 and Fig. 3.
6
7 11. This limitation of reactive component supply by the inverter has relevance in the cost function also.
8 This overlaps in the effective available real power from the DG (Source) also. These are not taken care
9 although the abstract mentioned the cost effective solution.
10
12
13 Thank you. In the DRP control approach reactive and active reference points are not fixed values.
14 Based on the load reactive power required reference reactive component is fixed. Therefore, we can
Fo
15 achieve more active power limit of inverter when reactive power required by load is less with lesser
16 designed rating of the inverter. This will reduce the cost of the inverter.
17
18
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19
20 12. Value of equivalent voltage depends on the switch -- Which equivalent voltage DC or AC (Vxo).
21
Thank you. V is the AC Phase voltage of inverter = 2V f S ) x = a, b, c and No. of switches/
ee
23
24 leg n = 1,2,3. .8.
25
26
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27
28 13. If DG is supporting the real power. How do you set the DG limit with Id max and Iq max. It seem to
29 be confusing in the figure and in the text. DG is shown as a source in the figure but it is referred as a
30 complete unit with inverter as a DG.
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31
33
Thank you. You raise a very valid point about the terminology. The real power is supported by DG
34
ie
35 source, which related to the control reference term Id max. In other hand DG unit is components of DG
36 source and inverter unit. The reactive power limit is related to the rating of the DG inverter, which related
37 to the control reference term Iq max.
w
38
39
40 ./012 34 56 1789089 :;<) = =.8/> ?3@89 AB??>8CD + .8/F078 ?3@89 AB??>8CD
On
41
42
43 14. IINDq is used for the generating the reference for the reactive power but in equ. 13 & 14 it is not
44 reflecting. Pl clarify.
45
ly
47
48 Thank you. Modifications are included in the manuscript and detailed information is explained as,
49
50 The dynamic reference point currents of proposed DG system can be defined as,
51
52
G = 4HIJ KLM , N )
53
54
O = 4HIJ KLM , N )
55
56 Where HIJ KLM and HIJ KLM are the maximum Dq components limits of DG system.
57
58
59
60
1
2
3 =
, =

4
5
The resultant reference value of DG control Loop at D-q axis can be obtained as,
6
7 ST
8 P GO = :R + )
U
9
10 where K W, K X are propotional and integral gains respectively.
11
12 The equivalent steady state switching functions can be obtained as,
13
[
14 Y
GZZ) = .G P G + ^P O _ )
\
Fo
G]
15
16 [
17 Y
OZZ) = \ .O P O ^P G )
G]
18
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19
20
21 15. What is the DG source considered with its dynamics to derived is not properly presented through
22 the equations 16-17-18.
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23
25
Thank you. The DC link voltage is assumed constant in this mode in order to evaluate the adaptability of
26
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27 the proposed control strategy for accurate power tracking. The dynamics of the eq.(15) is considered
28 based on the various load changes.
29
30
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31 16. Row and sigma shown are to be part of the dynamics (Equ 21-22). What are their values during
32 dynamic condition.
33
34
Authors Response:
ie
35
36 Thank you. The values of = 0.01 and = 0.001. These values are considered by trial and error method
37 based on the transient response of the system.
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38
39
40 17. 1n in the table 1 should be n only (at the bottom).
On
41
43
44 Thank you. As per your suggestions modifications are included in Table. 1.
45
ly
46
47
48
49
50
51 Please consider above revisions,
52
Thanking you,
53
54
55 Corresponding Author: AMARENDRA MATSA
56 amarmeetsyou@gmail.com
57
Ph.no:+91-9492904858.
58
59
60

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Electric Power Components and Systems

Modified Synchronous Vector control Design of Multilevel

Journal: Electric Power Components and Systems

Manuscript Type: Original Article

Date Submitted by the Author: 22-Jan-2016

Complete List of Authors: MATSA, AMARENDRA; VNIT, ELECTRICAL ENGINEERING

cascaded multilevel inverter, space vector pulse width modulation(svpwm),

URL: http://mc.manuscriptcentral.com/uemp Email: dan.m.ionel@gmail.com

31 tions in the conventional synchronous vector control algorithm of grid con-

35 cific advantages, such as increased reliability of the grid interfaced converter,

46 2 Modelling of the proposed system

41 CIN xequ = IDCequ f (SxM )iINx (2)

46 verter can be expressed as,

Figure 2. Proposed DRP control algorithm flow Chart

2.1 Steady state switching function of the proposed DG model

38 the DG converter, a Dynamic Reference Point programming strategy is developed.

31 connected DG model defines an acceptable area for the reference currents of DG

I load1D I*IND I load2D

27 Load R=110 ohms,L=40 mH

31 Switching frequency 2 KHz

35 [7] Majid Sanatkr-chayjani, Mohammad monfard,Simplified Digital current control strat-

35 [16] M. M. Renge, H. M. Suryawanshi, Five-level diode clamped inverter to eliminate

41 [17] V. Blasko,Analysis of a hybrid PWM based on modifiedspace-vector and triangle-

27 and show the improvements.

31 results are presented in Fig.14, 15, 16 for validity.

38 point algorithm shown in Fig. 6.

53 Seqq = Seqq( ss ) + Seqq( Ds )

27 used then explain with the reference and advantages.

35 1 Read values of Va , Vb and Vc . Read values of Va , Vb and Vc .

38 3 Find magnitude of Vref and angle of Vref Find angle of Vref.

38 (a) Where =  

46 Improvements of proposed DRP control strategy given briefly:

38 with the your controller.

S-ar putea să vă placă și

38 (a) Where =