434
2, FEBRUARY 2015
Modeling of Wide-Bandgap Power
Semiconductor DevicesPart II
Enrico Santi, Senior Member, IEEE, Kang Peng, Student Member, IEEE,
Homer Alan Mantooth, Fellow, IEEE, and Jerry L. Hudgins, Fellow, IEEE
(Invited Paper)
Abstract Compact models of wide-bandgap power devices are
necessary to analyze and evaluate their impact on circuit and
system performance. Part I reviewed compact models for silicon
carbide (SiC) power diodes and MOSFETs. Part II completes
the review of SiC devices and covers gallium nitride devices as
well.
Index Terms Gallium nitride (GaN), modeling, power device
modeling, power semiconductor devices, silicon carbide (SiC),
wide-bandgap.
I. I NTRODUCTION
T HIS paper, Part II, presents a survey of recent progress
on silicon carbide (SiC)- and gallium nitride (GaN)-based
power semiconductor devices along with their device models.
The SiC diode and the MOSFET were discussed in Part I of
this paper. An overview of the remaining SiC power device
types is described in Section II, beginning with the JFET.
GaN power devices are presented in Section III. Throughout
this paper, a description of reliability issues associated with
these wide-bandgap devices is provided. Some assertions
regarding outstanding issues and future trends of power device
modeling are provided in Section IV. An additional overview
of the current SiC and GaN devices is given in [1].
II. SiC P OWER D EVICES AND T HEIR M ODELS
A. SiC Power JFET
The SiC JFET is a very promising active device for
high-voltage power switching. It utilizes the p-n junction
depletion layers as a gate control mechanism and avoids
the gate oxide issues existing in an SiC MOSFET. The
JFET does not suffer from MOS native oxide problems
that limit SiC MOSFET performance, such as low
channel mobility, oxide defects, and long-term reliability.
Manuscript received August 12, 2014; revised October 20, 2014 and
November 15, 2014; accepted November 17, 2014. Date of publication
December 23, 2014; date of current version January 20, 2015. This work
was supported by the Office of Naval Research, Arlington, VA, USA,
under Grant N00014-08-1-0080. The review of this paper was arranged by
Editor N. Ohtani.
E. Santi and K. Peng are with the Department of Electrical Engineer-
ing, University of South Carolina, Columbia, SC 29208 USA (e-mail:
pengk@email.sc.edu; santi@engr.sc.edu).
H. A. Mantooth is with the University of Arkansas, Fayetteville, AR 72701
USA (e-mail: mantooth@uark.edu).
J. L. Hudgins is with the Department of Electrical Engineering, University
of Nebraska, Lincoln, NE 68588 USA (e-mail: jhudgins2@unl.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2373373
0018-9383 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO.
Fig. 1. Schematic cross section of (a) vertical JFET with a lateral channel
and (b) vertical trench channel JFET [2].
Siemens, in 1999, proposed the first SiC power JFET that
exhibited good performance. There is no essential structural
difference between normally- OFF and normally-ON JFETs.
Normally-OFF JFETs usually require a narrow and relatively
lightly doped channel to ensure normally-OFF operation,
thus sacrificing the ON-resistance characteristics. However,
normally-ON JFETs pose potential safety problems during
circuit startup or abnormal gate driver operation because the
gate threshold voltage is negative and the device is ON at zero
gatesource voltage condition. One way to solve this problem
is to connect a low-voltage normally-OFF switch device such
as a silicon MOSFET in series with the normally-ON JFET
in a cascode configuration. However, the maximum operating
temperature and switching speed are limited by the silicon
MOSFET.
At the present time, there are two commercially available
SiC high-voltage power JFET structures, i.e., the vertical JFET
with a lateral channel and the vertical JFET with a trench
channel (Fig. 1) [2]. The vertical JFET with a lateral channel
is quite similar to an SiC double implanted MOSFET, with
the gate oxide layer having been replaced by a p-doped region.
This can eliminate the oxide interface with its channel mobility
and reliability problem. This type of SiC JFET also offers
an intrinsic body diode as an antiparallel diode in switching
applications. The drawback of this structure with a lateral
channel is a relatively large specific ON-resistance, due to the
lateral configuration of the channel resulting in large cell pitch.
In contrast, the vertical trench channel JFET has smaller cell
pitch. However, the vertical trench channel JFET has no body
diode, and the Miller capacitance Cgd is very large, due to the
large overlap area between the gate and the drain, making the
gate driver design challenging.
Since SiC JFETs exhibit a very low ON-resistance
characteristic and can operate at high frequency and
SANTI et al.: WIDE-BANDGAP POWER SEMICONDUCTOR DEVICES 435

temperature conditions, several investigations in academia TABLE I

have been performed to evaluate the performance of this new P UBLISHED SiC P OWER JFET M ODELS
emerging power device.
To help power electronics designers understand device
internal mechanisms and predict the performance of a power
device, accurate SiC JFET device models are required. Several
papers have been published on SiC JFET models and are
chronologically listed in Table I.
1) Behavioral Models: Several converters were designed
and tested using JFETS [4], [5]. In [6], power loss in a
three-phase full-bridge inverter using SiC JFETs was estimated
based on the SiC JFET behavioral model. Polynomial func-
tions were implemented to model ON-resistance and switching
power loss based on the experimental data. The impact of
output power, operating temperature, and switching frequency
on inverter efficiency can be evaluated. Fonteneau et al. [7]
used a simple static model with two internal gate diodes,
Dgd and Dgs , and an ON-state drainsource resistance to
investigate device loss under forward and reverse conduction
conditions.
2) Semiphysics Models: To the best of our knowledge, the
Shockley model was the first JFET model ever proposed. The
Shockley model includes two different equations to describe
the drain current in the active region and the saturation region.
A clear boundary condition exists between the two operating
regions. Hao and Pan [8] used the standard Shockley equations
to simulate SiC JFET devices. In [9] and [10], a new model
for vertical JFET with a lateral channel was developed as a
modification of the standard Shockley model. An SiC power
JFET electrothermal model was proposed in [11]. This model
comprised static and dynamic electrical characteristics and a
thermal network to include the self-heating effect. The static
electrical characteristic of the proposed model was described
by the standard Shockley equations. The dynamic thermal
model was an RC Cauer network that can be extracted from
device junction temperature measurement. Another model
based on simple Shockley equations was reported in [12].
This model included the temperature coefficients of threshold
voltage and ON-resistance, to simulate the device behavior at
different temperatures. In [13], the probability distribution of
channel width was incorporated into the Shockley model, due
to the nonuniformity of the channel width during fabrication,
to improve forward characteristic accuracy.
In [14][17], a compact JFET model is proposed that
is partly behavioral and partly physics based. In particular,
temperature-dependent and material-dependent characteristics
are physics based, whereas the ON-state characteristic is
empirical, using a hyperbolic tangent function for the voltage-
controlled channel current. In [18], a different drain current
expression for a 6H-SiC JFET with an implanted gate was
derived based also on the hyperbolic tangent function. To sim-
ulate the transition from the linear to the saturation region,
a saturation voltage parameter was introduced, which was
dependent on the applied gatesource voltage.
The Shockley MOSFET model has also been used to transconductance, threshold voltage, and channel length
model the SiC JFET. In [19], the forward dc characteristic modulation coefficient was approximated by a polynomi-
of a JFET in unipolar operation was expressed by Shockley nal function. Another model with both forward and reverse
MOSFET model equations. The temperature effect on device dc characteristics using MOSFET equations was given in [20].
436 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

The reverse conduction characteristic is important in the TABLE II

freewheeling operation intervals (third-quadrant operation). P UBLISHED SiC P OWER BJT M ODELS
3) Physics-Based Models: A physics-based model for a
4H-SiC power JFET has been proposed [21]. The novel feature
of this model was that it considered the carrier mobility
dependence on both the electric field and the temperature.
Chen et al. [22] proposed a novel SiC JFET model with a
unified description of linear and saturated conduction modes.
This model held the advantages of improved robustness and
convergence, inclusion of the electric-field-dependent mobility,
and more physical understanding of the current saturation
phenomenon. To implement these proposed physics-based
models, a practical parameter extraction procedure for a
vertical power JFET was described in [23].
In [24], a high-temperature SiC JFET inverter was
designed for aircraft. The inverter in this paper was built
using SiC JFETs without any external antiparallel diodes.
In this case, SiC built-in diodes conducted reverse currents.
Therefore, modeling of the built-in diode was required to
simulate power device operation. In [25], a state-space model
of the built-in diode was provided. The model follows a
Fourier-series approach to transform the ambipolar diffusion
partial differential equation into a series of first-order ordinary
differential equations in time.
4) Numerical Models: In [26], an n-channel normally-OFF
bipolar mode field-effect transistor (FET) was modeled and
simulated using SILVACO TCAD 2-D simulation. In [27],
a 6H-SiC JFET numerical simulation was presented, and A large number of SiC BJT applications have been
the influence of a nonuniform channel doping profile was described in the literature. A comparison of experimental
investigated. In [28], the static forward I V curves are performance has been reported between SiC JFET and
simulated as well as simulations of switching waveforms SiC BJT for a 2-kW dc/dc converter in [31]. The results
using two parallel JFETs. showed that SiC BJT switching speed is slightly faster than
SiC JFET under the same circuit conditions, while the driving
loss for SiC BJT is larger. In [32], static and switching
B. SiC Power BJT behavior of a 1200 V 4H-SiC BJT at a bus voltage of 600 V
An SiC power bipolar junction transistor (BJT) has been has been demonstrated. A comparison between an SiC BJT
developed in recent years because of its unique characteristics, and an Si IGBT showed that the total loss in an SiC BJT can
such as low ON-resistance, positive temperature coefficient of be lower than that of an Si IGBT, though the driver loss of
the ON-state resistance, negative temperature coefficient of the an SiC BJT is higher. A 200-A all-SiC power module based
current gain, and normally-OFF nature. The first 6H-SiC BJT on SiC BJTs was reported in [33], and the performance of
was reported in [29]. This device had only a 50 V blocking this module was assessed in a 50-kW dcdc converter for
voltage and a four to eight common-emitter current gain. electric vehicle applications. Compared with a comparably
Luo et al. [30] demonstrated the first 4H-SiC power BJT, sized Si IGBT module, the SiC BJT module could achieve
which had an open base blocking voltage of 800 V and 40% lower power loss, 27% smaller overall weight, and
a common-emitter current gain of nine. Recently reported 10.5-kW/kg power density.
SiC BJTs have a blocking voltage in the range from Although SiC power BJTs have been reported and applied
600 V to 10 kV. Due to the absence of a gate oxide layer, under different operating conditions, few device models have
SiC BJTs can operate at high temperatures. In addition, unlike been proposed for circuit designers. The available SiC power
Si BJTs, SiC BJTs have a large square reverse bias safe BJT models are chronologically listed in Table II.
operating area boundary without second breakdown. However, 1) Semiphysics Models: The GummelPoon model is one
a significant drawback of SiC BJTs is that a continuous base of the earliest models for an Si BJT, proposed by Gummel
current is needed while the device is ON, and this results and Poon in 1970. It has become the standard model for
in complexity of device driver design and significant device simulation of a BJT for the past decades. In [34], the
driving loss. To reduce these shortcomings, the common- GummelPoon model has been used to model a 1.2-kV
emitter current gain (the ratio of collector current to base 4H-SiC BJT. Good agreement has been obtained between
current) is required to be sufficiently high. This issue is a simulation and experiments.
significant obstacle to the adoption of SiC BJTs for a wide 2) Physics-Based Models: A model capturing the depen-
range of applications. dence of the common-emitter current gain on the collector
SANTI et al.: WIDE-BANDGAP POWER SEMICONDUCTOR DEVICES
Fig. 2. Cross-sectional view of a 4H-SiC BJT.
current at different temperatures has been described in [35].
This model considered: 1) recombination in the emitterbase
space charge region; 2) surface recombination; 3) emitter
current crowding; 4) reduction in the emitter-injection Coeffi-
cient under high-level injection conditions; and 5) incomplete
ionization.
3) Seminumerical Models: In [36], a new SiC BJT model
was presented. The novel feature of this model is that the
Fourier-series solution has been used to solve the ambipolar
diffusion equation (ADE) in the device collector region. The
4H-SiC BJT structure is shown in Fig. 2. The voltage drop
in the n-drift region needs to be calculated in the ON state.
The injected excess carrier distribution is determined by the
ADE. In this model, the Fourier-series solution of the excess
carrier distribution was utilized to solve the ADE, a second-
order partial differential diffusion equation.
4) Numerical Models: 2-D device simulations have been
made to investigate SiC BJT behavior at high tempera-
ture [37], [38]. This numerical method provides a good way
to study the physical mechanisms of power semiconductor
devices.
C. SiC Power IGBT
SiC IGBT is seen as a promising candidate for high-voltage
applications (>10 kV) due to its substantial conductivity
modulation. For the past decade, a significant effort has been
invested to fabricate and investigate SiC IGBTs, and several
device structures have been reported. It is expected that an
SiC IGBT can replace an Si gate turn-off thyristor (GTO) in
the future under high-voltage conditions (1030 kV), owing
to its low ON-state voltage drop.
According to the device polarity, an SiC IGBT can be
categorized into two types: 1) p-IGBT and 2) n-IGBT. Both
of them have been demonstrated in [39][42]. In [39], recent
developments in ultrahigh voltage SiC IGBTs are presented.
A 4H-SiC p-IGBT had a high blocking voltage of 15 kV with
an active chip size of 0.16 cm2 , and exhibited a room temper-
ature differential specific ON-state resistance of 24 m cm2
with a gate voltage of 20 V. A 4H-SiC n-IGBT with the same
active chip area had a blocking voltage of 12.5 kV, and a room
temperature differential specific ON-resistance of 24 m cm2
at a gate voltage of 20 V. The first 4H-SiC p-channel IGBT
built on 20-kV blocking epilayer was reported in [40]. Another
12-kV p-channel IGBT was designed, and a differential
ON -resistance of 18.6 m cm2 was achieved with a gate bias
of 16 V [41]. A 4H-SiC n-channel IGBT with a blocking
voltage of 20.7 kV was reported in [42]. This is the highest
reported blocking voltage for an MOS power semiconduc-
tor switch to date. Compared with a p-channel SiC IGBT,
437
Fig. 3. IGBT structure with the equivalent circuit [44].
an n-channel SiC IGBT is more difficult to fabricate, because
of the unavailability of p-type SiC substrates with low
resistivity. Therefore, more investigation has been conducted
on p-IGBTs, though n-IGBTs can switch faster than p-IGBTs
due to a much lower current gain of the backside p-n-p
transistor than that of the backside n-p-n transistor in
a p-IGBT.
Very few models can be found for an SiC IGBT right now,
and significant effort is needed to develop accurate SiC IGBT
models.
1) Physics-Based Models: In [43], a unified physics-based
IGBT model has been developed for both Si and SiC IGBTs.
This is the first p-channel SiC IGBT model, and it is based
on the Hefner IGBT model [44]. The device model was
established according to the device internal structure shown
in Fig. 3. It comprises a MOSFET and a BJT. The MOSFET
provides base current for the BJT. Using the known MOSFET
and BJT characteristics, the device model for IGBT was
created by simplifying physics-based equations with fitting
parameters extracted from data sheets.
2) Numerical Models: The turn-OFF behavior of 4H-SiC
p-channel punch-through IGBTs under inductive loads was
studied by 2-D numerical simulations [45]. The results showed
that the reduction of lifetime in the buffer layer can decrease
turn-OFF switching time, but reducing the buffer layers life-
time will lead to larger ON-state resistance. The tradeoff
between switching loss and conduction loss needs to be made.
A properly optimized buffer layer can result in a significant
decrease in the switching loss, while causing a minimal
increase in the ON-state voltage drop.
D. SiC Power Thyristor
The Si GTO has been widely used for ac power circuits
and motor control until recently. This device is rugged and
capable of handling very high power levels, up to megawatts.
The SiC thyristor achieves improved performance over an
Si thyristor due to the SiC material characteristics, such as high
breakdown electric field and high thermal conductivity. Very
remarkable progress in the development of SiC thyristors has
been made in the past decade. In [46], a 6H-SiC thyristor with
a forward breakdown voltage close to 100 V was presented.
A 700 V asymmetrical 4H-SiC GTO was reported in [47],
and the device forward voltage drop at 350 C was 4.8 V at a
current density of 500 A/cm2 . Ryu et al. [48] demonstrated a
4H-SiC asymmetrical GTO with a blocking voltage of 3100 V
and a forward current of 12 A. In 2007, an 8-kV/64-A super
GTO designed by Temple and fabricated by Cree was used
438
Fig. 4. AlGaN/GaN HEMT structure [53].
in one of the first SiC fault current limiter applications [50].
This is the highest power handling capability reported for an
SiC power device.
1) Physics-Based Models: The lumped charge method was
used to model an SiC p-type super GTO, and ON-state and
switching behaviors were predicted accurately [49]. Tempera-
ture effects were also included in this model.
2) Numerical Models: In [51], the numerical simulation of
4H-SiC GTOs was presented using the 2-D simulator, and the
turn-OFF time and power loss were predicted by 2-D device
simulation.
III. GaN P OWER D EVICES AND T HEIR M ODELS
GaN is seen as one of the most promising wide-bandgap
semiconductor materials for power conversion applications.
GaN-based power devices have better figure of merit than
their Si counterparts. Although GaN-based devices have been
widely used in the photonics field to realize optical devices
such as light-emitting diodes and laser diodes, GaN power
devices are still in the early stage of development [52].
At present, two types of GaN power devices have been
reported: 1) GaN high-electron mobility transistors (HEMTs)
and 2) GaN Schottky diodes. Furthermore, these devices
have made great progress on their characteristics, due to the
improvement of device structures and GaN material quality.
Currently, due to the lack of high- quality GaN substrates,
GaN epilayers are grown on substrates made of foreign
materials, such as Si, SiC, and sapphire. Silicon substrates are
widely used for GaN-based devices, due to their low cost and
mature fabrication techniques, even if the GaN epilayer quality
is poor due to lattice mismatch. This lattice mismatch between
the AlN buffer layer, GaN, and substrate material (Si, SiC, or
sapphire) introduces defects and thus limits operational char-
acteristics and lowers reliability, similar to the defect problems
introduced in the SiC material. However, GaN substrates are
becoming available and should greatly reduce interface states
detrimental to device performance.
A. GaN HEMT
Fig. 4 shows the typical GaN HEMT structure with three
contacts: 1) source; 2) gate; and 3) drain. A thick layer
of undoped GaN is grown on the substrate. On the top of
the undoped GaN layer, an aluminum GaN (AlGaN) layer
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
with high conductivity is built. One of the most distinctive
features of GaN HEMTs is that a 2-D electron gas (2-DEG)
is generated at the interface between the AlGaN and GaN
layers, resulting in very high electron carrier mobility
(12002000 cm2 /V s) and low ON-state resistance [53]. This
2-DEG is due to the conduction band discontinuity between
AlGaN and GaN. This property makes GaN HEMT very
attractive in power conversion applications. Khan et al. [54]
first demonstrated a heterostructure FET based on an
AlGaN/GaN structure. Since then, several GaN heterostructure
transistors have been reported, especially in microwave or
RF areas [55][59]. In the switching power conversion field,
a small number of GaN transistors have also been reported
in the past decades. In [60], an AlGaN/GaN heterostructure
FET was reported. This device exhibited a very low specific
ON -resistance of 6.3 m cm2 and a breakdown voltage of
750 V. Wu et al. [61] demonstrated a 97.8% efficiency GaN
HEMT boost converter with 300-W output power at 1-MHz
switching frequency. This 175350 V hard-switching boost
converter was based on a high-voltage GaN HEMT with
more than 900 V breakdown voltage. Another 120-W boost
converter based on a 940 V/4.4 A GaN HEMT was reported in
[62], and a power efficiency of 94.2% was achieved at 1-MHz
switching frequency. In addition, a 600 V half-bridge module
using two GaN transistors and two SiC Schottky diodes was
constructed in [63]. This module had good reliability after
400 h of high temperature (250 C) testing.
Overall, a continuing problem with these HEMT devices
is that they typically operate in a normally- ON mode.
In addition, conduction current degradation (collapse) due to
electron trap sites created by surface defects and dislocations
is being addressed as progress is made on material quality.
SiN passivation has also been used to help mitigate some
of these effects. Another major disadvantage is that the
GaN HEMT device lacks any avalanche capability. There
is no p-n junction to absorb the avalanche energy. When a
GaN HEMT breaks down from too high of an applied voltage,
it usually punctures through some dielectric layers, which
is an irreversible process. This presents a great challenge
for the power electronics community. Further adoption of
the GaN HEMT may hasten increased use of soft-switching
topologies to reduce the avalanche energy requirement on
the switching devices. Lateral device structures are field
limited, but by incorporating field plates, improvements in
breakdown capability are being achieved [64]. Vertical struc-
tures [65], [66] as well as normally- OFF designs have been
proposed and are under development [67].
Although several GaN transistor devices have been reported,
to the best of our knowledge, only very few device models
have been proposed for GaN HEMTs in the power electronics
area. They are chronologically listed in Table III.
1) Behavioral Models: In [68], a behavioral SPICE model
of GaN HEMT was introduced based on Efficient Power
Conversion Corporation (EPC) device models. Power loss
estimation was made by the SPICE GaN HEMT model for an
acac direct converter. The acac direct converter simulation
results showed that the power loss of GaN transistors was
more than 30% less than that of Si-based devices. In [69],
SANTI et al.: WIDE-BANDGAP POWER SEMICONDUCTOR DEVICES
TABLE III
P UBLISHED GaN P OWER HEMT M ODELS
a behavioral model is developed that includes a GaN HEMT
in cascode with an Si MOSFET. Junction and terminal capac-
itances are modeled along with the external circuit parasitics.
2) Semiphysics-Based Models: The Statz model, originally
developed for short-channel gallium arsenide MESFET, has
been utilized to model both static and switching characteristics
of GaN HEMTs from EPC [70]. In [71], a loss model for the
GaN HEMT is developed based on the measurements from
a calorimeter. The resulting thermal model is expressed as
an RC equivalent circuit coupled to a SPICE electrical model
of the transistor.
3) Physics-Based Models: An analytical model of a
GaN HEMT device has been developed based on an accurate
determination of 2-DEG charge density [72]. For simplicity,
only the first energy level in the potential wall was considered.
Good agreement between model simulation and experi-
ment data was achieved. Another physics-based model for
GaN HEMTs has been presented in [73], which included some
significant factors, such as carrier velocity saturation, channel
439
Fig. 5. Cross-sectional view of lateral GaN Schottky diode.
length modulation, short-channel effect, mobility degradation,
and self-heating issue.
4) Numerical Models: A Sentaurus TCAD model for a
GaN HEMT device has been developed in [74], and the
calculated sheet polarization charge data were used to preset
numerical simulation. Recently, in [75], a device model para-
meter calibration guide was developed for use in TCAD
simulations.
B. GaN Schottky Diode
Significant progress has also been made on high-voltage
lateral GaN Schottky diodes for high-frequency high-power
switching applications. Due to the lack of high-conductivity
GaN substrates, most of the reported GaN Schottky diodes are
based on the lateral structure shown in Fig. 5 [76]. To the best
of our knowledge, no model for this device has been reported
to date.
IV. C ONCLUSION AND D ISCUSSION
A comprehensive review of recent developments in wide-
bandgap semiconductor power devices and their models has
been carried out to show a clear picture of the current
status of this important area of power electronics. SiC- and
GaN-based power devices are a new generation of advanced
power devices, which lead to more efficient power converters
in applications where silicon devices encounter limitations.
Different SiC and GaN power devices and models have been
reviewed in this paper. The classification of power device
models is based on five different levels, and wide-bandgap
semiconductor device models published in the literature have
been classified and briefly reviewed.
Although a large number of power device models are
available for different application conditions, some problems
and limitations still need to be considered.
1) These device models have different levels of complex-
ity, computation speeds, and accuracy. Model selection
should be based on application requirements. The degree
of accuracy and computation speed, which determine the
usefulness of device models for circuit simulation, need
to be specified.
2) Parameter determination is a critical issue for power
device modeling. Some parameters can be extracted
through static I V and CV measurements. However,
for a higher degree of accuracy, the knowledge of device
internal geometry and characteristics is helpful. In this
case, power device manufacturers play a vital role. Their
willingness to share this knowledge is important for
parameter determination. Unfortunately, this information
is generally confidential and unavailable.
440
3) Although simulation convergence is improved in several
power device models, convergence is still an issue,
particularly for more complex models or for larger
system simulations.
4) For SiC MOSFETs and IGBTs, accurate capacitance
modeling must be considered. The capacitances in these
devices exist in a 2-D distribution, at best, and are
thus difficult to reconcile appropriately and accurately
into many models that are 1-D descriptions. However,
1-D mostly lumped approximations are valid for many
types of required simulations used by circuit designers.
Discrepancies in the measured and the simulated
dynamic behavior may result if the capacitive approxi-
mations are too general.
5) Although many SiC JFET models have been proposed
for circuit and device simulations, complete physical
models for all relevant device mechanisms are not
available. As a power device with high blocking volt-
age and high temperature capability, the self-heating
model coupling to the electrical model is significant to
simulate power converters over long operation times.
In addition, the SiC JFET breakdown behavior is impor-
tant for high-voltage applications where it is likely
to happen. SiC JFET short-circuit behavior is impor-
tant to inverter applications. Finally, two internal gate
diodes, Dgd and Dgs , might become active due to gate
driver operation, and modeling of these diodes could be
especially meaningful in bipolar mode.
6) Very few device models for SiC BJT, IGBT, GTO,
and thyristor are available. Much effort is needed to
investigate these SiC bipolar power devices. The Fourier-
series method has been very successful in modeling
Si IGBT [77], [78], and it also has the potential to
simulate SiC IGBT behavior under different operating
conditions.
7) For GaN-based power devices, some physics-based
models use a large number of parameters, which com-
plicates parameter extraction and increases simulation
time. Moreover, model complexity can lead to poor
convergence in simulation. Although some of the models
discussed above have temperature dependencies built
into the device equations, a full electrothermal model
addressing self-heating has not been proposed to date.
8) Material defects can dominate device behavior, particu-
larly over time. This should be strongly considered when
trying to model actual characteristics of the currently
available devices, particularly with devices other than
diodes, where these effects are more significant.
Given these considerations, the authors recommend that a
model repository be created so that the published models
could be contributed for further evaluation and use by the
circuit design community. This model repository will allow
model developers to compare their work against the known
models to quantify improvements. Many device manufacturers
are providing device models on their websites, but often these
do not possess the features a circuit designer might require.
A repository organized by level, as described in Section II,
would be of great value. It may also lay the groundwork
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015
for model standardization efforts as has been achieved in the
low-voltage device community.
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442 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015

[69] X. Huang, Q. Li, Z. Liu, and F. C. Lee, Analytical loss model of Kang Peng received the B.S. degree in electri-
high voltage GaN HEMT in cascode configuration, IEEE Trans. Power cal engineering from Hunan University, Changsha,
Electron., vol. 29, no. 5, pp. 22082219, May 2014. China, in 2008, and the M.S. degree in electri-
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voltage bidirectional GaN transistors using lateral GaN power HEMT, Science and Technology, Wuhan, China, in 2011.
in Proc. 25th Int. Symp. Power Semiconductor Devices ICs (ISPSD), He is currently pursuing the Ph.D. degree with the
May 2013, pp. 213216. University of South Carolina, Columbia, SC, USA.
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of the driver of GaN power transistors through measurement of semiconductor devices modeling and application.
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B. Bakeroot, TCAD methodology for simulation of GaN-HEMT power He joined the faculty of the Department of
devices, in Proc. IEEE 26th Int. Symp. Power Semiconductor Devices Electrical Engineering, University of Arkansas,
ICs (ISPSD), Waikoloa, HI, USA, Jun. 2014, pp. 257260. Fayetteville, AR, USA, in 1998, where he currently
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berlin.com
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Enrico Santi (S90M94SM02) received the
Ph.D. degree from the California Institute of
Technology, Pasadena, CA, USA, in 1994.
He has been with the University of South
Carolina, Columbia, SC, USA, since 1998, where
he is currently an Associate Professor. His current
research interests include modeling and simula-
tion of semiconductor power devices, control of
power electronics systems, and advanced modeling
of power systems.
Jerry L. Hudgins received the Ph.D. degree from
Texas Tech University, Lubbock, TX, USA, in 1985.
He is currently the Chair of the Department
of Electrical Engineering with the University of
NebraskaLincoln, Lincoln, NE, USA. His current
research interests include power electronic device
characterization and modeling, power electronics
design, and renewable energy systems.