Memory interfacing to 8085

Memory interfacing is used to provide more memory space to accommodate complex

programs for more complicated systems. For any microprocessor memory is required to
store program as well as data. Since microprocessor doesnt have on-chip memory, we
need to connect it externally. Types of memories which are most commonly used to
interface with 8085 are RAM, ROM, and EEPROM. 8085 can access 64kB of external
memory.
It can be explained as- total number of address lines in 8085 are 16, therefore it can
access 2^16 = 65535 locations i.e. 64kB.
2^n = number of memory locations, where, n = number of address lines
The following are the steps involved in interfacing memory with 8085 processor.
1. First decide the size of memory requires to be interfaced. Depending on this we
can say how many address lines are required for it. For example if you want to
12
interface 4KB (2 ) memory it requires 12 address lines. Remaining address lines
can be used in address decoding.
2. Depending on the size of memory required and given address range, construct
address decoding circuitry. This address decoding circuitry can be implemented
with NAND gates and/or decoders or using PAL (when board size is a
constraint).
3. Connect data bus of memory to processor data bus.
4. Generate the control signals required for memory using IO/M, WR, RD signals
of 8085 processor.
Memories can be interfaced in two ways
Absolute decoding
All the higher order lines of microprocessor, left after using the required signals for
memory are completely used for generating chip select signal as shown in above
example. This type of decoding is called absolute decoding. Ex: In an interface of 4kB
memory only A0-A11 address lines are utilized, whereas the remaining A12-A15
address lines are used in Memory selection logic or as any other control signals.
Partial decoding
Only some of the address lines of microprocessor left after using the required signals for
memory are used for generating chip select signal. Because of this multiple address
ranges will be formed. If total memory space is not required for the system then, this
type of address decoding can be used. The advantage of this technique is fewer
components are required for memory interfacing because of this board size reduces
and in turn cost reduces. Ex: In an interface of 4kB memory only A0-A11 address lines
are utilized, whereas the remaining A12-A15 address lines are unused.
DMA
DMA stands for "Direct Memory Access" and is a method of transferring data from the
memory to another part of the computer without processing it using the CPU. DMA
generally occurs between an I/O device and memory without the use of the
microprocessor. DMA read transfer data from the memory to I/O device. DMA write
transfer data from the I/O to memory. DMA is an I/O technique commonly used for high-
speed data transfer from one location to another. For e.g: Data transfer between system
memory and a pen drive or other storage device.
The DMA I/O technique provides direct access to the memory while the microprocessor
is temporarily disabled. The DMA controller temporarily borrows the address bus, data
bus and control bus from the microprocessor and transfers the data directly from the
external devices to a series of memory locations (and vice versa).
It uses the following two signals available in 8085 microprocessor
HOLD: DMA sends hold request to 8085 microprocessor requesting the use of address
bus and data bus. When the processor recognizes the hold, it stops its execution and
enters hold cycles. After receiving the HOLD request, microprocessor relinquishes the
buses in the following machine cycle. MPU regains the power of buses after HOLD
goes low.
HLDA: This is an 8085 output signal indicating that MPU is relinquishing control of
buses. DMA controller uses these signals as if it's a peripheral device requesting the
control bus. Once the controller has gained control, it acts as processor for data
transfer. This process is called switching from slave to master mode.
Basic DMA Operations
The direct memory access (DMA) I/O technique provides direct access to the
memory while the microprocessor is temporarily disabled.
A DMA controller temporarily borrows the address bus, data bus, and control bus
from the microprocessor and transfers the data bytes directly between an I/O port
and a series of memory locations.
The DMA transfer is also used to do high-speed memory-to-memory transfers.
Two control signals are used to request and acknowledge a DMA transfer in the
microprocessor-based system.
The HOLD signal is a bus request signal which asks the microprocessor to
release control of the buses after the current bus cycle. The HOLD pin is an input
used to request a DMA action.
The HLDA signal is a bus grant signal which indicates that the microprocessor
has indeed released control of its buses by placing the buses at their high-
impedance states. The HLDA pin is an output that acknowledges the DMA action
The HOLD input has a higher priority than the INTR or NMI interrupt inputs.
DMA Operation Timing Operation

Whenever the HOLD input is placed at a logic 1 level, a DMA action (hold) is requested.
The microprocessor responds, within a few clocks, by suspending the execution of the
program and by placing its address, data, and control bus at their high-impedance
states.
The high-impedance state causes the microprocessor to appear as if it has been
removed from its socket. This state allows external I/O devices or other
microprocessors to gain access to the system buses so that memory can be accessed
directly.
As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle.
Thus, the hold can take effect any time during the operation of any instruction in the
microprocessor's instruction set. As soon as the microprocessor recognizes the hold, it
stops executing software and enters hold cycles.
Note that the HOLD input has a higher priority than the INTR or NMI interrupt inputs.
Interrupts take effect at the end of an instruction, while a HOLD takes effect in the
middle of an instruction.
The only microprocessor pin that has a higher priority than a HOLD is the RESET pin.
Note that the HOLD input may not be active during a RESET or the reset is not
guaranteed.
The HLDA signal becomes active to indicate that the microprocessor has indeed placed
its buses at their high-impedance state, as can be seen in the timing diagram. Note that
there are a few clock cycles between the time that HOLD changes and until HLDA
changes.
The HLDA output is a signal to the external requesting device that the microprocessor
has relinquished control of its memory and I/O space. You could call the HOLD input a
DMA request input and the HLDA output a DMA grant signal.
Types of DMA transfer
DMA transfer block
In this DMA mode, DMA controller is master of memory bus.
This mode is needed by the secondary memory like disk drives, that have data
transmission and are no to be stopped or slowed without any loss of data transfer of
blocks.
Block DMA transfer supports faster I/O data transfer rates but the CPU remains inactive
for relatively long period by tying up the system bus.
Cycle Stealing
In this method, system allows DMA controller to use system bus to transfer one word,
after which it should return back control of bus to CPU. This method reduces maximum
I/O transfer rates. It also reduces interference of DMA controller in CPU memory access
It is completely eliminated by designing DMA interface so that system bus cycles are
stolen only when CPU is not actually using system bus. This is also called as
Transparent DMA.

Data transfer technique directly between memory and I/O device

Steps
1. I/O device asserts DRQ signal.
2. DMA controller sends HOLD signal to CPU
3. CPU sends HLDA back to DMA controller
4. DMA controller give DMA acknowledgment back to I/O.
5. DMA controller places memory address on address bus
6. DMA controller updates memory address register and word counter register
7. When DC register becomes zero, DMA controller sets HOLD=0
8. Data transfer process terminates and processor regain control of system bus.
Advantages of DMA
Quick data transfer because a dedicated piece of hardware transfers data from
one computer location to another and only one or two bus read/write cycles are
required per piece of data transferred.
Processor is not used for holding the data transfer activity and is available for
other processing activity.
Also in systems where the processor primarily operates out of its cache, data
transfer actually occurring in parallel, thus increasing overall system utilization.
Devices that can use DMA are designed for low power consumption, making
them perfect for laptops.
A device that supports DMA supports faster CPUs than those devices without
DMA support.
A DMA-capable device can communicate directly with memory, bypassing the
CPU.

DMA controller 8237 interfacing

8237 is a programmable DMA controller. The 8237 supplies memory & I/O with control
signals and memory address information during the DMA transfer.
It is actually a special-purpose microprocessor whose job is high-speed data transfer
between memory and I/O. 8237 is not a discrete component in modern microprocessor-
based systems. It appears within many system controller chip sets. 8237 is a four-
channel device compatible with 8086/8088, adequate for small systems. 8237 is
capable of DMA transfers at rates up to 1.6MB per second. Each channel is capable of
addressing a full 64K-byte section of memory.
Pin diagram of 8237 (some important pin description)

DREQ3 DREQ0 (DMA request): Used to request a DMA transfer for a particular DMA
channel.
DACK3 DACK0 (DMA channel acknowledge): Acknowledges a channel DMA request
from a device.
HRQ (Hold request): Requests a DMA transfer.
HLDA (Hold acknowledge) signals the 8237 that the microprocessor has relinquished
control of the address, data and control buses.
MEMW (Memory write): Used as an output to cause memory to write data during a DMA
write cycle.
MEMR (Memory read): Used as an output to cause memory to read data during a DMA
read cycle
A3 A0: address pins select an internal register during programming and provide part of
the DMA transfer address during DMA operation.
A7 A4: address pins are outputs that provide part of the DMA transfer address during a
DMA operation.
DB0 DB7: data bus connected to microprocessor and is used during the programming
DMA controller.
Interfacing of 8237 DMA Controller
When the transfer begins, a DMA places the low-order byte on the address bus and the
high-order byte on the data bus and asserts AEN (Address Enable) and ADSTB
(Address Strobe). These two signals are used to latch the high-order byte from the data
bus: thus, it places the 16-bit address on the system bus.
After the transfer of first byte, the latch is updated when the lower bytes generates a
carry (or borrow).
Figure shows two latches: one latch (373 #1) to latch a high-order address from the
data bus by using the AEN and ADSTB signals, and the second latch (373 #2) to
demultiplex the 8085 bus and generate the low-order address bus by using the ALE
(Address Latch Enable from the 8085) signal. The AEN signal is connected to the OE
signal of the second latch to disable the low-order address bus from the 8085 when the
first latch is enabled to latch the high-order byte of address.
Interrupt
Interrupt is signal send by an external device to the processor, to request the processor
to perform a particular task or work. Mainly in the microprocessor based system the
interrupts are used for data transfer between the peripheral and the microprocessor.
The processor will check the interrupts always at the 2nd T-state of last machine cycle.
If there is any interrupt it accept the interrupt and send the INTA (active low) signal to
the peripheral. Interrupts are basically issued on:
Initialization of I/O operation.
Completion of I/O operation.
Occurrence of hardware or software errors
Process of interrupt operation
The I/O unit issues an interrupt signal to the processor. The processor first finishes
execution of the current instruction before responding to the interrupt. The processor
tests for an interrupt then determines that there is one, and it sends an acknowledgment
signal to the device that issued the interrupt. The processor now begins to transfer the
control to the routine which serves the interrupt request from the device. This routine is
called Interrupt service routine. For this process, the CPU needs to save all the
information needed to reassume the current program at the point of interrupt. The
minimum information required is:
the status of the processor, which is contained in the processor status word
(PSW) and
the location of the next instruction to be executed which is contained by the
program counter (PC)
These are all pushed onto the stack.
The processor then loads the program counter with the entry location of the interrupt
service routine. Once the program counter has been loaded, the control is transferred to
the interrupt handler program. The interrupt handler now begins to process the interrupt.
This will include an examination of status information relating to the I/O operation or the
other event that caused an interrupt.
When interrupt processing is complete the saved registers value are retrieved from the
stack and restored to the register. The final function is to restore the PSW and program
counter values from the stack. As a result, the next instruction to be executed will be
from the previously interrupted main program.
Interrupt Service Routine (ISR) A small program or a routine that when executed
services the corresponding interrupting source is called as an ISR.
Types of Interrupt
External interrupts
External interrupts are initiated via the microprocessors interrupt pins by external
devices such I/O devices, timing device, a circuit monitoring the power supply etc
Causes of these interrupts may be I/O device requesting transfer of data, I/O device
finished transfer of data, or power failure. External interrupts can be further divided into
two types:
1. Maskable interrupt
2. Non-Maskable interrupt
Maskable interrupt
An interrupt that can be disabled by writing some instruction is known as Maskable
Interrupt. It can be enabled or disabled by executing instructions such as EI ( enable
interrupts) and DI (Disable interrupt). In 8085, 1-byte instruction EI sets the interrupt
enable flip-flop and enables the interrupt process. 1-byte instruction DI resets the
interrupt enable flip-flop and disables the interrupt process.
Non-maskable interrupt
This type of interrupt cannot be enabled or disabled by instructions. This type of
interrupt has higher priority over the maskable interrupt. This means that if both the
maskable and non-maskable interrupts are activated at the same time, then the
processor will service the non-maskable interrupt first. For e.g. TRAP
Internal Interrupt
Internal interrupt happens from illegal or erroneous use of an instruction or data.
Causes of this interrupt may be: register overflow, attempt to divide by zero, an invalid
operation code, stack overflow etc. These error conditions usually occur as a result of
premature termination of the instruction execution. These are even known as
exceptions.
The difference between internal and external interrupt is that the internal interrupt is
initiated by some exceptional conditions caused by the program itself rather than by
external events. Internal interrupts are synchronous with the program, while external
interrupts are asynchronous. External interrupts depend on external conditions that are
independent of the program being executed at the time.
There are two types of interrupts used in 8085 Microprocessor
1. Hardware Interrupts
2. Software Interrupts
 Software Interrupt
A software interrupts is a particular instructions that can be inserted into the desired
location in the program. There are eight Software interrupts in 8085 Microprocessor.
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
8. RST7
Hardware interrupts
An external device initiates the hardware interrupts and placing an appropriate signal at
the interrupt pin of the processor. If the interrupt is accepted then the processor
executes an interrupt service routine.
The 8085 has five hardware interrupts:
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
The TRAP has the highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR.
TRAP
It is a non-maskable interrupt.
It has the highest priority among the interrupt signal.
It does not need to be enabled and it cannot be disabled.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and
then TRAP is recognized).
TRAP is generally used for such critical events as power failure and emergency
shut off.
RST7.5
It has the second highest priority. It is maskable interrupt. The vector address of this
interrupt is 003CH. It can also be reset or masked by resetting microprocessor.
RST6.5 and RST5.5
These are level triggered (Input goes to high and stay high until it recognized) and
maskable interrupts. RST 6.5 has third highest priority and RST 5.5 has fourth highest
priority. It can be masked by giving DI and SIM instructions or by resetting
microprocessor.
INTR
It is level triggered and maskable interrupt. The following sequence of events occurs
when INTR signal goes high:
1) The 8085 checks the status of INTR signal during execution of each instruction.
2) If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.
3) On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction.

It has the lowest priority.

Interrupt name Maskable Vectored

INTR Yes No

RST 5.5 Yes Yes

RST 6.5 Yes Yes

RST 7.5 Yes Yes

TRAP No Yes

Interrupt priority
In micro-computer a number of I/O device are attached to the processor, with
each device being able to originate an interrupt request.
There is possibility that several sources will request service simultaneously. In
this case, the system must also decide which device to service first.
An interrupt priority is a system that establishes a priority over the various
sources to determine which condition is to be serviced first when two or more
requests arrive simultaneously.
 Device with higher speed transfers such as magnetic disks are given high
priority, and slow devices such as keyboards receive low priority.
When two devices interrupt the processor at the same time, the processor
service the device, with the higher priority first.
There are mainly two ways of servicing multiple interrupts
Polled interrupt
Polled interrupt are handled using software and are therefore slower compared to
vectored interrupt.
In this method, there is one common branch address for all interrupts. The program that
takes care of interrupts begins at the branch address and polls the interrupts sources in
sequence.
The order in which they are tested determines the priority of each interrupt.
The highest priority source is tested first, and if its interrupt signal is on, control
branches to a service routine for this source. Otherwise, the next lower priority source is
tested, and so on.
However, for larger number of devices, the time required to poll each device may
exceed the time to service the device. In such case, the faster mechanism called
chained interrupt is used.
Chained (vectored) interrupt
This is hardware concept of handling the multiple interrupts. In this technique, the
devices are connected in a chain fashion for setting up the priority system.

Hardware Interrupt vs. Software Interrupt

Hardware interrupts are generated by hardware, e.g. a timer, keyboard, network card
etc while software interrupts are triggered by a special software instruction.
Hardware interrupt handlers are supposed to handle hardware events (e.g. a packet
arriving on a network interface) while software handlers are supposed to serve another
piece of software, usually an application, which executed the interrupt instruction (e.g. in
order to request the kernel to access a file on application's behalf).
In 8085, the software interrupt cannot be disabled or masked but the hardware interrupt
except TRAP can be disabled or masked.
SIM and RIM for Interrupts
RIM (Read Interrupt Mask) and SIM (Set Interrupt Mask)
The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
The status of these interrupts can be read by executing RIM instruction.
The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM instruction.
The format of the 8-bit data is shown below.

The status of pending interrupts can be read from accumulator after executing RIM
instruction.
When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown in fig.
SIM Instruction description
D7-D6 - The left two bits are related to the serial interface. When D6 (SDE-Serial Data
Enable) is 1, then whatever is in D7 (SOD-Serial Data Output) is written to the serial
data output (pin 4 of the 8085). If D6=0, nothing is written. This allows a SIM instruction
to be executed altering interrupt masks without affecting serial data.
Bit D5 is not used.
Bit D4 (R 7.5-Reset RST 7.5) This bit allows the SIM instruction to reset the interrupt
pending flag indicated by bit D6 in the RIM instruction layout. The 7.5 interrupt can
indicate that it is pending via the RIM instruction even though it is masked off. This bit
allows that pending request to be reset.
Bit D3 (MSE-Mask Set Enable) is like SDE -- it indicates whether the lower three bits
(D2-D0) are ignored or not. This allows the serial data output to occur without affecting
the interrupt masks.
Bits D2-D0 (RST 7.5 Mask, RST .5 Mask, RST 5.5 Mask) These are the interrupt masks
for the 8085 interrupts 7.5, 6.5, and 5.5. If the corresponding bit is 0, the interrupt is
enabled. If the bit is 1, the interrupt is masked (ignored).
RIM Instruction description
Bit D7 (SID-Serial Input Data) This is the input pin of the serial data interface which is
connected to pin 5 of the 8085.
Bits D6-D4 (I 7.5, I 6.5, I 5.5) These bits indicates that an interrupt is pending for these
three 8085 interrupts 7.5, 6.5, and 5.5.
Bit D3 (IE-Interrupt Enable) This bit indicates whether interrupts are enabled (1) using
the EI (Enable Interrupts) instruction, or disabled (0) using the DI (Disable Interrupts)
instruction.
Bits 2-D0 (M 7.5, M6.5, M5.5) Mask status of interrupts 7.5, 6.5, and 5.5. 1 if masked, 0
if enabled.

Response to Interrupt
1) Interrupt process should be enabled by writing the instruction EI in the main program. It
sets the Interrupt Enable flip-flop.

The instruction DI resets the flip-flop and disables the interrupt response.

2) When the microprocessor is executing a program, it checks the INTR line during the
execution of each instruction.

3) If the line INTR is high and the interrupt is enabled, the microprocessor completes the
current instruction, disables the Interrupt Enable flip-flop and sends a signal called
INTA(bar) Interrupt Acknowledge (active low). The processor cannot accept any
interrupt requests until the interrupt flip-flop is enabled again.
 4) The signal INTA(bar) is used to insert a restart (RST) instruction (or CALL instruction)
through external hardware.

5) When the microprocessor receives an RST instruction (or CALL instruction), it saves the
memory address of the next instruction on the stack. The program is transferred to the
CALL location.

6) Assuming that the task to be performed is written as a subroutine at the specified

location, the processor performs the task. This subroutine is known as a service routine.

7) The service routine should include the instruction EI to enable the interrupt again.

At the end of the subroutine, RET instruction retrieves the memory address where the program
was interrupted and continues the execution.

8259 Block diagram and explanation

Data Bus Buffer (8bit data bus buffer)

The data bus buffer allows the 8085 to send control words to the 8259A and read a
status word from the 8259A.
Read/Write Logic
The RD and WR inputs control the data flow on the data bus when the device is
selected by asserting its chip select (CS) input low.
Control Logic
This block has an input and an output line. If the 8259A is properly enabled, the
interrupt request will cause the 8259A to assert its INT output pin high. If this pin is
connected to the INTR pin of an 8085 and if the 8085 Interrupt Enable (IE) flag is set,
then this high signal will cause the 8085 to respond.
Interrupt Request Register (IRR)
IRR stores all the interrupt inputs that are requesting service. It keeps track of which
interrupt inputs are asking for service.
Interrupt Service Register (ISR)
The Interrupt Service Register (ISR) stores all the levels that are currently being
serviced.
Interrupt Mask Register (IMR)
The IMR is used to disable or enable individual interrupt inputs. Each bit in this register
corresponds to the interrupt input with the same number.
Priority Resolver
The priority resolver determines the priorities of the bits set in the IRR.
Cascade Buffer Comparator
This section generates control signals necessary for cascade operations. 8259
cascaded with other 8259s generates control signals for cascade operation.
CAS_0 - CAS_2
For a master 8259, the CAS_0 - CAS_2pins are output pins, and for slave 8259s, these
are input pins.
SP / EN (bar) (Slave Program /Enable Buffer)
The SP/EN signal is tied high for the master. However it is grounded for the slave.
Operating modes of 8259
Fully nested mode This is a general purpose mode where all IRs are arranged in
highest to lowest. IR0 highest and IR7 lowest.
Automatic Rotation Mode In this mode, a device after being serviced receives the
lowest priority.
Specific Rotation Mode In this mode, User can select any IR for lowest priority
thus fixing all priorities.
Note: 8259 is also called Programmable Interrupt Controller