UNIT-III

5. a) Draw the flow chart and explain the PLD design procedure 6
b) Explain briefly the configurable logic block of an FPGA
(Xilinx XC2000 FPGA or any other series) 6
OR
6. a) Design a BCD to 7 segment code converter using PROM 6
b) Explain the sequence of operations for a system to scan for
the key clouser in a 8x8 matrix key pad 6
UNIT-IV
7 a) Draw an SM chart to design a binary multiplier controller
and realize the control unit using D flip flops, Decoder
and MUXs 6
b) What are the basic blocks of SM chart? Explain 6
OR
8. a) Design a digital system which counts number of Os in a
register R1 and stores the result in a Register R2 . Draw a
SM chart to design the above circuit using RTL description 6
b) Write a brief note on Linked state machines 6
UNIT-V
9. a) What are the contents of the look up tables implementing a
4 to 1 MUX 6
b) What are carry chains in FPGA? How do they improve the
speed of addition? 6
OR
10. a) Draw a simplified view of Xilinx spaitan configurable
logic bloc 4
b) Explain how synthesis is carried out by a syntherizee
for a case statement 4
c) How many logic blocks are required to create a 4 to 16
decode 4

[4,12/I S/210]
 [EPRDS-101A/EPRVD-103A]
M.Tech. DEGREE EXAMINATION
DSSP & VLSI Design
I SEMESTER
DIGITAL LOGIC DESIGN
(Effective from the admitted batch 200910)
Time: 3 Hours Max.Marks: 60
--------------------------------------------------------------------------------------- -------------
Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- ------------
UNIT-I
1. a) Minimize the following expression by using K-map
f ( A, B, C , D, E ) (3,6,9,12,18,21,27,30,31) 6
b) Design a one input, one output serial 2s complementer.
The circuit accepts a string of bits from the input and
generates the 2s complement at the output 6
OR
2. a) Design a finite state machine to detect certain sequences as:
1011, 1010, 1000. The output Z is 1 when the above sequences
are detected. Implement the design using JK flipflops 6
b) Write a brief note on state equivalence and state reduction 6
UNIT-II
3. a) Explain briefly about the design units of a VHDL program with
an example each 6
b) Write a VHDL code to model a negative edge triggered JK
Master slave flip flop. Use behavioral model 6
OR
4. a) What are the different data types supported by VHDL? What
is a sub-type? How is it declared and used in a program?
Explain with an example each 6
b) Write a VHDL code to design a 4 bit ripple counter using T
flip flops in a structural modeling style 6
 UNIT-III
5. a) Draw the flow chart and explain the PLD design procedure 6
b) Explain briefly the configurable logic block of an FPGA
(Xilinx XC2000 FPGA or any other series) 6
OR
6. a) Design a BCD to 7 segment code converter using PROM 6
b) Explain the sequence of operations for a system to scan for
the key clouser in a 8x8 matrix key pad 6
UNIT-IV
7 a) Draw an SM chart to design a binary multiplier controller
and realize the control unit using D flip flops, Decoder
and MUXs 6
b) What are the basic blocks of SM chart? Explain 6
OR
8. a) Design a digital system which counts number of Os in a
register R1 and stores the result in a Register R2 . Draw a
SM chart to design the above circuit using RTL description 6
b) Write a brief note on Linked state machines 6
UNIT-V
9. a) What are the contents of the look up tables implementing a
4 to 1 MUX 6
b) What are carry chains in FPGA? How do they improve the
speed of addition? 6
OR
10. a) Draw a simplified view of Xilinx spaitan configurable
logic bloc 4
b) Explain how synthesis is carried out by a syntherizee
for a case statement 4
c) How many logic blocks are required to create a 4 to 16
decode 4

[4,12/I S/210]
 [EPRDS-101A/EPRVD-103A]
M.Tech. DEGREE EXAMINATION
DSSP & VLSI Design
I SEMESTER
DIGITAL LOGIC DESIGN
(Effective from the admitted batch 200910)
Time: 3 Hours Max.Marks: 60
--------------------------------------------------------------------------------------- -------------
Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- ------------
UNIT-I
1. a) Minimize the following expression by using K-map
f ( A, B, C , D, E ) (3,6,9,12,18,21,27,30,31) 6
b) Design a one input, one output serial 2s complementer.
The circuit accepts a string of bits from the input and
generates the 2s complement at the output 6
OR
2. a) Design a finite state machine to detect certain sequences as:
1011, 1010, 1000. The output Z is 1 when the above sequences
are detected. Implement the design using JK flipflops 6
b) Write a brief note on state equivalence and state reduction 6
UNIT-II
3. a) Explain briefly about the design units of a VHDL program with
an example each 6
b) Write a VHDL code to model a negative edge triggered JK
Master slave flip flop. Use behavioral model 6
OR
4. a) What are the different data types supported by VHDL? What
is a sub-type? How is it declared and used in a program?
Explain with an example each 6
b) Write a VHDL code to design a 4 bit ripple counter using T
flip flops in a structural modeling style 6