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8. For the common gate circuit shown in the following fig.4 calculate
the transfer function and the input impedance, Zin, explain why
Zin becomes independent of CL as it increases. 12
UNIT-V
9. a) Describe Op-amp design parameters providing why and where
each of them become important. 6
b) Explain the stability considerations in op-amps. 6
OR
10. a) Bring out a detailed comparison of various performance aspects
of op-amp topologies. 6
b) Explain the slewing characteristics in two stage op-amps. 6
[12/IS/209]
[EPRVD 104]
M.Tech. DEGREE EXAMINATION
VLSI Design
I SEMESTER
ANALOG IC DESIGN
(Effective from the DSSP admitted batch 200910)
OR
4. a) Derive the small signal voltage gain of CS stage with Diode
connected load configuration. 6
b) What is the importance of cascade amplifier? Obtain the
expression for voltage gain and output impedance. 6
UNIT-III
5. a) Quantify the behavior of a MOS differential pair as a function
of the input differential voltage and arrive at an expression with
large signal analysis. 6
b) For the basic differential transistor pairs with MOS and
current source loads, calculate the differential voltage gain if
Iss = 1 ma, (W/L)1,2 = 50/0.5 and (W/L)3,4 = 50/1. What is the
minimum allowable input CM level if Iss required atleast 0.4v
across it? Using this value for VinCM. Calculate the maximum
output voltage swing in each case. 6
OR
6. a) For the following circuit of fig.2
Assume (W/L)1.2 = 25/0.5, nCox = 50 A/V2, VTH = 0.6V,
= = 0, and VDD = 3V.
i) What is the required input CM for which RSS sustains
0.5 v?
ii) Calculate RD for a differential gain of 5.
iii) What happens at the output if the input CM level is 50 mV
higher than the value calculated in (a)? 6
b) Give the analysis of small signal behavior of basic current
mirror and bring out the importance of active and cascade
current mirrors. 6
UNIT-IV
7. a) Calculate the transfer characteristics and output impedance of
the following circuit shown in Fig.3. 6