OR

8. a) Explain the design Techniques to Reduce Switching Activity

in CMOS circuits. 6
b) Compute the switching power consumed by the multiplexer of
Figure-4 assuming that all significant capacitances have been
lumped into the three capacitors shown in the fiture, where
C = 0.3 pF. Assume that VDD = 2.5 V and independent,
identically-distributed uniform white noise inputs, with events
occurring at a frequency of 100 MHz. Perform this calculation
for the following: i) A static, fully complementary CMOS
implementation ii) A dynamic CMOS implementation. 6
 [EPRVD 102/EPRDS 102]
M.Tech. DEGREE EXAMINATION
VLSI/ DSSP
I SEMESTER
DIGITAL IC DESIGN
(Effective from the VLSI admitted batch 200809 onwards)
(Effective from the DSSP admitted batch 200910)

Time: 3 Hours Max.Marks: 60

-----------------------------------------------------------------------------------
Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
-----------------------------------------------------------------------------------
UNIT-I
1. a) What are the various issues in the Digital Integrated circuit
design. Illustrate with suitable example. 6
b) Explain the concept of regenerative property of a CMOS
Inverter. 6
OR
2. a) Give a graphical overview of different operations involved in
a typical photolithographic process. 6
b) Explain quality metrics of digital design. 6
UNIT-II
3. a) Illustrate the possible impact of process variations on the
performance of an MOS device? 6
b) What are the parasitic elements that have an impact on the
electrical behavior of the circuit and influence its electrical
properties of the interconnect wire. Present some simple
relations and techniques to estimate their values from the
interconnect geometrical models and topologies. 6
OR
4. a) How the reduction in feature size influences the operating
characteristics and properties of the MOS transistor, and
indirectly the critical digital design metrics? 6
 b) An NMOS device is plugged into the test configuration shown
below inFig.1. The input Vin = 2V. The current source draws a
constant current of 50 A. R is a variable resistor that can
assume values between 10 k and 30 k . Transistor M1
experiences short channel effects and has following transistor
parameters: k = 110* 10-6 V/A2, VT = 0.4 and VDSAT = 0.6V.
The transistor has a W/L = 2.5 / 0.25 . For simplicity body
effect and channel length modulation can be neglected,
i.e. = 0, Y = 0.

i) When R = 10 k & 30 k find the operation region,

VD and VS.
ii) For the case of R = 10 k , would VS increase or decrease
if 0. Explain qualitatively. 6
UNIT-III
5. a) Explain the design techniques for maximizing the noise margin. 6
b) Explain the performance of CMOS inverter with necessary
qualitative analysis. 6
OR
6. a) Scaling the technology is an effective means of reducing the
area, propagation delay and power consumption of a gate-
justify with necessary analogy. 6
 b) An NMOS transistor is used to charge a large capacitor, as
shown in Fig.2 6
i) Determine the tpLH of this circuit, assuming an ideal step
from 0 to 2.5V at the input node.
ii) Assume that a resistor RS of 5 k is used to discharge the
capacitance to ground. Determine tpHL.
iii) Determine how much energy is taken from the supply
during the charging of the capacitor. How much of this is
dissipated in M1. How much is dissipated in the pull-down
resistance during discharge? How does this change when
RS is reduced to 1 k . 6

UNIT-IV
7. a) Mention several approaches to reduce delays in large fan-in
circuits. Explain any one in detail. 6
b) Consider the circuit of Fig.3. Assume the inverter switches
ideally at VDD/2, neglect body effect, channel length
modulation and all parasitic capacitance throughout this
problem.
i) What is the logic function performed by this circuit?
ii) Explain why this circuit has non-zero static dissipation.
iii) Using only just 1 transistor, design a fix so that there will
not be any static power dissipation. Explain how you chose
the size of the transistor.
iv) Implement the same circuit using transmission gates. 6
 UNIT-V
9. a) Define setup Time, Hold time and propagation delay of a
synchronous register. 6
b) Prove that C2 MOS register with CLK-CLK clocking is
insensitive to overlap. 6
OR
10. a) Explain an approach to optimize sequential circuits. 6
b) What are the various approaches to implement an edge-
triggered register. Explain briefly. 6

[4,12/IS/209]
 UNIT-V
9. a) Define setup Time, Hold time and propagation delay of a
synchronous register. 6
b) Prove that C2 MOS register with CLK-CLK clocking is
insensitive to overlap. 6
OR
10. a) Explain an approach to optimize sequential circuits. 6
b) What are the various approaches to implement an edge-
triggered register. Explain briefly. 6

[4,12/IS/209]
 UNIT-V
9. a) Define setup Time, Hold time and propagation delay of a
synchronous register. 6
b) Prove that C2 MOS register with CLK-CLK clocking is
insensitive to overlap. 6
OR
10. a) Explain an approach to optimize sequential circuits. 6
b) What are the various approaches to implement an edge-
triggered register. Explain briefly. 6

[4,12/IS/209]
 UNIT-V
9. a) Define setup Time, Hold time and propagation delay of a
synchronous register. 6
b) Prove that C2 MOS register with CLK-CLK clocking is
insensitive to overlap. 6
OR
10. a) Explain an approach to optimize sequential circuits. 6
b) What are the various approaches to implement an edge-
triggered register. Explain briefly. 6

[4,12/IS/209]