[Nov-11]

[EPRVD-102/EPRDS-102A]
M.Tech. Degree Examination
VLSI Design & DSSP
I SEMESTER
DIGITAL IC DESIGN
(Effective for VLSI Design from the admitted batch 2008-09)
(Effective for DSSP from the admitted batch 2009-10)
Time: 3 Hours Max.Marks: 60
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Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
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UNIT-I
1. a) What are the issues connected with the Digital Integrated
Circuit design? 6
b) Distinguish between CMOS and Bi CMOS Technology 6
OR
2. a) In detail explain the CMOS process flow with help of the MOS
structure 6
b) What is meant by photolithography? Discuss in detail 6
UNIT-II
3. a) Draw the V-I characteristics of an nMOS transistor with bias
mode and derive the drain current equation in Linear and
Saturation region 8
b) Define channel length modulation and sub threshold voltage 4
OR
4. a) Draw the MOS transistor structure as a capacitance. How the
capacitance varies with cut off, resistive and saturation region 6
b) What is meant by latch-up? Explain with help of suitable circuit
diagram. How do you minimize the latch-up problem in CMOS
logic design? 6
 UNIT-III OR
5. a) Discuss various important properties of static CMOS logic 8. a) What are the design techniques for large Fan-in? Explain with
design 5 the help of suitable logic circuit 6
b) Draw and explain the static CMOS inverter voltage transfer b) Derive the mathematical expression for VOH and VOL for
characteristics 7 Pseudo nMOS/Ratioed inverter 6
OR UNIT-V
6. a) Give the analytical model for measuring power consumption 9. a) Discuss the behavior of two cross coupled inverter circuits 7
using SPICE 5
b) Design a NOR based CMOS S R latch 5
b) Consider the inverter circuit shown in Fig 1 and ignoring output
impedance, find the inversing threshold voltage. OR
Take n Cox 50 A V 2 and VTHon 0.8 V 7 2
10. a) Explain the operation of C MOS register 6
b) Write short notes on
i) Schmittrigger 2
ii) Monostable Sequential Circuit 2
iii) Pipelining 2

[4,12/I S/211]

UNIT-IV

7. a) Implement F A ( B C ) D using CMOS logic design 4

b) Implement Full adder using Pass Transistor logic and Dynamic
CMOS logic 8