Digital Electronics

an easy approach to learn

 Digital Electronics
an easy approach to learn

Sougata Ghosh
Md. Salim Ahmad
Rakesh Panda

SCITECH PUBLICATIONS (INDIA) PVT. LTD.

CHENNAI
Copyright 2014 Scitech Publications (India) Pvt. Ltd.

SCITECH PUBLICATIONS (INDIA) PVT. LTD.,

Plot No: 52, Door No: 2/619,
Firs Main Road, VGN Nagar,
Iyyappanthangal, Chennai - 600 056.
E-mail: scitech@airtelmail.in
visit us at : www.scitechpublications.com

Regd. Office: 7/3c, Madley Road,

T. Nagar, Chennai - 600 017.

Branches:
Hyderabad: scitech hyd@yahoo.co.in
Kolkata: scitech kol@yahoo.co.in
New Delhi: scitech del@yahoo.co.in

This book or any part thereof may not be reproduced

in any form without the written permission of the
publisher.

Published by V. Ramesh for Scitech Publications (India) Pvt. Ltd., Plot No: 52,
Door No: 2/619, Firs Main Road, VGN Nagar, Iyyappanthangal,
Chennai - 600 056.
 Why This Book???

Back when we were students we were very confused in selecting the digital books
which fulfils all the requirements simultaneously. From those days onwards, it
was our dream to present a book for the students which will remove all the con-
fusions and hone the fundamentals on the subject. Hence we started thinking of
writing a book, congregating all the digital ingredientswhich will help the students
to understand the concepts of DEC in an easier way.

This book is written from the student point of view, the language used is easy, the
concepts are discussed nicely, and is easy to understand. Through this book we
have tried to remove the problems which a general student faces on the subject.

Minutely analysing this subject we found that an average student faces difficulty in
understanding some easy chapters of digital, as for example the chapter, Sequen-
tial Circuits. Every student has a little bit of confusion regarding this chapter
i.e. the confusion in understanding the working of sequential circuits (flip-flop,
latches etc). So, in this book, utmost care has been taken to clarify all these con-
fusions. In addition, the book comprises of some facts along with special concepts
(written separately) in order to increase the general awareness of the readers.

To develop the competitive ability of the students, Brain Teasers are given at the
end of each chapter. Similarly, each chapter also comprises of objective questions,
to test the understanding of the chapter. The last chapter, i.e. Chapter 11 consists
of VHDL codes of various digital circuits.

We hope the 1stedition of this book will certainly rise up to the expectations of
our readers.

January, 2014 Authors

 Contents

Chapter 1 Number Systems 1.1 - 1.33

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
1.2 Number Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2
1.2.1 Binary number system . . . . . . . . . . . . . . . . . . . 1.2
1.2.2 Octal number system . . . . . . . . . . . . . . . . . . . . 1.6
1.2.3 Hexadecimal number system . . . . . . . . . . . . . . . . 1.8
1.3 Complements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.14
1.4 Signed Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . 1.16
1.5 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . 1.18
1.5.1 Binary arithmetic . . . . . . . . . . . . . . . . . . . . . . 1.18
1.5.2 Octal arithmetic . . . . . . . . . . . . . . . . . . . . . . . 1.22
1.5.3 Hexadecimal arithmetic . . . . . . . . . . . . . . . . . . 1.24
1.6 Floating Point Representation . . . . . . . . . . . . . . . . . . . . 1.27
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 1.30

Chapter 2 Codes 2.1 - 2.14

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1
2.2 Classification of Codes . . . . . . . . . . . . . . . . . . . . . . . 2.1
2.3 Non-Binary Code . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.3.1 Morse code . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.4 Binary Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.4.1 Weighted code . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.4.2 Types of BCD representation . . . . . . . . . . . . . . . . 2.3
2.4.3 Non-weighted code . . . . . . . . . . . . . . . . . . . . . 2.4
2.4.4 Parity bit . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6
2.4.5 Error detecting and correcting code . . . . . . . . . . . . 2.7
2.5 Alphanumeric Code . . . . . . . . . . . . . . . . . . . . . . . . . 2.9
2.6 Sequential Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10
 2.7 Self Complementary Code . . . . . . . . . . . . . . . . . . . . . 2.10
2.8 Reflective Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10
2.9 Cyclic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 2.11

Chapter 3 Boolean Algebra and Reduction Techniques 3.1 - 3.39

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1
3.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2
3.3 Basic Operations of Boolean Algebra . . . . . . . . . . . . . . . 3.2
3.4 Reduction of Boolean Expression . . . . . . . . . . . . . . . . . 3.5
3.5 Complement of a Boolean Expression . . . . . . . . . . . . . . . 3.6
3.6 Standard Forms of Boolean Expression . . . . . . . . . . . . . . 3.13
3.6.1 The Sum Of Product form (SOP) . . . . . . . . . . . . . . 3.14
3.6.2 The Product Of Sum form (POS) . . . . . . . . . . . . . . 3.14
3.7 Canonical Form . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14
3.7.1 Standard SOP form . . . . . . . . . . . . . . . . . . . . . 3.14
3.7.2 Standard POS form . . . . . . . . . . . . . . . . . . . . . 3.15
3.8 Boolean Expressions and Truth Table . . . . . . . . . . . . . . . 3.16
3.9 Karnaugh Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18
3.9.1 Rules for constructing a 2-variable K-map . . . . . . . . . 3.19
3.9.2 Rules for constructing a 3-variable K-map . . . . . . . . . 3.19
3.9.3 Rules for constructing a 4-variable K-map . . . . . . . . . 3.20
3.9.4 Mapping of truth table and a standard expression in K-map 3.20
3.10 Dont Care Condition . . . . . . . . . . . . . . . . . . . . . . . 3.30
3.11 Prime Implicants . . . . . . . . . . . . . . . . . . . . . . . . . . 3.31
3.12 Five Variable K-Map . . . . . . . . . . . . . . . . . . . . . . . . 3.33

Chapter 4 Logic Gates 4.1 - 4.57

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
4.2 Types of Logic System . . . . . . . . . . . . . . . . . . . . . . . 4.1
4.3 Not Gate (Inverter) . . . . . . . . . . . . . . . . . . . . . . . . . 4.3
4.4 AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4
 4.5 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5
4.6 NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6
4.7 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7
4.8 XOR Gate (Exclusive-OR) . . . . . . . . . . . . . . . . . . . . . 4.8
4.9 X-NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.10 Buffer Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.11 IC Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14
4.12 Realisation of Boolean Expression using Basic Gates (AND, OR,
NOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16
4.13 Realisation of Logic Function Using Universal Gates . . . . . . . 4.18
4.13.1 Level of gates . . . . . . . . . . . . . . . . . . . . . . . . 4.18
4.13.2 NAND & NOR realisation of basic gates . . . . . . . . . 4.18
4.14 Sensitive and Inhibitive Inputs . . . . . . . . . . . . . . . . . . . 4.28
4.15 Phantom or Wired Logic . . . . . . . . . . . . . . . . . . . . . . 4.29
4.16 Degenerated and Non Degenerated Forms . . . . . . . . . . . . . 4.39
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 4.48

Chapter 5 Combinational Logic Circuit 5.1 - 5.75

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1
5.2 Combinational Logic Circuit . . . . . . . . . . . . . . . . . . . . 5.2
5.3 Arithmetic and Logical Circuits . . . . . . . . . . . . . . . . . . 5.3
5.4 Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3
5.4.1 Half adder . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3
5.4.2 Full adder . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5
5.4.3 Parallel binary adder . . . . . . . . . . . . . . . . . . . . 5.8
5.4.4 Carry look ahead adder (Fast adder) . . . . . . . . . . . . 5.9
5.5 Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11
5.5.1 Half subtractor . . . . . . . . . . . . . . . . . . . . . . . 5.11
5.5.2 Full subtractor (FS) . . . . . . . . . . . . . . . . . . . . . 5.13
5.6 4-Bit Parallel Adder-Subtractor . . . . . . . . . . . . . . . . . . . 5.16
5.7 BCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19
5.8 Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21
 5.9 Binary Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23
5.10 Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . 5.24
5.11 Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . 5.27
5.12 Demultplexer (DEMUX) . . . . . . . . . . . . . . . . . . . . . . 5.43
5.13 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.49
5.14 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.53
5.15 Seven Segment Display . . . . . . . . . . . . . . . . . . . . . . . 5.58
5.16 Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . 5.64
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 5.70

Chapter 6 Introduction 6.1 - 6.66

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1
6.2 Synchronous Sequential Circuit . . . . . . . . . . . . . . . . . . 6.2
6.3 Asynchronous Sequential Circuit . . . . . . . . . . . . . . . . . . 6.2
6.4 Finite State Machine (FSM) . . . . . . . . . . . . . . . . . . . . 6.3
6.4.1 Mealy state machine . . . . . . . . . . . . . . . . . . . . 6.3
6.4.2 Moore state machine . . . . . . . . . . . . . . . . . . . . 6.4
6.5 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5
6.6 S-R Latch (Set-Reset) . . . . . . . . . . . . . . . . . . . . . . . . 6.5
6.6.1 NOR based S - R latch . . . . . . . . . . . . . . . . . . . 6.5
6.6.2 NAND based SR latch . . . . . . . . . . . . . . . . . . . 6.11
6.6.3 Gated SR latch . . . . . . . . . . . . . . . . . . . . . . . 6.17
6.8 Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20
6.9 SR Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22
6.10 D Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26
6.11 JK Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.28
6.12 T Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31
6.13 Applications of Flip Flops . . . . . . . . . . . . . . . . . . . . . 6.34
6.14 Race Around Condition . . . . . . . . . . . . . . . . . . . . . . . 6.35
6.14.1 Minimizing the clock pulse width . . . . . . . . . . . . . 6.36
6.14.2 Using edge triggered clock pulse . . . . . . . . . . . . . . 6.37
6.14.3 Master slave latches . . . . . . . . . . . . . . . . . . . . 6.38
 6.15 Asynchronous Preset and Clear Inputs . . . . . . . . . . . . . . . 6.40
6.16 Realisation of One Flip Flop Using Other Flip Flop . . . . . . . . 6.42
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 6.58

Chapter 7 Counter and Registers 7.1 - 7.57

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1
7.2 Asynchronous (Ripple or Serial) Counter . . . . . . . . . . . . . 7.2
7.3 Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . 7.2
7.3.1 Propagation delay in asynchronous counters . . . . . . . . 7.4
7.3.2 Counter decoder . . . . . . . . . . . . . . . . . . . . . . 7.5
7.3.3 Asynchronous down counter . . . . . . . . . . . . . . . . 7.6
7.3.4 Asynchronous up-down counter . . . . . . . . . . . . . . 7.8
7.3.5 Counter with unused states
(<Mod N counter) . . . . . . . . . . . . . . . . . . . . . 7.9
7.3.6 Procedure to construct any asynchronous counter
(< Mod-N counter) . . . . . . . . . . . . . . . . . . . . . 7.10
7.4 Synchronous Counter (Parallel Counter) . . . . . . . . . . . . . . 7.13
7.4.1 Synchronous binary counters . . . . . . . . . . . . . . . . 7.14
7.4.2 Propagation delay in synchronous (Parallel) counters . . . 7.15
7.4.3 Synchronous (Parallel) counters with ripple carry . . . . . 7.16
7.4.4 Synchronous (Parallel) down counters . . . . . . . . . . . 7.17
7.4.5 Synchronous up/down counters . . . . . . . . . . . . . . 7.18
7.4.6 Synchronous mod counter . . . . . . . . . . . . . . . . . 7.19
7.4.7 Procedure to construct any synchronous counter
(<Mod-N counter) . . . . . . . . . . . . . . . . . . . . . 7.19
7.5 Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.26
7.6 Johnson or Twisted Ring Counter . . . . . . . . . . . . . . . . . . 7.28
7.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30
7.8 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.31
7.8.1 SISO (Serial In Serial Out) shift register . . . . . . . . . . 7.32
7.8.2 SIPO (Serial In Parallel Out) shift register . . . . . . . . . 7.38
7.8.3 PIPO (Parallel In Parallel Out) shift register . . . . . . . . 7.41
 7.8.4 PISO (Parallel In Serial Out) shift registers . . . . . . . . 7.42
7.9 Universal Shift Registers . . . . . . . . . . . . . . . . . . . . . . 7.44
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 7.51

Chapter 8 D/A and A/D Converters 8.1 - 8.31

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1
8.2 Analog v/s Digital . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1
8.3 Digital To Analog Converter (DAC) . . . . . . . . . . . . . . . . 8.3
8.3.1 Weighted resistor type DAC . . . . . . . . . . . . . . . . 8.3
8.3.2 R - 2R Ladder type DAC . . . . . . . . . . . . . . . . . . 8.7
8.3.3 Voltage mode R - 2R ladder type DAC . . . . . . . . . . . 8.10
8.3.4 Inverted /current mode R - 2R ladder type D/A converter . 8.10
8.4 Specifications for DAC . . . . . . . . . . . . . . . . . . . . . . . 8.12
8.4.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . 8.12
8.4.2 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13
8.4.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13
8.4.4 Settling time . . . . . . . . . . . . . . . . . . . . . . . . 8.13
8.4.5 Temperature sensitivity . . . . . . . . . . . . . . . . . . . 8.14
8.4.6 Offset error . . . . . . . . . . . . . . . . . . . . . . . . . 8.14
8.5 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16
8.6 A Direct Conversion ADC/Flash ADC . . . . . . . . . . . . . . . 8.16
8.7 Successive Approximation ADC (SAC) . . . . . . . . . . . . . . 8.21
8.8 Counter Type ADC . . . . . . . . . . . . . . . . . . . . . . . . . 8.22
8.9 Specification of ADC . . . . . . . . . . . . . . . . . . . . . . . . 8.24
8.9.1 ADC voltage resolution . . . . . . . . . . . . . . . . . . 8.24
8.9.2 Signal to quantization noise ratio (SNR) . . . . . . . . . . 8.24
8.9.3 Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.25
8.9.4 Conversion time . . . . . . . . . . . . . . . . . . . . . . 8.25
8.9.5 Input voltage range . . . . . . . . . . . . . . . . . . . . . 8.25
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 8.28
Chapter 9 Logic Family 9.1 - 9.30
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1
9.2 Digital Logic Families . . . . . . . . . . . . . . . . . . . . . . . 9.1
9.3 Specification of Logic Devices . . . . . . . . . . . . . . . . . . . 9.2
9.4 Diode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8
9.5 Resistor Transistor Logic(RTL) . . . . . . . . . . . . . . . . . . . 9.10
9.6 Diode Transistor Logic (DTL) . . . . . . . . . . . . . . . . . . . 9.12
9.7 High Threshold Logic (HTL) . . . . . . . . . . . . . . . . . . . . 9.13
9.8 Transistor-Transistor Logic (TTL) . . . . . . . . . . . . . . . . . 9.13
9.8.1 Totem pole output configuration . . . . . . . . . . . . . . 9.14
9.8.2 Open collector output configuration of TTL logic . . . . . 9.15
9.8.3 Tristate configuration of TTL . . . . . . . . . . . . . . . 9.16
9.9 Emitter Coupled Logic(ECL) . . . . . . . . . . . . . . . . . . . . 9.17
9.10 CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.18
9.10.1 Implementation of logic functions using CMOS logic . . . 9.19
9.11 Comparison of Different Logic Gate Families . . . . . . . . . . . 9.23
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 9.26

Chapter 10 Memory Devices 10.1 - 10.20

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1
10.2 Basics of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2
10.3 Programmable Logic Devices (PLDS) . . . . . . . . . . . . . . . 10.6
10.3.1 PROM (Programmable Read Only Memory) . . . . . . . 10.7
10.3.2 Programmable Array Logic (PAL) . . . . . . . . . . . . . 10.8
10.3.3 Programmable Logic Array (PLA) . . . . . . . . . . . . . 10.9
10.4 CPLD (Complex Programmable Logic Device) . . . . . . . . . . 10.10
10.5 FPGA (Field Programmable Gate Array) . . . . . . . . . . . . . . 10.11
10.6 RAM (Random Access Memory) . . . . . . . . . . . . . . . . . . 10.12
10.6.1 DRAM (Dynamic Random Access Memory) . . . . . . . 10.12
10.6.2 SRAM (Static Random Access Memory) . . . . . . . . . 10.13
10.7 ROM (Read Only Memory) . . . . . . . . . . . . . . . . . . . . . 10.15
10.7.1 Erasable ROM . . . . . . . . . . . . . . . . . . . . . . . 10.15
 10.7.2 EPROM (Erasable Programmable Read Only Memory) . . 10.15
10.7.3 EEPROM (Electrically Erasable Programmable Read Only
Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . 10.15
10.8 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.16
10.9 Magnetic Memory . . . . . . . . . . . . . . . . . . . . . . . . . 10.16
Objective Questions . . . . . . . . . . . . . . . . . . . . . . . . 10.17

Chapter 11 Introduction 11.1 - 11.47

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1
11.2 VHDL Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1
11.3 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2
11.4 Keywords in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 11.5
11.5 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6
11.6 Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10
11.7 Data Objects: Signals, Variables and Constants . . . . . . . . . . 11.10
11.8 Entity Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11
11.9 Dataflow Modelling . . . . . . . . . . . . . . . . . . . . . . . . . 11.13
11.10Behavioural Modelling . . . . . . . . . . . . . . . . . . . . . . . 11.15
11.11Structural Modelling . . . . . . . . . . . . . . . . . . . . . . . . 11.21

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.1 - I.4