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Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description Features
The ACPL-332J is an advanced 2.5 A output current, easy- Under Voltage Lock-Out Protection (UVLO) with
to-use, intelligent gate driver which makes IGBT VCE fault Hysteresis
protection compact, affordable, and easy-to implement. Desaturation Detection
Features such as integrated VCE detection, under
voltage lockout (UVLO), soft IGBT turn-off, isolated Miller Clamping
open collector fault feedback and active Miller clamping Open Collector Isolated fault feedback
provide maximum design flexibility and circuit protec- Soft IGBT Turn-off
tion.
Fault Reset by next LED turn-on (low to high) after
The ACPL-332J contains a AlGaAs LED. The LED is fault mute period
optically coupled to an integrated circuit with a power
Available in SO-16 package
output stage. ACPL-332J is ideally suited for driving
power IGBTs and MOSFETs used in motor control inverter Safety approvals: UL approved, 5000 VRMS for 1
applications. The voltage and current supplied by these minute, CSA approved, IEC/EN/DIN-EN 60747-5-5
optocouplers make them ideally suited for directly approved VIORM = 1414 VPEAK
driving IGBTs with ratings up to 1200 V and 150 A. For
IGBTs with higher ratings, the ACPL-332J can be used to
Specifications
drive a discrete power stage which drives the IGBT gate. 2.5 A maximum peak output current
The ACPL-332J has an insulation voltage of VIORM = 1414 2.0 A minimum peak output current
VPEAK.
250 ns maximum propagation delay over temperature
Block Diagram range
13 100 ns maximum pulse width distortion (PWD)
V CC2
UVLO 50 kV/s minimum common mode rejection (CMR) at
6, 7 D VCM = 1500 V
ANODE R
5, 8 I 11
V OUT ICC(max) < 5 mA maximum supply current
CATHODE V
DESAT
LED1 E 14 Wide VCC operating range: 15 V to 30 V over
R
DESAT
temperature range
9, 12
SHIELD
V EE 1.7 A Miller Clamp. Clamp pin short to VEE if not used
V CLAMP Wide operating temperature range: 40C to 105C
2 10
V CC1
LED2
V CLAMP Applications
3 VE
FAULT 16
Isolated IGBT/Power MOSFET gate drive
AC and brushless DC motor drives
1, 4
VS
SHIELD
15
V LED Industrial inverters and Uninterruptible Power Supply
(UPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.
Pin Description Pin Symbol Description
1 VS Input Ground
1 VS VE 16 2 VCC1 Positive input supply voltage. (3.3 V to 5.5 V)
3 FAULT Fault output. FAULT changes from a high impedance state
2 VCC1 VLED 15 to a logic low output within 5 s of the voltage on the
DESAT pin exceeding an internal reference voltage of 7 V.
3 FAULT DESAT 14 FAULT output is an open collector which allows the FAULT
outputs from all ACPL-332J in a circuit to be connected
together in a wired OR forming a single fault bus for inter-
4 VS VCC2 13 facing directly to the micro-controller.
4 VS Input Ground
5 CATHODE VEE 12
5 CATHODE Cathode
6 ANODE Anode
6 ANODE VOUT 11
7 ANODE Anode
7 ANODE VCLAMP 10 8 CATHODE Cathode
9 VEE Output supply voltage.
8 CATHODE VEE 9 10 VCLAMP Miller clamp
11 VOUT Gate drive voltage output
12 VEE Output supply voltage.
13 VCC2 Positive output supply voltage
14 DESAT Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while the
IGBT is on, FAULT output is changed from a high impedance
state to a logic low state within 5 s.
15 VLED LED anode. This pin must be left unconnected for guaran-
teed data sheet performance. (For optical coupling testing
only)
16 VE Common (IGBT emitter) output supply voltage.
Ordering Information
ACPL-332J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option Surface IEC/EN/DIN EN
Part number RoHS Compliant Package Mount Tape& Reel 60747-5-5 Quantity
ACPL-332J -000E SO-16 X X 45 per tube
-500E X X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-332J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-332J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation #XXX is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use -XXXE.
2
Package Outline Drawings
16-Lead Surface Mount Package
TYPE NUMBER
DATE CODE
AVAGO A XXXX
LEAD-FREE YYWW 7.493 0.254 11.63 (0.458)
EEE (0.295 0.010)
PIN 1 DOT
LOT ID
2.16 (0.085)
1 2 3 4 5 6 7 8
10.312 0.254
(0.406 0.10)
8.763 0.254 ALL LEADS TO
9 (0.345 0.010) BE COPLANAR
0.05 (0.002)
3
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-332J is approved by the following organizations:
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a
detailed description of Method a and Method b partial discharge test profiles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
4
Table 2. Insulation and Safety Related Specifications
Parameter Symbol ACPL-332J Units Conditions
Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output terminals,
(Clearance) shortest distance through air.
Minimum External Tracking L(102) 8.3 mm Measured from input terminals to output terminals,
(Creepage) shortest distance path along body.
Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to conductor,
(Internal Clearance) usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
5
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values at TA = 25C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions. Positive Supply Voltage used.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
FAULT Logic Low VFAULTL 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 5.5V
Output Voltage IFAULT = 1.1 mA, VCC1 = 3.3V
0.1 0.4 V
FAULT Logic High IFAULTH 0.02 0.5 A VFAULT = 5.5 V, VCC1 = 5.5V
Output Current
0.002 0.3 A VFAULT = 3.3 V, VCC1 = 3.3V
High Level IOH -0.5 -1.5 A VO = VCC2 - 4 2, 4, 5
Output Current -2.0 A VO = VCC2 15 21 3
Low Level IOL 0.5 1.5 A VO = VEE + 2.5 3, 5, 5
Output Current 2.0 A VO = VEE + 15 22 3
Low Level Output Current IOLF 90 140 230 mA VOUT - VEE = 14 V 6
During Fault Condition
High Level VOH VCC-2.9 VCC-2.0 V IO = -650 A 4, 6, 7, 8, 9
Output Voltage 23 23
Low Level VOL 0.17 0.5 V IO = 100 mA 5, 7,
Output Voltage 24
Clamp Pin VtClamp 2.0 V
Threshold Voltage
Clamp Low Level ICL 0.35 1.1 A VO = VEE + 2.5 8
Sinking Current
High Level ICC2H 2.5 5 mA IO = 0 mA 9, 10, 9
Supply Current 25,
Low Level ICC2L 2.5 5 mA IO = 0 mA 26
Supply Current
Blanking Capacitor ICHG -0.13 -0.24 -0.33 mA VDESAT = 2 V 11, 27 9, 10
Charging Current
Blanking Capacitor IDSCHG 10 30 mA VDESAT = 7.0 V 28
Discharge Current
DESAT Threshold VDESAT 6 6.5 7.5 V VCC2 -VE >VUVLO- 12 9
UVLO Threshold VUVLO+ 10.5 11.6 12.5 V VO > 5 V 7, 9,
11
VUVLO- 9.2 10.3 11.1 V VO < 5 V 7, 9,
12
UVLO Hysteresis (VUVLO+ 0.4 1.3 V
- VUVLO-)
Threshold Input Current IFLH 2.0 6 mA IO = 0 mA, VO > 5 V
Low to High
Threshold Input Voltage VFHL 0.8 V
High to Low
Input Forward Voltage VF 1.2 1.6 1.95 V IF = 10 mA
Temperature Coefficient DVF/DTA -1.3 mV/C
of Input Forward Voltage
Input Reverse BVR 5 V IR = 10 mA
Breakdown Voltage
Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V
6
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions. Only Positive Supply Voltage used.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time tPLH 100 180 250 ns Rg = 10 W, 1, 13, 13, 15
to High Output Level Cg = 10 nF, 14, 15,
f = 10 kHz, 16, 29
Propagation Delay Time tPHL 100 180 250 ns Duty Cycle = 50%, 1, 13,
to Low Output Level IF = 10 mA, 14, 15,
VCC2 = 30 V 16, 29
Pulse Width Distortion PWD -100 20 100 ns 14, 17
Propagation Delay (tPHL - tPLH) -150 150 ns 17, 16
Difference Between PDD
Any Two Parts or Channels
Rise Time tR 50 ns
Fall Time tF 50 ns
DESAT Sense to tDESAT(90%) 0.15 0.5 s CDESAT = 100pF, Rg = 10 W, 17, 30, 19
90%VO Delay Cg = 10 nF, VCC2 = 30 V 37
DESAT Sense to tDESAT(10%) 2 3 s CDESAT = 100pF, Rg = 10 W, 18, 19,
10% VO Delay Cg = 10 nF, VCC2 = 30 V 20, 30,
37
DESAT Sense to Low Level tDESAT(FAULT) 0.25 0.5 s CDESAT = 100 pF, RF = 2.1 k, 30, 37 18
FAULT Signal Delay CF = Open, Rg = 10 ,
Cg = 10 nF, VCC2 = 30 V
0.8 CDESAT = 100 pF, RF = 2.1 k,
CF = 1 nF, Rg = 10 ,
Cg = 10 nF, VCC2 = 30 V
DESAT Sense to DESAT tDESAT(LOW) 0.25 s CDESAT = 100pF, RF = 2.1 kW, 30, 37 19
Low Propagation Delay Rg = 10 W, Cg = 10 nF,
VCC2 = 30 V
DESAT Input Mute tDESAT(MUTE) 5 s 37 20
RESET to High Level tRESET(FAULT) 0.3 1 2.0 s CDESAT = 100pF, RF = 2.1 kW,
FAULT Signal Delay Rg = 10 W, Cg = 10 nF,
VCC1 = 5.5V, VCC2 = 30 V
0.8 1.5 2.5 s CDESAT = 100pF, RF = 2.1 kW,
Rg = 10 W, Cg = 10 nF,
VCC1 = 3.3V, VCC2 = 30 V
Output High Level Common |CMH| 15 25 kV/s TA = 25C, IF = 10 mA 31, 32, 21
Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V, RF 33, 34
= 2.1 k, CF = 15 pF
50 60 TA = 25C, IF = 10 mA 21, 26
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 k, CF = 1 nF
Output Low Level Common |CML| 15 25 kV/s TA = 25C, VF = 0 V 31, 32, 22
Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V, RF 33, 34
= 2.1 k, CF = 15 pF
50 60 TA = 25C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 k, CF = 1 nF
7
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO 5000 Vrms RH < 50%, t = 1 min., 24, 25
Withstand Voltage TA = 25C
Input-Output Resistance RI-O > 109 W VI-O = 500 V 25
Input-Output Capacitance CI-O 1.3 pF freq=1 MHz
Output IC-to-Pins 9 &10 q09-10 30 C/W TA = 25C
Thermal Resistance
Notes:
1. Derate linearly above 70C free air temperature at a rate of 0.3 mA/C.
2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/C above 90C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 s. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. Derate
linearly from 3.0 A at +25C to 2.5 A at +105C. This compensates for increased IOPEAK due to changes in VOL over temperature.
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 s.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 12.5V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once VO of the ACPL-332J is allowed to go high (VCC2 - VE > VUVLO+), the DESAT detection feature of the ACPL-332J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional
until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant
IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the increasing (i.e. turn-on or positive going direction) of VCC2 - VE
12. This is the decreasing (i.e. turn-off or negative going direction) of VCC2 - VE
13. This load condition approximates the gate load of a 1200 V/150A IGBT.
14. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
15. As measured from IF to VO.
16. The difference between tPHL and tPLH between any two ACPL-332J parts under the same test conditions.
17. As measured from ANODE, CATHODE of LED to VOUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto
Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V).
22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 A
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 34.
8
IF
tr tf
90%
50%
V OUT 10%
tPLH tPHL
3.0 5
IOH - OUTPUT HIGH CURRENT - A
4
2.5
1.5
1 -----V OUT =VEE +15V
___VOUT =VEE +2.5V
1.0 0
-40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105
T A - TEMPERATURE - oC T A - TEMPERATURE - o C
0 0.25
____ I = -650uA
OUT
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V
-0.5 0.2
VOL - OUTPUT LOW VOLTAGE - V
-1 0.15
-1.5 0.1
-2 0.05
-2.5 0
-40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105
o oC
TA - TEMPERATURE - C T A - TEMPERATURE -
9
30 8
_ _ _ _ 105 o C _ _ _ _ 105 o C
7
V OH - HIGH OUTPUT VOLTAGE DROP - V
28 5
4
27 3
2
26
1
25 0
0.0 0.2 0.4 0.6 0.8 1.0 0 0.5 1 1.5 2 2.5
I OH - OUTPUT HIGH CURRENT - A IoL - OUTPUT LOW CURRENT - A
Figure 6. VOH vs. IOH Figure 7. VOL vs. IOL
4 3.50
ICC2H
ICL - CLAMP LOW LEVEN SINKING CURRENT
3.25 ICC2L
3 ICC2 - OUTPUT SUPPLY CURRENT - mA
3.00
2 2.75
2.50
1
2.25
0 2.00
-40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105
TA - TEMPERATURE - oC TA - TEMPERATURE - C o
2.65 -0.20
ICC2H
ICC2L
ICC2 - OUTPUT SUPPLY CURRENT - mA
2.55
ICH - BLANKING CAPACITOR
CHARGING CURRENT - mA
-0.25
2.45
-0.30
2.35
2.25 -0.35
15 20 25 30 -40 -20 0 20 40 60 80 105
VCC2 - OUTPUR SUPPLY VOLTAGE - V TA - TEMPERATURE - oC
Figure 10. ICC2 vs. VCC2 Figure 11. ICHG vs. temperature
10
7.5 300
t PLH
t PHL
VDESAT - DESAT THRESHOLD - V
TP - PROPAGATION DELAY - ns
250
7.0
200
6.5
150
6.0 100
-40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105
TA - TEMPERATURE - C TA - TEMPERATURE - C
Figure 12. DESAT threshold vs. temperature Figure 13. Propagation delay vs. temperature
300 300
t PLH t PLH
t PHL t PHL
TP - PROPAGATION DELAY - ns
250 250
TP - PROPAGATION DELAY - ns
200 200
150 150
100 100
15 20 25 30 0 10 20 30 40 50
Vcc - SUPPLY VOLTAGE - V LOAD RESISTANCE - ohm
Figure 14. Propagation delay vs. supply voltage Figure 15. Propagation delay vs. load resistance
300
t PLH
t PHL
TP - PROPAGATION DELAY - ns
200
100
0
0 10 20 30 40 50
LOAD CAPACITANCE - nF
11
3.0
300 VCC2 = 15V
VCC2 = 30V
2.5
250
200 2.0
150 1.5
100 1.0
-40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105
TA - TEMPERATURE - C TA - TEMPERATURE - C
Figure 17. DESAT sense to 90% VOUT delay vs. temperature Figure 18. DESAT sense to 10% VOUT delay vs. temperature
4.0 0.012
VCC2 = 15V
TDESAT10% - DESAT Sense to 10% Vo Delay - us
2.0
0.004
1.0
0.0 0.000
10 20 30 40 50 0 10 20 30 40 50
LOAD RESISTANCE - ohm LOAD CAPACITANCE - nF
Figure 19. DESAT sense to 10% VOUT delay vs. load resistance Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance
12
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
15V Pulsed
5 CATHODE VEE 12 +_
IOUT
6 ANODE VOUT 11 30V
0.1F
+_
7 ANODE VCLAMP 10
10mA
8 CATHODE VEE 9
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
15V Pulsed
5 CATHODE VEE 12
IOUT
6 ANODE VOUT 11 30V
0.1F
+_
7 ANODE VCLAMP 10 +_
8 CATHODE VEE 9
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
0.1F
+_
7 ANODE VCLAMP 10
10mA 650A
8 CATHODE VEE 9
13
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
100mA
5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
0.1F
+_
7 ANODE VCLAMP 10
8 CATHODE VEE 9
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
ICC2
5 CATHODE VEE 12
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
I CC2
5 CATHODE VEE 12
8 CATHODE VEE 9
14
1 VS VE 16
ICHG
2 VCC1 VLED 15
4 VS VCC2 13
5 CATHODE VEE 12
1 VS VE 16
+_ 7V
2 VCC1 VLED 15
5 CATHODE VEE 12
8 CATHODE VEE 9
1 VS VE 16
2 VCC1 VLED 15
4 VS VCC2 13
5 CATHODE VEE 12
VOUT
6 ANODE VOUT 11 30V
10 0.1F
+_
7 ANODE VCLAMP 10
10nF
8 CATHODE VEE 9
10mA, 10kHz,
50% Duty Cycle
15
1 VS VE 16
1 VS VE 16
5V
2 VCC1 VLED 15
RF=2.1k
SCOPE
3 FAULT DESAT 14
CF=15pF
or 1nF 30V
4 VS VCC2 13
0.1F
5 CATHODE VEE 12
10
10
6 ANODE VOUT 11
0.1F
360
7 ANODE VCLAMP 10
10nF
8 CATHODE VEE 9
1 VS VE 16
5V
2 VCC1 VLED 15
RF=2.1k
SCOPE
3 FAULT DESAT 14
CF=15pF
or 1nF 30V
4 VS VCC2 13
0.1F
5 CATHODE VEE 12
10
6 ANODE VOUT 11
0.1F
360
7 ANODE VCLAMP 10
10nF
8 CATHODE VEE 9
16
1 VS VE 16
5V
2 VCC1 VLED 15
RF=2.1k
3 FAULT DESAT 14
CF=15pF
or 1nF
30V
4 VS VCC2 13
0.1F
5 CATHODE VEE 12 SCOPE
10
10
6 ANODE VOUT 11
0.1F
360
7 ANODE VCLAMP 10
10nF
8 CATHODE VEE 9
VCM
Figure 33. CMR Test circuit LED1 off
1 VS VE 16
5V
2 VCC1 VLED 15
RF=2.1k
3 FAULT DESAT 14
CF=15pF
or 1nF
30V
4 VS VCC2 13
0.1F 5 CATHODE
5 CATHODE VEE 12 SCOPE
10 6 ANODE
6 ANODE VOUT 11 180
0.1F 5V
360 7 ANODE
7 ANODE VCLAMP 10 180
10nF
8 CATHODE
8 CATHODE VEE 9
VCM
Figure 34. CMR Test Circuit LED1 on
17
Application Information
Product Overview Description
13
The ACPL-332J is a highly integrated power control V CC2
18
1 VS VE 16
0.1F
2 VCC1 VLED 15 CBLANK
0.1F RF DDESAT
+
_ 3 FAULT DESAT 14
100
CF
4 VS VCC2 13
5 CATHODE VEE 12
+
_ + HVDC
RG +
6 ANODE VOUT 11 VCE
R Q1 -
3-PHASE
7 ANODE VCLAMP 10 RPULL--DOWN AC
+
_ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
Description of Operation
Normal Operation
During normal operation, VOUT of the ACPL-332J is con- activated is an internal feedback channel which brings
trolled by input LED current IF (pins 5, 6, 7 and 8), with the FAULT output low for the purpose of notifying the
the IGBT collector-to-emitter voltage being monitored micro-controller of the fault condition.
through DESAT. The FAULT output is high. See Figure 37.
Fault Reset
Fault Condition
Once fault is detected, the output will be muted for 5 s
The DESAT pin monitors the IGBT Vce voltage. When the (minimum). All input LED signals will be ignored during
voltage on the DESAT pin exceeds 6.5 V while the IGBT is the mute period to allow the driver to completely soft
on, VOUT is slowly brought low in order to softly turn-off shut-down the IGBT. The fault mechanism can be reset by
the IGBT and prevent large di/dt induced voltages. Also the next LED turn-on after the 5us (minimum) mute time.
See Figure 37.
IF t DESAT(LOW)
Reset done
6.5V during the next
LED turn-on
V DESAT
t BLANK t DESAT(10%)
90%
VOUT
10% t RESET(FAULT)
t DESAT(90%)
t DESAT(MUTE)
Figure 37. Fault Timing diagram
19
Output Control Slow IGBT Gate Discharge during Fault Condition
The outputs (VOUT and FAULT) of the ACPL-332J are con- When a desaturation fault is detected, a weak pull-down
trolled by the combination of IF, UVLO and a detected device in the ACPL-332J output drive stage will turn on
IGBT Desat condition. Once UVLO is not active (VCC2 - to softly turn off the IGBT. This device slowly discharges
VE > VUVLO), VOUT is allowed to go high, and the DESAT the IGBT gate to prevent fast changes in drain current
(pin 14) detection feature of the ACPL-332J will be the that could cause damaging voltage spikes due to lead
primary source of IGBT protection. Once VCC2 is increased and wire inductance. During the slow turn off, the large
from 0V to above VUVLO+, DESAT will remain functional output pull-down device remains off until the output
until VCC2 is decreased below VUVLO-. Thus, the DESAT voltage falls below VEE + 2 Volts, at which time the large
detection and UVLO features of the ACPL-332J work in pull down device clamps the IGBT gate to VEE.
conjunction to ensure constant IGBT protection.
DESAT Fault Detection Blanking Time
Desaturation Detection and High Current Protection The DESAT fault detection circuitry must remain disabled
The ACPL-332J satisfies these criteria by combining a for a short time period following the turn-on of the IGBT
high speed, high output current driver, high voltage to allow the collector voltage to fall below the DESAT
optical isolation between the input and output, local threshold. This time period, called the DESAT blanking
IGBT desaturation detection and shut down, and an time is controlled by the internal DESAT charge current,
optically isolated fault status feedback signal into a single the DESAT voltage threshold, and the external DESAT
16-pin surface mount package. capacitor.
The fault detection method, which is adopted in the The nominal blanking time is calculated in terms of
ACPL-332J, is to monitor the saturation (collector) external capacitance (CBLANK), FAULT threshold voltage
voltage of the IGBT and to trigger a local fault shutdown (VDESAT ), and DESAT charge current (ICHG) as tBLANK =
sequence if the collector voltage exceeds a predeter- CBLANK x VDESAT / ICHG. The nominal blanking time with
mined threshold. A small gate discharge device slowly the recommended 100pF capacitor is 100pF * 6.5 V / 240
reduces the high short circuit IGBT current to prevent A = 2.7 sec.
damaging voltage spikes. Before the dissipated energy
The capacitance value can be scaled slightly to adjust the
can reach destructive levels, the IGBT is shut off. During
blanking time, though a value smaller than 100 pF is not
the off state of the IGBT, the fault detect circuitry is simply
recommended. This nominal blanking time represents
disabled to prevent false fault signals.
the longest time it will take for the ACPL-332J to respond
The alternative protection scheme of measuring IGBT to a DESAT fault condition. If the IGBT is turned on while
current to prevent desaturation is effective if the short the collector and emitter are shorted to the supply rails
circuit capability of the power device is known, but (switching into a short), the soft shut-down sequence
this method will fail if the gate drive voltage decreases will begin after approximately 3 sec. If the IGBT collector
enough to only partially turn on the IGBT. By directly and emitter are shorted to the supply rails after the IGBT
measuring the collector voltage, the ACPL-332J limits the is already on, the response time will be much quicker due
power dissipation in the IGBT even with insufficient gate to the parasitic parallel capacitance of the DESAT diode.
drive voltage. Another more subtle advantage of the de- The recommended 100pF capacitor should provide
saturation detection method is that power dissipation in adequate blanking as well as fault response times for
the IGBT is monitored, while the current sense method most applications.
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
20
Under Voltage Lockout
1 VS VE 16
The ACPL-332J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate 2 VCC1 VLED 15
voltage to the IGBT by forcing the ACPL-332J output
3 FAULT DESAT 14
low during power-up. IGBTs typically require gate VCC
21
Pull-up Resistor on FAULT Pin
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ORed together with
other types of protection (e.g. over-temperature, over-
voltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
1 VS VE 16
01F 01F
2 VCC1 VLED 15
3 FAULT DESAT 14
4 VS VCC2 13
01F O R 2
5 CATHODE VEE 12
+_ + HVDC
O R 1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN _+ +
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
Figure 40. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used)
VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology
1 VS VE 16
01F 01F
2 VCC1 VLED 15
3 FAULT DESAT 14
4 VS VCC2 13
01F O R 2
5 CATHODE VEE 12
+_ + HVDC
O R 1 RG +
6 ANODE VOUT 11 VCE
Q1 -
3-PHASE
7 ANODE VCLAMP 10
AC
RPULL-DOWN +_
+
8 CATHODE VEE 9 Q2 VCE
-
- HVDC
R3
Figure 41. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
22
Thermal Model
The ACPL-332J is designed to dissipate the majority of where Pi = power into input IC and Po = power into
the heat through pins 1, 4, 5 & 8 for the input IC and pins output IC. Since 5A and 9,12A are dependent on PCB
9 & 12 for the output IC. (There are two VEE pins on the layout and airflow, their exact number may not be
output side, pins 9 and 12, for this purpose.) Heat flow available. Therefore, a more accurate method of calcu-
through other pins or through the package directly into lating the junction temperature is with the following
ambient are considered negligible and not modeled equations:
here.
Tji = Pi i5 + TP5
In order to achieve the power dissipation specified in
Tjo = Po o9,12 + TP9,12
the absolute maximum specification, it is imperative
that pins 5, 9, and 12 have ground planes connected to These equations, however, require that the pin 5 and pins
them. As long as the maximum power specification is 9, 12 temperatures be measured with a thermal couple
not exceeded, the only other limitation to the amount on the pin at the ACPL-332J package edge.
of power one can dissipate is the absolute maximum
If the calculated junction temperatures for the thermal
junction temperature specification of 125C. The junction
model in Figure 42 is higher than 125C, the pin tem-
temperatures can be calculated with the following
perature for pins 9 and 12 should be measured (at the
equations:
package edge) under worst case operating environment
Tji = Pi (i5 + 5A) + TA for a more accurate estimate of the junction tempera-
tures.
Tjo = Po (o9,12 + 9,12A) + TA
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Data subject to change. Copyright 2005-2015 Avago Technologies. All rights reserved.
AV02-0120EN - November 20, 2015